1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 */ 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/display/drm_hdmi_helper.h> 10 #include <drm/display/drm_hdmi_state_helper.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_print.h> 14 #include <drm/drm_probe_helper.h> 15 16 #include <linux/clk.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 21 #include "rk3066_hdmi.h" 22 23 #include "rockchip_drm_drv.h" 24 25 #define DEFAULT_PLLA_RATE 30000000 26 27 struct hdmi_data_info { 28 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ 29 unsigned int enc_out_format; 30 unsigned int colorimetry; 31 }; 32 33 struct rk3066_hdmi_i2c { 34 struct i2c_adapter adap; 35 36 u8 ddc_addr; 37 u8 segment_addr; 38 u8 stat; 39 40 struct mutex i2c_lock; /* For i2c operation. */ 41 struct completion cmpltn; 42 }; 43 44 struct rk3066_hdmi { 45 struct device *dev; 46 struct drm_device *drm_dev; 47 struct regmap *grf_regmap; 48 int irq; 49 struct clk *hclk; 50 void __iomem *regs; 51 52 struct drm_bridge bridge; 53 struct drm_connector *connector; 54 struct rockchip_encoder encoder; 55 56 struct rk3066_hdmi_i2c *i2c; 57 58 unsigned int tmdsclk; 59 60 struct hdmi_data_info hdmi_data; 61 }; 62 63 static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) 64 { 65 return container_of(bridge, struct rk3066_hdmi, bridge); 66 } 67 68 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) 69 { 70 return readl_relaxed(hdmi->regs + offset); 71 } 72 73 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) 74 { 75 writel_relaxed(val, hdmi->regs + offset); 76 } 77 78 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, 79 u32 msk, u32 val) 80 { 81 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 82 83 temp |= val & msk; 84 hdmi_writeb(hdmi, offset, temp); 85 } 86 87 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) 88 { 89 int ddc_bus_freq; 90 91 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; 92 93 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 94 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 95 96 /* Clear the EDID interrupt flag and mute the interrupt. */ 97 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 98 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); 99 } 100 101 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) 102 { 103 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; 104 } 105 106 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) 107 { 108 u8 current_mode, next_mode; 109 u8 i = 0; 110 111 current_mode = rk3066_hdmi_get_power_mode(hdmi); 112 113 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); 114 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); 115 116 if (current_mode == mode) 117 return; 118 119 do { 120 if (current_mode > mode) { 121 next_mode = current_mode / 2; 122 } else { 123 if (current_mode < HDMI_SYS_POWER_MODE_A) 124 next_mode = HDMI_SYS_POWER_MODE_A; 125 else 126 next_mode = current_mode * 2; 127 } 128 129 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); 130 131 if (next_mode != HDMI_SYS_POWER_MODE_D) { 132 hdmi_modb(hdmi, HDMI_SYS_CTRL, 133 HDMI_SYS_POWER_MODE_MASK, next_mode); 134 } else { 135 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 136 HDMI_SYS_POWER_MODE_D | 137 HDMI_SYS_PLL_RESET_MASK); 138 usleep_range(90, 100); 139 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 140 HDMI_SYS_POWER_MODE_D | 141 HDMI_SYS_PLLB_RESET); 142 usleep_range(90, 100); 143 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 144 HDMI_SYS_POWER_MODE_D); 145 } 146 current_mode = next_mode; 147 i = i + 1; 148 } while ((next_mode != mode) && (i < 5)); 149 150 /* 151 * When the IP controller isn't configured with accurate video timing, 152 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, 153 * so we need to init the TMDS rate to the PCLK rate and reconfigure 154 * the DDC clock. 155 */ 156 if (mode < HDMI_SYS_POWER_MODE_D) 157 hdmi->tmdsclk = DEFAULT_PLLA_RATE; 158 } 159 160 static int rk3066_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 161 { 162 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 163 164 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, HDMI_INFOFRAME_AVI); 165 166 return 0; 167 } 168 169 static int 170 rk3066_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 171 { 172 /* FIXME: add support for this InfoFrame */ 173 174 drm_warn_once(bridge->encoder->dev, "HDMI VSI not supported\n"); 175 176 return 0; 177 } 178 179 static int 180 rk3066_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, 181 const u8 *buffer, size_t len) 182 { 183 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 184 ssize_t i; 185 186 rk3066_hdmi_bridge_clear_avi_infoframe(bridge); 187 188 for (i = 0; i < len; i++) 189 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, buffer[i]); 190 191 return 0; 192 } 193 194 static int 195 rk3066_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 196 const u8 *buffer, size_t len) 197 { 198 rk3066_hdmi_bridge_clear_hdmi_infoframe(bridge); 199 200 /* FIXME: add support for this InfoFrame */ 201 202 return 0; 203 } 204 205 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, 206 struct drm_display_mode *mode) 207 { 208 int value, vsync_offset; 209 210 /* Set the details for the external polarity and interlace mode. */ 211 value = HDMI_EXT_VIDEO_SET_EN; 212 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 213 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; 214 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 215 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; 216 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 217 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; 218 219 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) 220 vsync_offset = 6; 221 else 222 vsync_offset = 0; 223 224 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; 225 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); 226 227 /* Set the details for the external video timing. */ 228 value = mode->htotal; 229 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); 230 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); 231 232 value = mode->htotal - mode->hdisplay; 233 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); 234 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); 235 236 value = mode->htotal - mode->hsync_start; 237 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); 238 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); 239 240 value = mode->hsync_end - mode->hsync_start; 241 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); 242 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); 243 244 value = mode->vtotal; 245 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); 246 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); 247 248 value = mode->vtotal - mode->vdisplay; 249 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); 250 251 value = mode->vtotal - mode->vsync_start + vsync_offset; 252 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); 253 254 value = mode->vsync_end - mode->vsync_start; 255 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); 256 257 return 0; 258 } 259 260 static void 261 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) 262 { 263 hdmi_writeb(hdmi, offset, value); 264 hdmi_modb(hdmi, HDMI_SYS_CTRL, 265 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); 266 usleep_range(90, 100); 267 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); 268 usleep_range(900, 1000); 269 } 270 271 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) 272 { 273 /* TMDS uses the same frequency as dclk. */ 274 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); 275 276 /* 277 * The semi-public documentation does not describe the hdmi registers 278 * used by the function rk3066_hdmi_phy_write(), so we keep using 279 * these magic values for now. 280 */ 281 if (hdmi->tmdsclk > 100000000) { 282 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); 283 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 284 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 285 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 286 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); 287 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); 288 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 289 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); 290 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 291 } else if (hdmi->tmdsclk > 50000000) { 292 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); 293 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 294 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 295 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 296 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); 297 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); 298 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 299 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 300 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 301 } else { 302 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); 303 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 304 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 305 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 306 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); 307 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); 308 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 309 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 310 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 311 } 312 } 313 314 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, 315 struct drm_atomic_commit *state) 316 { 317 struct drm_bridge *bridge = &hdmi->bridge; 318 struct drm_connector *connector; 319 struct drm_display_info *display; 320 struct drm_display_mode *mode; 321 struct drm_connector_state *new_conn_state; 322 struct drm_crtc_state *new_crtc_state; 323 324 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 325 326 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 327 if (WARN_ON(!new_conn_state)) 328 return -EINVAL; 329 330 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 331 if (WARN_ON(!new_crtc_state)) 332 return -EINVAL; 333 334 display = &connector->display_info; 335 mode = &new_crtc_state->adjusted_mode; 336 337 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 338 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 339 340 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || 341 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || 342 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || 343 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) 344 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 345 else 346 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 347 348 hdmi->tmdsclk = mode->clock * 1000; 349 350 /* Mute video and audio output. */ 351 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, 352 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); 353 354 /* Set power state to mode B. */ 355 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) 356 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 357 358 /* Input video mode is RGB 24 bit. Use external data enable signal. */ 359 hdmi_modb(hdmi, HDMI_AV_CTRL1, 360 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); 361 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, 362 HDMI_VIDEO_OUTPUT_RGB444 | 363 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | 364 HDMI_VIDEO_INPUT_COLOR_RGB); 365 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); 366 367 rk3066_hdmi_config_video_timing(hdmi, mode); 368 369 if (display->is_hdmi) { 370 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 371 HDMI_VIDEO_MODE_HDMI); 372 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 373 } else { 374 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); 375 } 376 377 rk3066_hdmi_config_phy(hdmi); 378 379 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); 380 381 /* 382 * When the IP controller is configured with accurate video 383 * timing, the TMDS clock source should be switched to 384 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode 385 * clock rate and reconfigure the DDC clock. 386 */ 387 rk3066_hdmi_i2c_init(hdmi); 388 389 /* Unmute video output. */ 390 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 391 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); 392 return 0; 393 } 394 395 static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 396 struct drm_atomic_commit *state) 397 { 398 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 399 struct drm_connector_state *conn_state; 400 struct drm_crtc_state *crtc_state; 401 int mux, val; 402 403 conn_state = drm_atomic_get_new_connector_state(state, hdmi->connector); 404 if (WARN_ON(!conn_state)) 405 return; 406 407 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 408 if (WARN_ON(!crtc_state)) 409 return; 410 411 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, &hdmi->encoder.encoder); 412 if (mux) 413 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; 414 else 415 val = HDMI_VIDEO_SEL << 16; 416 417 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); 418 419 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", 420 (mux) ? "1" : "0"); 421 422 rk3066_hdmi_setup(hdmi, state); 423 } 424 425 static void rk3066_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 426 struct drm_atomic_commit *state) 427 { 428 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 429 430 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); 431 432 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { 433 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, 434 HDMI_VIDEO_AUDIO_DISABLE_MASK); 435 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 436 HDMI_AUDIO_CP_LOGIC_RESET_MASK, 437 HDMI_AUDIO_CP_LOGIC_RESET); 438 usleep_range(500, 510); 439 } 440 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 441 } 442 443 static int 444 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 445 struct drm_crtc_state *crtc_state, 446 struct drm_connector_state *conn_state) 447 { 448 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 449 450 s->output_mode = ROCKCHIP_OUT_MODE_P888; 451 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 452 453 return 0; 454 } 455 456 static const struct drm_encoder_funcs rk3066_hdmi_encoder_funcs = { 457 .destroy = drm_encoder_cleanup, 458 }; 459 460 static const 461 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { 462 .atomic_check = rk3066_hdmi_encoder_atomic_check, 463 }; 464 465 static enum drm_connector_status 466 rk3066_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 467 { 468 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 469 470 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? 471 connector_status_connected : connector_status_disconnected; 472 } 473 474 static const struct drm_edid * 475 rk3066_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) 476 { 477 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 478 const struct drm_edid *drm_edid; 479 480 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 481 if (!drm_edid) 482 dev_dbg(hdmi->dev, "failed to get edid\n"); 483 484 return drm_edid; 485 } 486 487 static enum drm_mode_status 488 rk3066_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 489 const struct drm_display_info *info, 490 const struct drm_display_mode *mode) 491 { 492 u32 vic = drm_match_cea_mode(mode); 493 494 if (vic > 1) 495 return MODE_OK; 496 else 497 return MODE_BAD; 498 } 499 500 static const struct drm_bridge_funcs rk3066_hdmi_bridge_funcs = { 501 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 502 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 503 .atomic_create_state = drm_atomic_helper_bridge_create_state, 504 .atomic_enable = rk3066_hdmi_bridge_atomic_enable, 505 .atomic_disable = rk3066_hdmi_bridge_atomic_disable, 506 .detect = rk3066_hdmi_bridge_detect, 507 .edid_read = rk3066_hdmi_bridge_edid_read, 508 .hdmi_clear_avi_infoframe = rk3066_hdmi_bridge_clear_avi_infoframe, 509 .hdmi_write_avi_infoframe = rk3066_hdmi_bridge_write_avi_infoframe, 510 .hdmi_clear_hdmi_infoframe = rk3066_hdmi_bridge_clear_hdmi_infoframe, 511 .hdmi_write_hdmi_infoframe = rk3066_hdmi_bridge_write_hdmi_infoframe, 512 .mode_valid = rk3066_hdmi_bridge_mode_valid, 513 }; 514 515 516 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) 517 { 518 struct rk3066_hdmi *hdmi = dev_id; 519 irqreturn_t ret = IRQ_NONE; 520 u8 interrupt; 521 522 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) 523 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); 524 525 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); 526 if (interrupt) 527 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); 528 529 if (interrupt & HDMI_INTR_EDID_MASK) { 530 hdmi->i2c->stat = interrupt; 531 complete(&hdmi->i2c->cmpltn); 532 } 533 534 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) 535 ret = IRQ_WAKE_THREAD; 536 537 return ret; 538 } 539 540 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) 541 { 542 struct rk3066_hdmi *hdmi = dev_id; 543 544 drm_helper_hpd_irq_event(hdmi->connector->dev); 545 546 return IRQ_HANDLED; 547 } 548 549 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 550 { 551 int length = msgs->len; 552 u8 *buf = msgs->buf; 553 int ret; 554 555 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); 556 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) 557 return -EAGAIN; 558 559 while (length--) 560 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); 561 562 return 0; 563 } 564 565 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 566 { 567 /* 568 * The DDC module only supports read EDID message, so 569 * we assume that each word write to this i2c adapter 570 * should be the offset of the EDID word address. 571 */ 572 if (msgs->len != 1 || 573 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 574 return -EINVAL; 575 576 reinit_completion(&hdmi->i2c->cmpltn); 577 578 if (msgs->addr == DDC_SEGMENT_ADDR) 579 hdmi->i2c->segment_addr = msgs->buf[0]; 580 if (msgs->addr == DDC_ADDR) 581 hdmi->i2c->ddc_addr = msgs->buf[0]; 582 583 /* Set edid fifo first address. */ 584 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); 585 586 /* Set edid word address 0x00/0x80. */ 587 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 588 589 /* Set edid segment pointer. */ 590 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 591 592 return 0; 593 } 594 595 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, 596 struct i2c_msg *msgs, int num) 597 { 598 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); 599 struct rk3066_hdmi_i2c *i2c = hdmi->i2c; 600 int i, ret = 0; 601 602 mutex_lock(&i2c->i2c_lock); 603 604 rk3066_hdmi_i2c_init(hdmi); 605 606 /* Unmute HDMI EDID interrupt. */ 607 hdmi_modb(hdmi, HDMI_INTR_MASK1, 608 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); 609 i2c->stat = 0; 610 611 for (i = 0; i < num; i++) { 612 DRM_DEV_DEBUG(hdmi->dev, 613 "xfer: num: %d/%d, len: %d, flags: %#x\n", 614 i + 1, num, msgs[i].len, msgs[i].flags); 615 616 if (msgs[i].flags & I2C_M_RD) 617 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); 618 else 619 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); 620 621 if (ret < 0) 622 break; 623 } 624 625 if (!ret) 626 ret = num; 627 628 /* Mute HDMI EDID interrupt. */ 629 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 630 631 mutex_unlock(&i2c->i2c_lock); 632 633 return ret; 634 } 635 636 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) 637 { 638 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 639 } 640 641 static const struct i2c_algorithm rk3066_hdmi_algorithm = { 642 .master_xfer = rk3066_hdmi_i2c_xfer, 643 .functionality = rk3066_hdmi_i2c_func, 644 }; 645 646 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) 647 { 648 struct i2c_adapter *adap; 649 struct rk3066_hdmi_i2c *i2c; 650 int ret; 651 652 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 653 if (!i2c) 654 return ERR_PTR(-ENOMEM); 655 656 mutex_init(&i2c->i2c_lock); 657 init_completion(&i2c->cmpltn); 658 659 adap = &i2c->adap; 660 adap->owner = THIS_MODULE; 661 adap->dev.parent = hdmi->dev; 662 adap->dev.of_node = hdmi->dev->of_node; 663 adap->algo = &rk3066_hdmi_algorithm; 664 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); 665 i2c_set_adapdata(adap, hdmi); 666 667 ret = devm_i2c_add_adapter(hdmi->dev, adap); 668 if (ret) { 669 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", 670 adap->name); 671 devm_kfree(hdmi->dev, i2c); 672 return ERR_PTR(ret); 673 } 674 675 hdmi->i2c = i2c; 676 677 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 678 679 return adap; 680 } 681 682 static int 683 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) 684 { 685 struct drm_encoder *encoder = &hdmi->encoder.encoder; 686 struct device *dev = hdmi->dev; 687 int ret; 688 689 encoder->possible_crtcs = 690 drm_of_find_possible_crtcs(drm, dev->of_node); 691 692 /* 693 * If we failed to find the CRTC(s) which this encoder is 694 * supposed to be connected to, it's because the CRTC has 695 * not been registered yet. Defer probing, and hope that 696 * the required CRTC is added later. 697 */ 698 if (encoder->possible_crtcs == 0) 699 return -EPROBE_DEFER; 700 701 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); 702 drm_encoder_init(drm, encoder, &rk3066_hdmi_encoder_funcs, 703 DRM_MODE_ENCODER_TMDS, NULL); 704 705 hdmi->bridge.driver_private = hdmi; 706 hdmi->bridge.funcs = &rk3066_hdmi_bridge_funcs; 707 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 708 DRM_BRIDGE_OP_EDID | 709 DRM_BRIDGE_OP_HDMI | 710 DRM_BRIDGE_OP_HPD; 711 hdmi->bridge.of_node = hdmi->dev->of_node; 712 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 713 hdmi->bridge.vendor = "Rockchip"; 714 hdmi->bridge.product = "RK3066 HDMI"; 715 716 hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi); 717 if (IS_ERR(hdmi->bridge.ddc)) 718 return PTR_ERR(hdmi->bridge.ddc); 719 720 if (IS_ERR(hdmi->bridge.ddc)) 721 return PTR_ERR(hdmi->bridge.ddc); 722 723 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 724 if (ret) 725 return ret; 726 727 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 728 if (ret) 729 return ret; 730 731 hdmi->connector = drm_bridge_connector_init(drm, encoder); 732 if (IS_ERR(hdmi->connector)) { 733 ret = PTR_ERR(hdmi->connector); 734 dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret); 735 return ret; 736 } 737 738 return 0; 739 } 740 741 static int rk3066_hdmi_bind(struct device *dev, struct device *master, 742 void *data) 743 { 744 struct platform_device *pdev = to_platform_device(dev); 745 struct drm_device *drm = data; 746 struct rk3066_hdmi *hdmi; 747 int irq; 748 int ret; 749 750 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 751 if (!hdmi) 752 return -ENOMEM; 753 754 hdmi->dev = dev; 755 hdmi->drm_dev = drm; 756 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 757 if (IS_ERR(hdmi->regs)) 758 return PTR_ERR(hdmi->regs); 759 760 irq = platform_get_irq(pdev, 0); 761 if (irq < 0) 762 return irq; 763 764 hdmi->hclk = devm_clk_get(dev, "hclk"); 765 if (IS_ERR(hdmi->hclk)) { 766 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); 767 return PTR_ERR(hdmi->hclk); 768 } 769 770 ret = clk_prepare_enable(hdmi->hclk); 771 if (ret) { 772 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); 773 return ret; 774 } 775 776 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 777 "rockchip,grf"); 778 if (IS_ERR(hdmi->grf_regmap)) { 779 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); 780 ret = PTR_ERR(hdmi->grf_regmap); 781 goto err_disable_hclk; 782 } 783 784 /* internal hclk = hdmi_hclk / 25 */ 785 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); 786 787 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 788 usleep_range(999, 1000); 789 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); 790 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); 791 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); 792 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); 793 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 794 795 ret = rk3066_hdmi_register(drm, hdmi); 796 if (ret) 797 goto err_disable_hclk; 798 799 dev_set_drvdata(dev, hdmi); 800 801 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, 802 rk3066_hdmi_irq, IRQF_SHARED, 803 dev_name(dev), hdmi); 804 if (ret) { 805 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); 806 goto err_cleanup_hdmi; 807 } 808 809 return 0; 810 811 err_cleanup_hdmi: 812 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 813 err_disable_hclk: 814 clk_disable_unprepare(hdmi->hclk); 815 816 return ret; 817 } 818 819 static void rk3066_hdmi_unbind(struct device *dev, struct device *master, 820 void *data) 821 { 822 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); 823 824 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 825 826 clk_disable_unprepare(hdmi->hclk); 827 } 828 829 static const struct component_ops rk3066_hdmi_ops = { 830 .bind = rk3066_hdmi_bind, 831 .unbind = rk3066_hdmi_unbind, 832 }; 833 834 static int rk3066_hdmi_probe(struct platform_device *pdev) 835 { 836 return component_add(&pdev->dev, &rk3066_hdmi_ops); 837 } 838 839 static void rk3066_hdmi_remove(struct platform_device *pdev) 840 { 841 component_del(&pdev->dev, &rk3066_hdmi_ops); 842 } 843 844 static const struct of_device_id rk3066_hdmi_dt_ids[] = { 845 { .compatible = "rockchip,rk3066-hdmi" }, 846 { /* sentinel */ }, 847 }; 848 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); 849 850 struct platform_driver rk3066_hdmi_driver = { 851 .probe = rk3066_hdmi_probe, 852 .remove = rk3066_hdmi_remove, 853 .driver = { 854 .name = "rockchip-rk3066-hdmi", 855 .of_match_table = rk3066_hdmi_dt_ids, 856 }, 857 }; 858