1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 */ 6 7 #include <drm/drm_atomic.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/display/drm_hdmi_helper.h> 10 #include <drm/display/drm_hdmi_state_helper.h> 11 #include <drm/drm_edid.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_print.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_simple_kms_helper.h> 16 17 #include <linux/clk.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 #include "rk3066_hdmi.h" 23 24 #include "rockchip_drm_drv.h" 25 26 #define DEFAULT_PLLA_RATE 30000000 27 28 struct hdmi_data_info { 29 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */ 30 unsigned int enc_out_format; 31 unsigned int colorimetry; 32 }; 33 34 struct rk3066_hdmi_i2c { 35 struct i2c_adapter adap; 36 37 u8 ddc_addr; 38 u8 segment_addr; 39 u8 stat; 40 41 struct mutex i2c_lock; /* For i2c operation. */ 42 struct completion cmpltn; 43 }; 44 45 struct rk3066_hdmi { 46 struct device *dev; 47 struct drm_device *drm_dev; 48 struct regmap *grf_regmap; 49 int irq; 50 struct clk *hclk; 51 void __iomem *regs; 52 53 struct drm_bridge bridge; 54 struct drm_connector *connector; 55 struct rockchip_encoder encoder; 56 57 struct rk3066_hdmi_i2c *i2c; 58 59 unsigned int tmdsclk; 60 61 struct hdmi_data_info hdmi_data; 62 }; 63 64 static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) 65 { 66 return container_of(bridge, struct rk3066_hdmi, bridge); 67 } 68 69 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) 70 { 71 return readl_relaxed(hdmi->regs + offset); 72 } 73 74 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) 75 { 76 writel_relaxed(val, hdmi->regs + offset); 77 } 78 79 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, 80 u32 msk, u32 val) 81 { 82 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 83 84 temp |= val & msk; 85 hdmi_writeb(hdmi, offset, temp); 86 } 87 88 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) 89 { 90 int ddc_bus_freq; 91 92 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; 93 94 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 95 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 96 97 /* Clear the EDID interrupt flag and mute the interrupt. */ 98 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 99 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK); 100 } 101 102 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi) 103 { 104 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK; 105 } 106 107 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode) 108 { 109 u8 current_mode, next_mode; 110 u8 i = 0; 111 112 current_mode = rk3066_hdmi_get_power_mode(hdmi); 113 114 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode); 115 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode); 116 117 if (current_mode == mode) 118 return; 119 120 do { 121 if (current_mode > mode) { 122 next_mode = current_mode / 2; 123 } else { 124 if (current_mode < HDMI_SYS_POWER_MODE_A) 125 next_mode = HDMI_SYS_POWER_MODE_A; 126 else 127 next_mode = current_mode * 2; 128 } 129 130 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode); 131 132 if (next_mode != HDMI_SYS_POWER_MODE_D) { 133 hdmi_modb(hdmi, HDMI_SYS_CTRL, 134 HDMI_SYS_POWER_MODE_MASK, next_mode); 135 } else { 136 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 137 HDMI_SYS_POWER_MODE_D | 138 HDMI_SYS_PLL_RESET_MASK); 139 usleep_range(90, 100); 140 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 141 HDMI_SYS_POWER_MODE_D | 142 HDMI_SYS_PLLB_RESET); 143 usleep_range(90, 100); 144 hdmi_writeb(hdmi, HDMI_SYS_CTRL, 145 HDMI_SYS_POWER_MODE_D); 146 } 147 current_mode = next_mode; 148 i = i + 1; 149 } while ((next_mode != mode) && (i < 5)); 150 151 /* 152 * When the IP controller isn't configured with accurate video timing, 153 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz, 154 * so we need to init the TMDS rate to the PCLK rate and reconfigure 155 * the DDC clock. 156 */ 157 if (mode < HDMI_SYS_POWER_MODE_D) 158 hdmi->tmdsclk = DEFAULT_PLLA_RATE; 159 } 160 161 static int rk3066_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 162 { 163 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 164 165 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, HDMI_INFOFRAME_AVI); 166 167 return 0; 168 } 169 170 static int 171 rk3066_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 172 { 173 /* FIXME: add support for this InfoFrame */ 174 175 drm_warn_once(bridge->encoder->dev, "HDMI VSI not supported\n"); 176 177 return 0; 178 } 179 180 static int 181 rk3066_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, 182 const u8 *buffer, size_t len) 183 { 184 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 185 ssize_t i; 186 187 rk3066_hdmi_bridge_clear_avi_infoframe(bridge); 188 189 for (i = 0; i < len; i++) 190 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, buffer[i]); 191 192 return 0; 193 } 194 195 static int 196 rk3066_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 197 const u8 *buffer, size_t len) 198 { 199 rk3066_hdmi_bridge_clear_hdmi_infoframe(bridge); 200 201 /* FIXME: add support for this InfoFrame */ 202 203 return 0; 204 } 205 206 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi, 207 struct drm_display_mode *mode) 208 { 209 int value, vsync_offset; 210 211 /* Set the details for the external polarity and interlace mode. */ 212 value = HDMI_EXT_VIDEO_SET_EN; 213 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 214 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW; 215 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 216 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW; 217 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 218 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE; 219 220 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3) 221 vsync_offset = 6; 222 else 223 vsync_offset = 0; 224 225 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT; 226 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value); 227 228 /* Set the details for the external video timing. */ 229 value = mode->htotal; 230 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF); 231 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF); 232 233 value = mode->htotal - mode->hdisplay; 234 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF); 235 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF); 236 237 value = mode->htotal - mode->hsync_start; 238 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF); 239 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF); 240 241 value = mode->hsync_end - mode->hsync_start; 242 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF); 243 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF); 244 245 value = mode->vtotal; 246 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF); 247 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF); 248 249 value = mode->vtotal - mode->vdisplay; 250 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF); 251 252 value = mode->vtotal - mode->vsync_start + vsync_offset; 253 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF); 254 255 value = mode->vsync_end - mode->vsync_start; 256 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF); 257 258 return 0; 259 } 260 261 static void 262 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value) 263 { 264 hdmi_writeb(hdmi, offset, value); 265 hdmi_modb(hdmi, HDMI_SYS_CTRL, 266 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET); 267 usleep_range(90, 100); 268 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0); 269 usleep_range(900, 1000); 270 } 271 272 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi) 273 { 274 /* TMDS uses the same frequency as dclk. */ 275 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22); 276 277 /* 278 * The semi-public documentation does not describe the hdmi registers 279 * used by the function rk3066_hdmi_phy_write(), so we keep using 280 * these magic values for now. 281 */ 282 if (hdmi->tmdsclk > 100000000) { 283 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E); 284 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 285 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 286 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 287 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA); 288 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1); 289 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 290 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22); 291 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 292 } else if (hdmi->tmdsclk > 50000000) { 293 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06); 294 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 295 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 296 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 297 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA); 298 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3); 299 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 300 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 301 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 302 } else { 303 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02); 304 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00); 305 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60); 306 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00); 307 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2); 308 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2); 309 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e); 310 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20); 311 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00); 312 } 313 } 314 315 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi, 316 struct drm_atomic_state *state) 317 { 318 struct drm_bridge *bridge = &hdmi->bridge; 319 struct drm_connector *connector; 320 struct drm_display_info *display; 321 struct drm_display_mode *mode; 322 struct drm_connector_state *new_conn_state; 323 struct drm_crtc_state *new_crtc_state; 324 325 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 326 327 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 328 if (WARN_ON(!new_conn_state)) 329 return -EINVAL; 330 331 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 332 if (WARN_ON(!new_crtc_state)) 333 return -EINVAL; 334 335 display = &connector->display_info; 336 mode = &new_crtc_state->adjusted_mode; 337 338 hdmi->hdmi_data.vic = drm_match_cea_mode(mode); 339 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB; 340 341 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 || 342 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 || 343 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 || 344 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18) 345 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; 346 else 347 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; 348 349 hdmi->tmdsclk = mode->clock * 1000; 350 351 /* Mute video and audio output. */ 352 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK, 353 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE); 354 355 /* Set power state to mode B. */ 356 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B) 357 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 358 359 /* Input video mode is RGB 24 bit. Use external data enable signal. */ 360 hdmi_modb(hdmi, HDMI_AV_CTRL1, 361 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE); 362 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1, 363 HDMI_VIDEO_OUTPUT_RGB444 | 364 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT | 365 HDMI_VIDEO_INPUT_COLOR_RGB); 366 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20); 367 368 rk3066_hdmi_config_video_timing(hdmi, mode); 369 370 if (display->is_hdmi) { 371 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 372 HDMI_VIDEO_MODE_HDMI); 373 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 374 } else { 375 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0); 376 } 377 378 rk3066_hdmi_config_phy(hdmi); 379 380 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E); 381 382 /* 383 * When the IP controller is configured with accurate video 384 * timing, the TMDS clock source should be switched to 385 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode 386 * clock rate and reconfigure the DDC clock. 387 */ 388 rk3066_hdmi_i2c_init(hdmi); 389 390 /* Unmute video output. */ 391 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 392 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE); 393 return 0; 394 } 395 396 static void rk3066_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 397 struct drm_atomic_state *state) 398 { 399 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 400 struct drm_connector_state *conn_state; 401 struct drm_crtc_state *crtc_state; 402 int mux, val; 403 404 conn_state = drm_atomic_get_new_connector_state(state, hdmi->connector); 405 if (WARN_ON(!conn_state)) 406 return; 407 408 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 409 if (WARN_ON(!crtc_state)) 410 return; 411 412 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, &hdmi->encoder.encoder); 413 if (mux) 414 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL; 415 else 416 val = HDMI_VIDEO_SEL << 16; 417 418 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val); 419 420 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n", 421 (mux) ? "1" : "0"); 422 423 rk3066_hdmi_setup(hdmi, state); 424 } 425 426 static void rk3066_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 427 struct drm_atomic_state *state) 428 { 429 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 430 431 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n"); 432 433 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) { 434 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2, 435 HDMI_VIDEO_AUDIO_DISABLE_MASK); 436 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, 437 HDMI_AUDIO_CP_LOGIC_RESET_MASK, 438 HDMI_AUDIO_CP_LOGIC_RESET); 439 usleep_range(500, 510); 440 } 441 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 442 } 443 444 static int 445 rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 446 struct drm_crtc_state *crtc_state, 447 struct drm_connector_state *conn_state) 448 { 449 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 450 451 s->output_mode = ROCKCHIP_OUT_MODE_P888; 452 s->output_type = DRM_MODE_CONNECTOR_HDMIA; 453 454 return 0; 455 } 456 457 static const 458 struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = { 459 .atomic_check = rk3066_hdmi_encoder_atomic_check, 460 }; 461 462 static enum drm_connector_status 463 rk3066_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 464 { 465 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 466 467 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ? 468 connector_status_connected : connector_status_disconnected; 469 } 470 471 static const struct drm_edid * 472 rk3066_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) 473 { 474 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge); 475 const struct drm_edid *drm_edid; 476 477 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 478 if (!drm_edid) 479 dev_dbg(hdmi->dev, "failed to get edid\n"); 480 481 return drm_edid; 482 } 483 484 static enum drm_mode_status 485 rk3066_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 486 const struct drm_display_info *info, 487 const struct drm_display_mode *mode) 488 { 489 u32 vic = drm_match_cea_mode(mode); 490 491 if (vic > 1) 492 return MODE_OK; 493 else 494 return MODE_BAD; 495 } 496 497 static const struct drm_bridge_funcs rk3066_hdmi_bridge_funcs = { 498 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 499 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 500 .atomic_reset = drm_atomic_helper_bridge_reset, 501 .atomic_enable = rk3066_hdmi_bridge_atomic_enable, 502 .atomic_disable = rk3066_hdmi_bridge_atomic_disable, 503 .detect = rk3066_hdmi_bridge_detect, 504 .edid_read = rk3066_hdmi_bridge_edid_read, 505 .hdmi_clear_avi_infoframe = rk3066_hdmi_bridge_clear_avi_infoframe, 506 .hdmi_write_avi_infoframe = rk3066_hdmi_bridge_write_avi_infoframe, 507 .hdmi_clear_hdmi_infoframe = rk3066_hdmi_bridge_clear_hdmi_infoframe, 508 .hdmi_write_hdmi_infoframe = rk3066_hdmi_bridge_write_hdmi_infoframe, 509 .mode_valid = rk3066_hdmi_bridge_mode_valid, 510 }; 511 512 513 static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id) 514 { 515 struct rk3066_hdmi *hdmi = dev_id; 516 irqreturn_t ret = IRQ_NONE; 517 u8 interrupt; 518 519 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A) 520 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B); 521 522 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1); 523 if (interrupt) 524 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt); 525 526 if (interrupt & HDMI_INTR_EDID_MASK) { 527 hdmi->i2c->stat = interrupt; 528 complete(&hdmi->i2c->cmpltn); 529 } 530 531 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS)) 532 ret = IRQ_WAKE_THREAD; 533 534 return ret; 535 } 536 537 static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id) 538 { 539 struct rk3066_hdmi *hdmi = dev_id; 540 541 drm_helper_hpd_irq_event(hdmi->connector->dev); 542 543 return IRQ_HANDLED; 544 } 545 546 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 547 { 548 int length = msgs->len; 549 u8 *buf = msgs->buf; 550 int ret; 551 552 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10); 553 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR) 554 return -EAGAIN; 555 556 while (length--) 557 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR); 558 559 return 0; 560 } 561 562 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs) 563 { 564 /* 565 * The DDC module only supports read EDID message, so 566 * we assume that each word write to this i2c adapter 567 * should be the offset of the EDID word address. 568 */ 569 if (msgs->len != 1 || 570 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 571 return -EINVAL; 572 573 reinit_completion(&hdmi->i2c->cmpltn); 574 575 if (msgs->addr == DDC_SEGMENT_ADDR) 576 hdmi->i2c->segment_addr = msgs->buf[0]; 577 if (msgs->addr == DDC_ADDR) 578 hdmi->i2c->ddc_addr = msgs->buf[0]; 579 580 /* Set edid fifo first address. */ 581 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00); 582 583 /* Set edid word address 0x00/0x80. */ 584 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 585 586 /* Set edid segment pointer. */ 587 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 588 589 return 0; 590 } 591 592 static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap, 593 struct i2c_msg *msgs, int num) 594 { 595 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap); 596 struct rk3066_hdmi_i2c *i2c = hdmi->i2c; 597 int i, ret = 0; 598 599 mutex_lock(&i2c->i2c_lock); 600 601 rk3066_hdmi_i2c_init(hdmi); 602 603 /* Unmute HDMI EDID interrupt. */ 604 hdmi_modb(hdmi, HDMI_INTR_MASK1, 605 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK); 606 i2c->stat = 0; 607 608 for (i = 0; i < num; i++) { 609 DRM_DEV_DEBUG(hdmi->dev, 610 "xfer: num: %d/%d, len: %d, flags: %#x\n", 611 i + 1, num, msgs[i].len, msgs[i].flags); 612 613 if (msgs[i].flags & I2C_M_RD) 614 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]); 615 else 616 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]); 617 618 if (ret < 0) 619 break; 620 } 621 622 if (!ret) 623 ret = num; 624 625 /* Mute HDMI EDID interrupt. */ 626 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0); 627 628 mutex_unlock(&i2c->i2c_lock); 629 630 return ret; 631 } 632 633 static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter) 634 { 635 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 636 } 637 638 static const struct i2c_algorithm rk3066_hdmi_algorithm = { 639 .master_xfer = rk3066_hdmi_i2c_xfer, 640 .functionality = rk3066_hdmi_i2c_func, 641 }; 642 643 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi) 644 { 645 struct i2c_adapter *adap; 646 struct rk3066_hdmi_i2c *i2c; 647 int ret; 648 649 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 650 if (!i2c) 651 return ERR_PTR(-ENOMEM); 652 653 mutex_init(&i2c->i2c_lock); 654 init_completion(&i2c->cmpltn); 655 656 adap = &i2c->adap; 657 adap->owner = THIS_MODULE; 658 adap->dev.parent = hdmi->dev; 659 adap->dev.of_node = hdmi->dev->of_node; 660 adap->algo = &rk3066_hdmi_algorithm; 661 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name)); 662 i2c_set_adapdata(adap, hdmi); 663 664 ret = devm_i2c_add_adapter(hdmi->dev, adap); 665 if (ret) { 666 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n", 667 adap->name); 668 devm_kfree(hdmi->dev, i2c); 669 return ERR_PTR(ret); 670 } 671 672 hdmi->i2c = i2c; 673 674 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 675 676 return adap; 677 } 678 679 static int 680 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi) 681 { 682 struct drm_encoder *encoder = &hdmi->encoder.encoder; 683 struct device *dev = hdmi->dev; 684 int ret; 685 686 encoder->possible_crtcs = 687 drm_of_find_possible_crtcs(drm, dev->of_node); 688 689 /* 690 * If we failed to find the CRTC(s) which this encoder is 691 * supposed to be connected to, it's because the CRTC has 692 * not been registered yet. Defer probing, and hope that 693 * the required CRTC is added later. 694 */ 695 if (encoder->possible_crtcs == 0) 696 return -EPROBE_DEFER; 697 698 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs); 699 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 700 701 hdmi->bridge.driver_private = hdmi; 702 hdmi->bridge.funcs = &rk3066_hdmi_bridge_funcs; 703 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 704 DRM_BRIDGE_OP_EDID | 705 DRM_BRIDGE_OP_HDMI | 706 DRM_BRIDGE_OP_HPD; 707 hdmi->bridge.of_node = hdmi->dev->of_node; 708 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 709 hdmi->bridge.vendor = "Rockchip"; 710 hdmi->bridge.product = "RK3066 HDMI"; 711 712 hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi); 713 if (IS_ERR(hdmi->bridge.ddc)) 714 return PTR_ERR(hdmi->bridge.ddc); 715 716 if (IS_ERR(hdmi->bridge.ddc)) 717 return PTR_ERR(hdmi->bridge.ddc); 718 719 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 720 if (ret) 721 return ret; 722 723 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 724 if (ret) 725 return ret; 726 727 hdmi->connector = drm_bridge_connector_init(drm, encoder); 728 if (IS_ERR(hdmi->connector)) { 729 ret = PTR_ERR(hdmi->connector); 730 dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret); 731 return ret; 732 } 733 734 drm_connector_attach_encoder(hdmi->connector, encoder); 735 736 return 0; 737 } 738 739 static int rk3066_hdmi_bind(struct device *dev, struct device *master, 740 void *data) 741 { 742 struct platform_device *pdev = to_platform_device(dev); 743 struct drm_device *drm = data; 744 struct rk3066_hdmi *hdmi; 745 int irq; 746 int ret; 747 748 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 749 if (!hdmi) 750 return -ENOMEM; 751 752 hdmi->dev = dev; 753 hdmi->drm_dev = drm; 754 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 755 if (IS_ERR(hdmi->regs)) 756 return PTR_ERR(hdmi->regs); 757 758 irq = platform_get_irq(pdev, 0); 759 if (irq < 0) 760 return irq; 761 762 hdmi->hclk = devm_clk_get(dev, "hclk"); 763 if (IS_ERR(hdmi->hclk)) { 764 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n"); 765 return PTR_ERR(hdmi->hclk); 766 } 767 768 ret = clk_prepare_enable(hdmi->hclk); 769 if (ret) { 770 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret); 771 return ret; 772 } 773 774 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, 775 "rockchip,grf"); 776 if (IS_ERR(hdmi->grf_regmap)) { 777 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n"); 778 ret = PTR_ERR(hdmi->grf_regmap); 779 goto err_disable_hclk; 780 } 781 782 /* internal hclk = hdmi_hclk / 25 */ 783 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25); 784 785 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B); 786 usleep_range(999, 1000); 787 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG); 788 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0); 789 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0); 790 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0); 791 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A); 792 793 ret = rk3066_hdmi_register(drm, hdmi); 794 if (ret) 795 goto err_disable_hclk; 796 797 dev_set_drvdata(dev, hdmi); 798 799 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq, 800 rk3066_hdmi_irq, IRQF_SHARED, 801 dev_name(dev), hdmi); 802 if (ret) { 803 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret); 804 goto err_cleanup_hdmi; 805 } 806 807 return 0; 808 809 err_cleanup_hdmi: 810 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 811 err_disable_hclk: 812 clk_disable_unprepare(hdmi->hclk); 813 814 return ret; 815 } 816 817 static void rk3066_hdmi_unbind(struct device *dev, struct device *master, 818 void *data) 819 { 820 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev); 821 822 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); 823 824 clk_disable_unprepare(hdmi->hclk); 825 } 826 827 static const struct component_ops rk3066_hdmi_ops = { 828 .bind = rk3066_hdmi_bind, 829 .unbind = rk3066_hdmi_unbind, 830 }; 831 832 static int rk3066_hdmi_probe(struct platform_device *pdev) 833 { 834 return component_add(&pdev->dev, &rk3066_hdmi_ops); 835 } 836 837 static void rk3066_hdmi_remove(struct platform_device *pdev) 838 { 839 component_del(&pdev->dev, &rk3066_hdmi_ops); 840 } 841 842 static const struct of_device_id rk3066_hdmi_dt_ids[] = { 843 { .compatible = "rockchip,rk3066-hdmi" }, 844 { /* sentinel */ }, 845 }; 846 MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids); 847 848 struct platform_driver rk3066_hdmi_driver = { 849 .probe = rk3066_hdmi_probe, 850 .remove = rk3066_hdmi_remove, 851 .driver = { 852 .name = "rockchip-rk3066-hdmi", 853 .of_match_table = rk3066_hdmi_dt_ids, 854 }, 855 }; 856