xref: /linux/drivers/gpu/drm/rockchip/inno_hdmi.c (revision 5a558f369ef89c6fd8170ee1137274fcc08517ae)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4  *    Zheng Yang <zhengyang@rock-chips.com>
5  *    Yakir Yang <ykk@rock-chips.com>
6  */
7 
8 #include <linux/irq.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/hdmi.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/platform_device.h>
17 
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_edid.h>
21 #include <drm/drm_of.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_simple_kms_helper.h>
24 
25 #include "rockchip_drm_drv.h"
26 
27 #include "inno_hdmi.h"
28 
29 #define INNO_HDMI_MIN_TMDS_CLOCK  25000000U
30 
31 struct inno_hdmi_phy_config {
32 	unsigned long pixelclock;
33 	u8 pre_emphasis;
34 	u8 voltage_level_control;
35 };
36 
37 struct inno_hdmi_variant {
38 	struct inno_hdmi_phy_config *phy_configs;
39 	struct inno_hdmi_phy_config *default_phy_config;
40 };
41 
42 struct inno_hdmi_i2c {
43 	struct i2c_adapter adap;
44 
45 	u8 ddc_addr;
46 	u8 segment_addr;
47 
48 	struct mutex lock;
49 	struct completion cmp;
50 };
51 
52 struct inno_hdmi {
53 	struct device *dev;
54 
55 	struct clk *pclk;
56 	struct clk *refclk;
57 	void __iomem *regs;
58 
59 	struct drm_connector	connector;
60 	struct rockchip_encoder	encoder;
61 
62 	struct inno_hdmi_i2c *i2c;
63 	struct i2c_adapter *ddc;
64 
65 	const struct inno_hdmi_variant *variant;
66 };
67 
68 struct inno_hdmi_connector_state {
69 	struct drm_connector_state	base;
70 	unsigned int			enc_out_format;
71 	unsigned int			colorimetry;
72 	bool				rgb_limited_range;
73 };
74 
75 static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
76 {
77 	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
78 
79 	return container_of(rkencoder, struct inno_hdmi, encoder);
80 }
81 
82 static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
83 {
84 	return container_of(connector, struct inno_hdmi, connector);
85 }
86 
87 #define to_inno_hdmi_conn_state(conn_state) \
88 	container_of_const(conn_state, struct inno_hdmi_connector_state, base)
89 
90 enum {
91 	CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
92 	CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
93 	CSC_RGB_0_255_TO_RGB_16_235_8BIT,
94 };
95 
96 static const char coeff_csc[][24] = {
97 	/*
98 	 * RGB2YUV:601 SD mode:
99 	 *   Cb = -0.291G - 0.148R + 0.439B + 128
100 	 *   Y  = 0.504G  + 0.257R + 0.098B + 16
101 	 *   Cr = -0.368G + 0.439R - 0.071B + 128
102 	 */
103 	{
104 		0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
105 		0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
106 		0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
107 	},
108 	/*
109 	 * RGB2YUV:709 HD mode:
110 	 *   Cb = - 0.338G - 0.101R + 0.439B + 128
111 	 *   Y  = 0.614G   + 0.183R + 0.062B + 16
112 	 *   Cr = - 0.399G + 0.439R - 0.040B + 128
113 	 */
114 	{
115 		0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
116 		0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
117 		0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
118 	},
119 	/*
120 	 * RGB[0:255]2RGB[16:235]:
121 	 *   R' = R x (235-16)/255 + 16;
122 	 *   G' = G x (235-16)/255 + 16;
123 	 *   B' = B x (235-16)/255 + 16;
124 	 */
125 	{
126 		0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
127 		0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
128 		0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
129 	},
130 };
131 
132 static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
133 	{  74250000, 0x3f, 0xbb },
134 	{ 165000000, 0x6f, 0xbb },
135 	{      ~0UL, 0x00, 0x00 }
136 };
137 
138 static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
139 	{  74250000, 0x3f, 0xaa },
140 	{ 165000000, 0x5f, 0xaa },
141 	{      ~0UL, 0x00, 0x00 }
142 };
143 
144 static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
145 				     unsigned long pixelclk)
146 {
147 	const struct inno_hdmi_phy_config *phy_configs =
148 						hdmi->variant->phy_configs;
149 	int i;
150 
151 	for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
152 		if (pixelclk <= phy_configs[i].pixelclock)
153 			return i;
154 	}
155 
156 	DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
157 		      pixelclk);
158 
159 	return -EINVAL;
160 }
161 
162 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
163 {
164 	return readl_relaxed(hdmi->regs + (offset) * 0x04);
165 }
166 
167 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
168 {
169 	writel_relaxed(val, hdmi->regs + (offset) * 0x04);
170 }
171 
172 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
173 			     u32 msk, u32 val)
174 {
175 	u8 temp = hdmi_readb(hdmi, offset) & ~msk;
176 
177 	temp |= val & msk;
178 	hdmi_writeb(hdmi, offset, temp);
179 }
180 
181 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
182 {
183 	unsigned long long ddc_bus_freq = rate >> 2;
184 
185 	do_div(ddc_bus_freq, HDMI_SCL_RATE);
186 
187 	hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
188 	hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
189 
190 	/* Clear the EDID interrupt flag and mute the interrupt */
191 	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
192 	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
193 }
194 
195 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
196 {
197 	if (enable)
198 		hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
199 	else
200 		hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
201 }
202 
203 static void inno_hdmi_standby(struct inno_hdmi *hdmi)
204 {
205 	inno_hdmi_sys_power(hdmi, false);
206 
207 	hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
208 	hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
209 	hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
210 	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
211 };
212 
213 static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
214 			       unsigned long mpixelclock)
215 {
216 	struct inno_hdmi_phy_config *phy_config;
217 	int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
218 
219 	if (ret < 0) {
220 		phy_config = hdmi->variant->default_phy_config;
221 		DRM_DEV_ERROR(hdmi->dev,
222 			      "Using default phy configuration for TMDS rate %lu",
223 			      mpixelclock);
224 	} else {
225 		phy_config = &hdmi->variant->phy_configs[ret];
226 	}
227 
228 	inno_hdmi_sys_power(hdmi, false);
229 
230 	hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
231 	hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
232 	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
233 	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
234 	hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
235 	hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
236 	hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
237 	hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
238 
239 	inno_hdmi_sys_power(hdmi, true);
240 };
241 
242 static void inno_hdmi_reset(struct inno_hdmi *hdmi)
243 {
244 	u32 val;
245 	u32 msk;
246 
247 	hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
248 	udelay(100);
249 
250 	hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
251 	udelay(100);
252 
253 	msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
254 	val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
255 	hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
256 
257 	inno_hdmi_standby(hdmi);
258 }
259 
260 static void inno_hdmi_disable_frame(struct inno_hdmi *hdmi,
261 				    enum hdmi_infoframe_type type)
262 {
263 	struct drm_connector *connector = &hdmi->connector;
264 
265 	if (type != HDMI_INFOFRAME_TYPE_AVI) {
266 		drm_err(connector->dev,
267 			"Unsupported infoframe type: %u\n", type);
268 		return;
269 	}
270 
271 	hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
272 }
273 
274 static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi,
275 				  union hdmi_infoframe *frame, enum hdmi_infoframe_type type)
276 {
277 	struct drm_connector *connector = &hdmi->connector;
278 	u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
279 	ssize_t rc, i;
280 
281 	if (type != HDMI_INFOFRAME_TYPE_AVI) {
282 		drm_err(connector->dev,
283 			"Unsupported infoframe type: %u\n", type);
284 		return 0;
285 	}
286 
287 	inno_hdmi_disable_frame(hdmi, type);
288 
289 	rc = hdmi_infoframe_pack(frame, packed_frame,
290 				 sizeof(packed_frame));
291 	if (rc < 0)
292 		return rc;
293 
294 	for (i = 0; i < rc; i++)
295 		hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
296 			    packed_frame[i]);
297 
298 	return 0;
299 }
300 
301 static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
302 				      struct drm_display_mode *mode)
303 {
304 	struct drm_connector *connector = &hdmi->connector;
305 	struct drm_connector_state *conn_state = connector->state;
306 	struct inno_hdmi_connector_state *inno_conn_state =
307 					to_inno_hdmi_conn_state(conn_state);
308 	union hdmi_infoframe frame;
309 	int rc;
310 
311 	rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
312 						      &hdmi->connector,
313 						      mode);
314 	if (rc) {
315 		inno_hdmi_disable_frame(hdmi, HDMI_INFOFRAME_TYPE_AVI);
316 		return rc;
317 	}
318 
319 	if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444)
320 		frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
321 	else if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV422)
322 		frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
323 	else
324 		frame.avi.colorspace = HDMI_COLORSPACE_RGB;
325 
326 	if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
327 		drm_hdmi_avi_infoframe_quant_range(&frame.avi,
328 						   connector, mode,
329 						   inno_conn_state->rgb_limited_range ?
330 						   HDMI_QUANTIZATION_RANGE_LIMITED :
331 						   HDMI_QUANTIZATION_RANGE_FULL);
332 	} else {
333 		frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
334 		frame.avi.ycc_quantization_range =
335 			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
336 	}
337 
338 	return inno_hdmi_upload_frame(hdmi, &frame, HDMI_INFOFRAME_TYPE_AVI);
339 }
340 
341 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
342 {
343 	struct drm_connector *connector = &hdmi->connector;
344 	struct drm_connector_state *conn_state = connector->state;
345 	struct inno_hdmi_connector_state *inno_conn_state =
346 					to_inno_hdmi_conn_state(conn_state);
347 	int c0_c2_change = 0;
348 	int csc_enable = 0;
349 	int csc_mode = 0;
350 	int auto_csc = 0;
351 	int value;
352 	int i;
353 
354 	/* Input video mode is SDR RGB24bit, data enable signal from external */
355 	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
356 		    v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
357 
358 	/* Input color hardcode to RGB, and output color hardcode to RGB888 */
359 	value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
360 		v_VIDEO_OUTPUT_COLOR(0) |
361 		v_VIDEO_INPUT_CSP(0);
362 	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
363 
364 	if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
365 		if (inno_conn_state->rgb_limited_range) {
366 			csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
367 			auto_csc = AUTO_CSC_DISABLE;
368 			c0_c2_change = C0_C2_CHANGE_DISABLE;
369 			csc_enable = v_CSC_ENABLE;
370 
371 		} else {
372 			value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
373 			hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
374 
375 			hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
376 				  m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
377 				  v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
378 				  v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
379 			return 0;
380 		}
381 	} else {
382 		if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
383 			if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
384 				csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
385 				auto_csc = AUTO_CSC_DISABLE;
386 				c0_c2_change = C0_C2_CHANGE_DISABLE;
387 				csc_enable = v_CSC_ENABLE;
388 			}
389 		} else {
390 			if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
391 				csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
392 				auto_csc = AUTO_CSC_DISABLE;
393 				c0_c2_change = C0_C2_CHANGE_DISABLE;
394 				csc_enable = v_CSC_ENABLE;
395 			}
396 		}
397 	}
398 
399 	for (i = 0; i < 24; i++)
400 		hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
401 			    coeff_csc[csc_mode][i]);
402 
403 	value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
404 	hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
405 	hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
406 		  m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
407 		  v_VIDEO_C0_C2_SWAP(c0_c2_change));
408 
409 	return 0;
410 }
411 
412 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
413 					 struct drm_display_mode *mode)
414 {
415 	int value;
416 
417 	/* Set detail external video timing polarity and interlace mode */
418 	value = v_EXTERANL_VIDEO(1);
419 	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
420 		 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
421 	value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
422 		 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
423 	value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
424 		 v_INETLACE(1) : v_INETLACE(0);
425 	hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
426 
427 	/* Set detail external video timing */
428 	value = mode->htotal;
429 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
430 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
431 
432 	value = mode->htotal - mode->hdisplay;
433 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
434 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
435 
436 	value = mode->htotal - mode->hsync_start;
437 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
438 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
439 
440 	value = mode->hsync_end - mode->hsync_start;
441 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
442 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
443 
444 	value = mode->vtotal;
445 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
446 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
447 
448 	value = mode->vtotal - mode->vdisplay;
449 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
450 
451 	value = mode->vtotal - mode->vsync_start;
452 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
453 
454 	value = mode->vsync_end - mode->vsync_start;
455 	hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
456 
457 	hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
458 	hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
459 	hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
460 
461 	return 0;
462 }
463 
464 static int inno_hdmi_setup(struct inno_hdmi *hdmi,
465 			   struct drm_display_mode *mode)
466 {
467 	struct drm_display_info *display = &hdmi->connector.display_info;
468 	unsigned long mpixelclock = mode->clock * 1000;
469 
470 	/* Mute video and audio output */
471 	hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
472 		  v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
473 
474 	/* Set HDMI Mode */
475 	hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
476 		    v_HDMI_DVI(display->is_hdmi));
477 
478 	inno_hdmi_config_video_timing(hdmi, mode);
479 
480 	inno_hdmi_config_video_csc(hdmi);
481 
482 	if (display->is_hdmi)
483 		inno_hdmi_config_video_avi(hdmi, mode);
484 
485 	/*
486 	 * When IP controller have configured to an accurate video
487 	 * timing, then the TMDS clock source would be switched to
488 	 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
489 	 * clock rate, and reconfigure the DDC clock.
490 	 */
491 	inno_hdmi_i2c_init(hdmi, mpixelclock);
492 
493 	/* Unmute video and audio output */
494 	hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
495 		  v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
496 
497 	inno_hdmi_power_up(hdmi, mpixelclock);
498 
499 	return 0;
500 }
501 
502 static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi,
503 							 struct drm_display_mode *mode)
504 {
505 	unsigned long mpixelclk, max_tolerance;
506 	long rounded_refclk;
507 
508 	/* No support for double-clock modes */
509 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
510 		return MODE_BAD;
511 
512 	mpixelclk = mode->clock * 1000;
513 
514 	if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
515 		return MODE_CLOCK_LOW;
516 
517 	if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
518 		return MODE_CLOCK_HIGH;
519 
520 	if (hdmi->refclk) {
521 		rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk);
522 		if (rounded_refclk < 0)
523 			return MODE_BAD;
524 
525 		/* Vesa DMT standard mentions +/- 0.5% max tolerance */
526 		max_tolerance = mpixelclk / 200;
527 		if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
528 			return MODE_NOCLOCK;
529 	}
530 
531 	return MODE_OK;
532 }
533 
534 static void inno_hdmi_encoder_enable(struct drm_encoder *encoder,
535 				     struct drm_atomic_state *state)
536 {
537 	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
538 	struct drm_connector_state *conn_state;
539 	struct drm_crtc_state *crtc_state;
540 
541 	conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
542 	if (WARN_ON(!conn_state))
543 		return;
544 
545 	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
546 	if (WARN_ON(!crtc_state))
547 		return;
548 
549 	inno_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
550 }
551 
552 static void inno_hdmi_encoder_disable(struct drm_encoder *encoder,
553 				      struct drm_atomic_state *state)
554 {
555 	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
556 
557 	inno_hdmi_standby(hdmi);
558 }
559 
560 static int
561 inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
562 			       struct drm_crtc_state *crtc_state,
563 			       struct drm_connector_state *conn_state)
564 {
565 	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
566 	struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
567 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
568 	u8 vic = drm_match_cea_mode(mode);
569 	struct inno_hdmi_connector_state *inno_conn_state =
570 					to_inno_hdmi_conn_state(conn_state);
571 
572 	s->output_mode = ROCKCHIP_OUT_MODE_P888;
573 	s->output_type = DRM_MODE_CONNECTOR_HDMIA;
574 
575 	if (vic == 6 || vic == 7 ||
576 	    vic == 21 || vic == 22 ||
577 	    vic == 2 || vic == 3 ||
578 	    vic == 17 || vic == 18)
579 		inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
580 	else
581 		inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
582 
583 	inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
584 	inno_conn_state->rgb_limited_range =
585 		drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
586 
587 	return  inno_hdmi_display_mode_valid(hdmi,
588 				&crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL;
589 }
590 
591 static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
592 	.atomic_check	= inno_hdmi_encoder_atomic_check,
593 	.atomic_enable	= inno_hdmi_encoder_enable,
594 	.atomic_disable	= inno_hdmi_encoder_disable,
595 };
596 
597 static enum drm_connector_status
598 inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
599 {
600 	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
601 
602 	return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
603 		connector_status_connected : connector_status_disconnected;
604 }
605 
606 static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
607 {
608 	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
609 	const struct drm_edid *drm_edid;
610 	int ret = 0;
611 
612 	if (!hdmi->ddc)
613 		return 0;
614 
615 	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
616 	drm_edid_connector_update(connector, drm_edid);
617 	ret = drm_edid_connector_add_modes(connector);
618 	drm_edid_free(drm_edid);
619 
620 	return ret;
621 }
622 
623 static enum drm_mode_status
624 inno_hdmi_connector_mode_valid(struct drm_connector *connector,
625 			       struct drm_display_mode *mode)
626 {
627 	struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
628 
629 	return  inno_hdmi_display_mode_valid(hdmi, mode);
630 }
631 
632 static void inno_hdmi_connector_destroy(struct drm_connector *connector)
633 {
634 	drm_connector_unregister(connector);
635 	drm_connector_cleanup(connector);
636 }
637 
638 static void
639 inno_hdmi_connector_destroy_state(struct drm_connector *connector,
640 				  struct drm_connector_state *state)
641 {
642 	struct inno_hdmi_connector_state *inno_conn_state =
643 						to_inno_hdmi_conn_state(state);
644 
645 	__drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
646 	kfree(inno_conn_state);
647 }
648 
649 static void inno_hdmi_connector_reset(struct drm_connector *connector)
650 {
651 	struct inno_hdmi_connector_state *inno_conn_state;
652 
653 	if (connector->state) {
654 		inno_hdmi_connector_destroy_state(connector, connector->state);
655 		connector->state = NULL;
656 	}
657 
658 	inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
659 	if (!inno_conn_state)
660 		return;
661 
662 	__drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
663 
664 	inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
665 	inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
666 	inno_conn_state->rgb_limited_range = false;
667 }
668 
669 static struct drm_connector_state *
670 inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
671 {
672 	struct inno_hdmi_connector_state *inno_conn_state;
673 
674 	if (WARN_ON(!connector->state))
675 		return NULL;
676 
677 	inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
678 				  sizeof(*inno_conn_state), GFP_KERNEL);
679 
680 	if (!inno_conn_state)
681 		return NULL;
682 
683 	__drm_atomic_helper_connector_duplicate_state(connector,
684 						      &inno_conn_state->base);
685 
686 	return &inno_conn_state->base;
687 }
688 
689 static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
690 	.fill_modes = drm_helper_probe_single_connector_modes,
691 	.detect = inno_hdmi_connector_detect,
692 	.destroy = inno_hdmi_connector_destroy,
693 	.reset = inno_hdmi_connector_reset,
694 	.atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
695 	.atomic_destroy_state = inno_hdmi_connector_destroy_state,
696 };
697 
698 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
699 	.get_modes = inno_hdmi_connector_get_modes,
700 	.mode_valid = inno_hdmi_connector_mode_valid,
701 };
702 
703 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
704 {
705 	struct drm_encoder *encoder = &hdmi->encoder.encoder;
706 	struct device *dev = hdmi->dev;
707 
708 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
709 
710 	/*
711 	 * If we failed to find the CRTC(s) which this encoder is
712 	 * supposed to be connected to, it's because the CRTC has
713 	 * not been registered yet.  Defer probing, and hope that
714 	 * the required CRTC is added later.
715 	 */
716 	if (encoder->possible_crtcs == 0)
717 		return -EPROBE_DEFER;
718 
719 	drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
720 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
721 
722 	hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
723 
724 	drm_connector_helper_add(&hdmi->connector,
725 				 &inno_hdmi_connector_helper_funcs);
726 	drm_connector_init_with_ddc(drm, &hdmi->connector,
727 				    &inno_hdmi_connector_funcs,
728 				    DRM_MODE_CONNECTOR_HDMIA,
729 				    hdmi->ddc);
730 
731 	drm_connector_attach_encoder(&hdmi->connector, encoder);
732 
733 	return 0;
734 }
735 
736 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
737 {
738 	struct inno_hdmi_i2c *i2c = hdmi->i2c;
739 	u8 stat;
740 
741 	stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
742 	if (!(stat & m_INT_EDID_READY))
743 		return IRQ_NONE;
744 
745 	/* Clear HDMI EDID interrupt flag */
746 	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
747 
748 	complete(&i2c->cmp);
749 
750 	return IRQ_HANDLED;
751 }
752 
753 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
754 {
755 	struct inno_hdmi *hdmi = dev_id;
756 	irqreturn_t ret = IRQ_NONE;
757 	u8 interrupt;
758 
759 	if (hdmi->i2c)
760 		ret = inno_hdmi_i2c_irq(hdmi);
761 
762 	interrupt = hdmi_readb(hdmi, HDMI_STATUS);
763 	if (interrupt & m_INT_HOTPLUG) {
764 		hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
765 		ret = IRQ_WAKE_THREAD;
766 	}
767 
768 	return ret;
769 }
770 
771 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
772 {
773 	struct inno_hdmi *hdmi = dev_id;
774 
775 	drm_helper_hpd_irq_event(hdmi->connector.dev);
776 
777 	return IRQ_HANDLED;
778 }
779 
780 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
781 {
782 	int length = msgs->len;
783 	u8 *buf = msgs->buf;
784 	int ret;
785 
786 	ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
787 	if (!ret)
788 		return -EAGAIN;
789 
790 	while (length--)
791 		*buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
792 
793 	return 0;
794 }
795 
796 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
797 {
798 	/*
799 	 * The DDC module only support read EDID message, so
800 	 * we assume that each word write to this i2c adapter
801 	 * should be the offset of EDID word address.
802 	 */
803 	if ((msgs->len != 1) ||
804 	    ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
805 		return -EINVAL;
806 
807 	reinit_completion(&hdmi->i2c->cmp);
808 
809 	if (msgs->addr == DDC_SEGMENT_ADDR)
810 		hdmi->i2c->segment_addr = msgs->buf[0];
811 	if (msgs->addr == DDC_ADDR)
812 		hdmi->i2c->ddc_addr = msgs->buf[0];
813 
814 	/* Set edid fifo first addr */
815 	hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
816 
817 	/* Set edid word address 0x00/0x80 */
818 	hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
819 
820 	/* Set edid segment pointer */
821 	hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
822 
823 	return 0;
824 }
825 
826 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
827 			      struct i2c_msg *msgs, int num)
828 {
829 	struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
830 	struct inno_hdmi_i2c *i2c = hdmi->i2c;
831 	int i, ret = 0;
832 
833 	mutex_lock(&i2c->lock);
834 
835 	/* Clear the EDID interrupt flag and unmute the interrupt */
836 	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
837 	hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
838 
839 	for (i = 0; i < num; i++) {
840 		DRM_DEV_DEBUG(hdmi->dev,
841 			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
842 			      i + 1, num, msgs[i].len, msgs[i].flags);
843 
844 		if (msgs[i].flags & I2C_M_RD)
845 			ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
846 		else
847 			ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
848 
849 		if (ret < 0)
850 			break;
851 	}
852 
853 	if (!ret)
854 		ret = num;
855 
856 	/* Mute HDMI EDID interrupt */
857 	hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
858 
859 	mutex_unlock(&i2c->lock);
860 
861 	return ret;
862 }
863 
864 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
865 {
866 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
867 }
868 
869 static const struct i2c_algorithm inno_hdmi_algorithm = {
870 	.master_xfer	= inno_hdmi_i2c_xfer,
871 	.functionality	= inno_hdmi_i2c_func,
872 };
873 
874 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
875 {
876 	struct i2c_adapter *adap;
877 	struct inno_hdmi_i2c *i2c;
878 	int ret;
879 
880 	i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
881 	if (!i2c)
882 		return ERR_PTR(-ENOMEM);
883 
884 	mutex_init(&i2c->lock);
885 	init_completion(&i2c->cmp);
886 
887 	adap = &i2c->adap;
888 	adap->owner = THIS_MODULE;
889 	adap->dev.parent = hdmi->dev;
890 	adap->dev.of_node = hdmi->dev->of_node;
891 	adap->algo = &inno_hdmi_algorithm;
892 	strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
893 	i2c_set_adapdata(adap, hdmi);
894 
895 	ret = i2c_add_adapter(adap);
896 	if (ret) {
897 		dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
898 		devm_kfree(hdmi->dev, i2c);
899 		return ERR_PTR(ret);
900 	}
901 
902 	hdmi->i2c = i2c;
903 
904 	DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
905 
906 	return adap;
907 }
908 
909 static int inno_hdmi_bind(struct device *dev, struct device *master,
910 				 void *data)
911 {
912 	struct platform_device *pdev = to_platform_device(dev);
913 	struct drm_device *drm = data;
914 	struct inno_hdmi *hdmi;
915 	const struct inno_hdmi_variant *variant;
916 	int irq;
917 	int ret;
918 
919 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
920 	if (!hdmi)
921 		return -ENOMEM;
922 
923 	hdmi->dev = dev;
924 
925 	variant = of_device_get_match_data(hdmi->dev);
926 	if (!variant)
927 		return -EINVAL;
928 
929 	hdmi->variant = variant;
930 
931 	hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
932 	if (IS_ERR(hdmi->regs))
933 		return PTR_ERR(hdmi->regs);
934 
935 	hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
936 	if (IS_ERR(hdmi->pclk)) {
937 		DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
938 		return PTR_ERR(hdmi->pclk);
939 	}
940 
941 	ret = clk_prepare_enable(hdmi->pclk);
942 	if (ret) {
943 		DRM_DEV_ERROR(hdmi->dev,
944 			      "Cannot enable HDMI pclk clock: %d\n", ret);
945 		return ret;
946 	}
947 
948 	hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
949 	if (IS_ERR(hdmi->refclk)) {
950 		DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
951 		ret = PTR_ERR(hdmi->refclk);
952 		goto err_disable_pclk;
953 	}
954 
955 	ret = clk_prepare_enable(hdmi->refclk);
956 	if (ret) {
957 		DRM_DEV_ERROR(hdmi->dev,
958 			      "Cannot enable HDMI reference clock: %d\n", ret);
959 		goto err_disable_pclk;
960 	}
961 
962 	irq = platform_get_irq(pdev, 0);
963 	if (irq < 0) {
964 		ret = irq;
965 		goto err_disable_clk;
966 	}
967 
968 	inno_hdmi_reset(hdmi);
969 
970 	hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
971 	if (IS_ERR(hdmi->ddc)) {
972 		ret = PTR_ERR(hdmi->ddc);
973 		hdmi->ddc = NULL;
974 		goto err_disable_clk;
975 	}
976 
977 	/*
978 	 * When the controller isn't configured to an accurate
979 	 * video timing and there is no reference clock available,
980 	 * then the TMDS clock source would be switched to PCLK_HDMI,
981 	 * so we need to init the TMDS rate to PCLK rate, and
982 	 * reconfigure the DDC clock.
983 	 */
984 	if (hdmi->refclk)
985 		inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk));
986 	else
987 		inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk));
988 
989 	ret = inno_hdmi_register(drm, hdmi);
990 	if (ret)
991 		goto err_put_adapter;
992 
993 	dev_set_drvdata(dev, hdmi);
994 
995 	/* Unmute hotplug interrupt */
996 	hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
997 
998 	ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
999 					inno_hdmi_irq, IRQF_SHARED,
1000 					dev_name(dev), hdmi);
1001 	if (ret < 0)
1002 		goto err_cleanup_hdmi;
1003 
1004 	return 0;
1005 err_cleanup_hdmi:
1006 	hdmi->connector.funcs->destroy(&hdmi->connector);
1007 	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
1008 err_put_adapter:
1009 	i2c_put_adapter(hdmi->ddc);
1010 err_disable_clk:
1011 	clk_disable_unprepare(hdmi->refclk);
1012 err_disable_pclk:
1013 	clk_disable_unprepare(hdmi->pclk);
1014 	return ret;
1015 }
1016 
1017 static void inno_hdmi_unbind(struct device *dev, struct device *master,
1018 			     void *data)
1019 {
1020 	struct inno_hdmi *hdmi = dev_get_drvdata(dev);
1021 
1022 	hdmi->connector.funcs->destroy(&hdmi->connector);
1023 	hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
1024 
1025 	i2c_put_adapter(hdmi->ddc);
1026 	clk_disable_unprepare(hdmi->refclk);
1027 	clk_disable_unprepare(hdmi->pclk);
1028 }
1029 
1030 static const struct component_ops inno_hdmi_ops = {
1031 	.bind	= inno_hdmi_bind,
1032 	.unbind	= inno_hdmi_unbind,
1033 };
1034 
1035 static int inno_hdmi_probe(struct platform_device *pdev)
1036 {
1037 	return component_add(&pdev->dev, &inno_hdmi_ops);
1038 }
1039 
1040 static void inno_hdmi_remove(struct platform_device *pdev)
1041 {
1042 	component_del(&pdev->dev, &inno_hdmi_ops);
1043 }
1044 
1045 static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = {
1046 	.phy_configs = rk3036_hdmi_phy_configs,
1047 	.default_phy_config = &rk3036_hdmi_phy_configs[1],
1048 };
1049 
1050 static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = {
1051 	.phy_configs = rk3128_hdmi_phy_configs,
1052 	.default_phy_config = &rk3128_hdmi_phy_configs[1],
1053 };
1054 
1055 static const struct of_device_id inno_hdmi_dt_ids[] = {
1056 	{ .compatible = "rockchip,rk3036-inno-hdmi",
1057 	  .data = &rk3036_inno_hdmi_variant,
1058 	},
1059 	{ .compatible = "rockchip,rk3128-inno-hdmi",
1060 	  .data = &rk3128_inno_hdmi_variant,
1061 	},
1062 	{},
1063 };
1064 MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
1065 
1066 struct platform_driver inno_hdmi_driver = {
1067 	.probe  = inno_hdmi_probe,
1068 	.remove_new = inno_hdmi_remove,
1069 	.driver = {
1070 		.name = "innohdmi-rockchip",
1071 		.of_match_table = inno_hdmi_dt_ids,
1072 	},
1073 };
1074