1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/hw_bitfield.h> 11 #include <linux/iopoll.h> 12 #include <linux/math64.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/of_platform.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/bridge/dw_mipi_dsi.h> 25 #include <drm/drm_mipi_dsi.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include "rockchip_drm_drv.h" 30 31 #define DSI_PHY_RSTZ 0xa0 32 #define PHY_DISFORCEPLL 0 33 #define PHY_ENFORCEPLL BIT(3) 34 #define PHY_DISABLECLK 0 35 #define PHY_ENABLECLK BIT(2) 36 #define PHY_RSTZ 0 37 #define PHY_UNRSTZ BIT(1) 38 #define PHY_SHUTDOWNZ 0 39 #define PHY_UNSHUTDOWNZ BIT(0) 40 41 #define DSI_PHY_IF_CFG 0xa4 42 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 43 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 44 45 #define DSI_PHY_STATUS 0xb0 46 #define LOCK BIT(0) 47 #define STOP_STATE_CLK_LANE BIT(2) 48 49 #define DSI_PHY_TST_CTRL0 0xb4 50 #define PHY_TESTCLK BIT(1) 51 #define PHY_UNTESTCLK 0 52 #define PHY_TESTCLR BIT(0) 53 #define PHY_UNTESTCLR 0 54 55 #define DSI_PHY_TST_CTRL1 0xb8 56 #define PHY_TESTEN BIT(16) 57 #define PHY_UNTESTEN 0 58 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 59 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 60 61 #define DSI_INT_ST0 0xbc 62 #define DSI_INT_ST1 0xc0 63 #define DSI_INT_MSK0 0xc4 64 #define DSI_INT_MSK1 0xc8 65 66 #define PHY_STATUS_TIMEOUT_US 10000 67 #define CMD_PKT_STATUS_TIMEOUT_US 20000 68 69 #define BYPASS_VCO_RANGE BIT(7) 70 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 71 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 72 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 73 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 74 #define REF_BIAS_CUR_SEL BIT(0) 75 76 #define CP_CURRENT_3UA 0x1 77 #define CP_CURRENT_4_5UA 0x2 78 #define CP_CURRENT_7_5UA 0x6 79 #define CP_CURRENT_6UA 0x9 80 #define CP_CURRENT_12UA 0xb 81 #define CP_CURRENT_SEL(val) ((val) & 0xf) 82 #define CP_PROGRAM_EN BIT(7) 83 84 #define LPF_RESISTORS_15_5KOHM 0x1 85 #define LPF_RESISTORS_13KOHM 0x2 86 #define LPF_RESISTORS_11_5KOHM 0x4 87 #define LPF_RESISTORS_10_5KOHM 0x8 88 #define LPF_RESISTORS_8KOHM 0x10 89 #define LPF_PROGRAM_EN BIT(6) 90 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 91 92 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 93 94 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 95 #define LOW_PROGRAM_EN 0 96 #define HIGH_PROGRAM_EN BIT(7) 97 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 98 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 99 #define PLL_LOOP_DIV_EN BIT(5) 100 #define PLL_INPUT_DIV_EN BIT(4) 101 102 #define POWER_CONTROL BIT(6) 103 #define INTERNAL_REG_CURRENT BIT(3) 104 #define BIAS_BLOCK_ON BIT(2) 105 #define BANDGAP_ON BIT(0) 106 107 #define TER_RESISTOR_HIGH BIT(7) 108 #define TER_RESISTOR_LOW 0 109 #define LEVEL_SHIFTERS_ON BIT(6) 110 #define TER_CAL_DONE BIT(5) 111 #define SETRD_MAX (0x7 << 2) 112 #define POWER_MANAGE BIT(1) 113 #define TER_RESISTORS_ON BIT(0) 114 115 #define BIASEXTR_SEL(val) ((val) & 0x7) 116 #define BANDGAP_SEL(val) ((val) & 0x7) 117 #define TLP_PROGRAM_EN BIT(7) 118 #define THS_PRE_PROGRAM_EN BIT(7) 119 #define THS_ZERO_PROGRAM_EN BIT(6) 120 121 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 122 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 123 #define PLL_LPF_AND_CP_CONTROL 0x12 124 #define PLL_INPUT_DIVIDER_RATIO 0x17 125 #define PLL_LOOP_DIVIDER_RATIO 0x18 126 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 127 #define BANDGAP_AND_BIAS_CONTROL 0x20 128 #define TERMINATION_RESISTER_CONTROL 0x21 129 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 130 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 131 #define HS_RX_CONTROL_OF_LANE_0 0x44 132 #define HS_RX_CONTROL_OF_LANE_1 0x54 133 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 134 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 135 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 136 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 137 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 138 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 139 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 140 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 141 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 142 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 143 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 144 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 145 #define HS_RX_CONTROL_OF_LANE_2 0x84 146 #define HS_RX_CONTROL_OF_LANE_3 0x94 147 148 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 149 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 150 151 #define PX30_GRF_PD_VO_CON1 0x0438 152 #define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7) 153 #define PX30_DSI_FORCERXMODE BIT(6) 154 #define PX30_DSI_TURNDISABLE BIT(5) 155 #define PX30_DSI_LCDC_SEL BIT(0) 156 157 #define RK3128_GRF_LVDS_CON0 0x0150 158 #define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10) 159 #define RK3128_DSI_FORCERXMODE BIT(9) 160 #define RK3128_DSI_TURNDISABLE BIT(8) 161 162 #define RK3288_GRF_SOC_CON6 0x025c 163 #define RK3288_DSI0_LCDC_SEL BIT(6) 164 #define RK3288_DSI1_LCDC_SEL BIT(9) 165 166 #define RK3368_GRF_SOC_CON7 0x41c 167 #define RK3368_DSI_FORCETXSTOPMODE (0xf << 7) 168 #define RK3368_DSI_FORCERXMODE BIT(6) 169 #define RK3368_DSI_TURNDISABLE BIT(5) 170 171 #define RK3399_GRF_SOC_CON20 0x6250 172 #define RK3399_DSI0_LCDC_SEL BIT(0) 173 #define RK3399_DSI1_LCDC_SEL BIT(4) 174 175 #define RK3399_GRF_SOC_CON22 0x6258 176 #define RK3399_DSI0_TURNREQUEST (0xfUL << 12) 177 #define RK3399_DSI0_TURNDISABLE (0xfUL << 8) 178 #define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4) 179 #define RK3399_DSI0_FORCERXMODE (0xfUL << 0) 180 181 #define RK3399_GRF_SOC_CON23 0x625c 182 #define RK3399_DSI1_TURNDISABLE (0xfUL << 12) 183 #define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8) 184 #define RK3399_DSI1_FORCERXMODE (0xfUL << 4) 185 #define RK3399_DSI1_ENABLE (0xfUL << 0) 186 187 #define RK3399_GRF_SOC_CON24 0x6260 188 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 189 #define RK3399_TXRX_ENABLECLK BIT(6) 190 #define RK3399_TXRX_BASEDIR BIT(5) 191 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 192 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 193 194 #define RK3568_GRF_VO_CON2 0x0368 195 #define RK3568_DSI0_SKEWCALHS (0x1fUL << 11) 196 #define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4) 197 #define RK3568_DSI0_TURNDISABLE BIT(2) 198 #define RK3568_DSI0_FORCERXMODE BIT(0) 199 200 /* 201 * Note these registers do not appear in the datasheet, they are 202 * however present in the BSP driver which is where these values 203 * come from. Name GRF_VO_CON3 is assumed. 204 */ 205 #define RK3568_GRF_VO_CON3 0x36c 206 #define RK3568_DSI1_SKEWCALHS (0x1fUL << 11) 207 #define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4) 208 #define RK3568_DSI1_TURNDISABLE BIT(2) 209 #define RK3568_DSI1_FORCERXMODE BIT(0) 210 211 #define RV1126_GRF_DSIPHY_CON 0x10220 212 #define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4) 213 #define RV1126_DSI_TURNDISABLE BIT(2) 214 #define RV1126_DSI_FORCERXMODE BIT(0) 215 216 enum { 217 DW_DSI_USAGE_IDLE, 218 DW_DSI_USAGE_DSI, 219 DW_DSI_USAGE_PHY, 220 }; 221 222 enum { 223 BANDGAP_97_07, 224 BANDGAP_98_05, 225 BANDGAP_99_02, 226 BANDGAP_100_00, 227 BANDGAP_93_17, 228 BANDGAP_94_15, 229 BANDGAP_95_12, 230 BANDGAP_96_10, 231 }; 232 233 enum { 234 BIASEXTR_87_1, 235 BIASEXTR_91_5, 236 BIASEXTR_95_9, 237 BIASEXTR_100, 238 BIASEXTR_105_94, 239 BIASEXTR_111_88, 240 BIASEXTR_118_8, 241 BIASEXTR_127_7, 242 }; 243 244 struct rockchip_dw_dsi_chip_data { 245 u32 reg; 246 247 u32 lcdsel_grf_reg; 248 u32 lcdsel_big; 249 u32 lcdsel_lit; 250 251 u32 enable_grf_reg; 252 u32 enable; 253 254 u32 lanecfg1_grf_reg; 255 u32 lanecfg1; 256 u32 lanecfg2_grf_reg; 257 u32 lanecfg2; 258 259 int (*dphy_rx_init)(struct phy *phy); 260 int (*dphy_rx_power_on)(struct phy *phy); 261 int (*dphy_rx_power_off)(struct phy *phy); 262 263 unsigned int flags; 264 unsigned int max_data_lanes; 265 }; 266 267 struct dw_mipi_dsi_rockchip { 268 struct device *dev; 269 struct rockchip_encoder encoder; 270 void __iomem *base; 271 272 struct regmap *grf_regmap; 273 struct clk *pclk; 274 struct clk *pllref_clk; 275 struct clk *grf_clk; 276 struct clk *phy_cfg_clk; 277 278 /* dual-channel */ 279 bool is_slave; 280 struct dw_mipi_dsi_rockchip *slave; 281 282 /* optional external dphy */ 283 struct phy *phy; 284 union phy_configure_opts phy_opts; 285 286 /* being a phy for other mipi hosts */ 287 unsigned int usage_mode; 288 struct mutex usage_mutex; 289 struct phy *dphy; 290 struct phy_configure_opts_mipi_dphy dphy_config; 291 292 unsigned int lane_mbps; /* per lane */ 293 u16 input_div; 294 u16 feedback_div; 295 u32 format; 296 297 struct dw_mipi_dsi *dmd; 298 const struct rockchip_dw_dsi_chip_data *cdata; 299 struct dw_mipi_dsi_plat_data pdata; 300 301 bool dsi_bound; 302 }; 303 304 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 305 { 306 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 307 308 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 309 } 310 311 struct dphy_pll_parameter_map { 312 unsigned int max_mbps; 313 u8 hsfreqrange; 314 u8 icpctrl; 315 u8 lpfctrl; 316 }; 317 318 /* The table is based on 27MHz DPHY pll reference clock. */ 319 static const struct dphy_pll_parameter_map dppa_map[] = { 320 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 321 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 322 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 323 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 324 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 325 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 326 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 327 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 328 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 329 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 330 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 331 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 332 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 333 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 334 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 335 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 336 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 337 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 338 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 339 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 340 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 341 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 342 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 343 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 344 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 345 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 346 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 347 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 348 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 349 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 350 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 351 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 352 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 353 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 354 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 355 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 356 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 357 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 358 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 359 }; 360 361 static int max_mbps_to_parameter(unsigned int max_mbps) 362 { 363 int i; 364 365 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 366 if (dppa_map[i].max_mbps >= max_mbps) 367 return i; 368 369 return -EINVAL; 370 } 371 372 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 373 { 374 writel(val, dsi->base + reg); 375 } 376 377 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 378 u8 test_code, 379 u8 test_data) 380 { 381 /* 382 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 383 * is latched internally as the current test code. Test data is 384 * programmed internally by rising edge on TESTCLK. 385 */ 386 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 387 388 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 389 PHY_TESTDIN(test_code)); 390 391 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 392 393 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 394 PHY_TESTDIN(test_data)); 395 396 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 397 } 398 399 /* 400 * ns2bc - Nanoseconds to byte clock cycles 401 */ 402 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 403 { 404 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 405 } 406 407 /* 408 * ns2ui - Nanoseconds to UI time periods 409 */ 410 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 411 { 412 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 413 } 414 415 static int dw_mipi_dsi_phy_init(void *priv_data) 416 { 417 struct dw_mipi_dsi_rockchip *dsi = priv_data; 418 int ret, i, vco; 419 420 if (dsi->phy) 421 return 0; 422 423 /* 424 * Get vco from frequency(lane_mbps) 425 * vco frequency table 426 * 000 - between 80 and 200 MHz 427 * 001 - between 200 and 300 MHz 428 * 010 - between 300 and 500 MHz 429 * 011 - between 500 and 700 MHz 430 * 100 - between 700 and 900 MHz 431 * 101 - between 900 and 1100 MHz 432 * 110 - between 1100 and 1300 MHz 433 * 111 - between 1300 and 1500 MHz 434 */ 435 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 436 437 i = max_mbps_to_parameter(dsi->lane_mbps); 438 if (i < 0) { 439 DRM_DEV_ERROR(dsi->dev, 440 "failed to get parameter for %dmbps clock\n", 441 dsi->lane_mbps); 442 return i; 443 } 444 445 ret = clk_prepare_enable(dsi->phy_cfg_clk); 446 if (ret) { 447 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 448 return ret; 449 } 450 451 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 452 BYPASS_VCO_RANGE | 453 VCO_RANGE_CON_SEL(vco) | 454 VCO_IN_CAP_CON_LOW | 455 REF_BIAS_CUR_SEL); 456 457 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 458 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 459 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 460 CP_PROGRAM_EN | LPF_PROGRAM_EN | 461 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 462 463 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 464 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 465 466 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 467 INPUT_DIVIDER(dsi->input_div)); 468 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 469 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 470 LOW_PROGRAM_EN); 471 /* 472 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 473 * to make the configured LSB effective according to IP simulation 474 * and lab test results. 475 * Only in this way can we get correct mipi phy pll frequency. 476 */ 477 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 478 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 479 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 480 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 481 HIGH_PROGRAM_EN); 482 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 483 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 484 485 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 486 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 487 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 488 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 489 490 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 491 POWER_CONTROL | INTERNAL_REG_CURRENT | 492 BIAS_BLOCK_ON | BANDGAP_ON); 493 494 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 495 TER_RESISTOR_LOW | TER_CAL_DONE | 496 SETRD_MAX | TER_RESISTORS_ON); 497 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 498 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 499 SETRD_MAX | POWER_MANAGE | 500 TER_RESISTORS_ON); 501 502 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 503 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 504 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 505 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 506 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 507 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 508 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 509 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 510 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 511 BIT(5) | ns2bc(dsi, 100)); 512 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 513 BIT(5) | (ns2bc(dsi, 60) + 7)); 514 515 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 516 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 517 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 518 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 519 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 520 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 521 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 522 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 523 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 524 BIT(5) | ns2bc(dsi, 100)); 525 526 clk_disable_unprepare(dsi->phy_cfg_clk); 527 528 return ret; 529 } 530 531 static void dw_mipi_dsi_phy_power_on(void *priv_data) 532 { 533 struct dw_mipi_dsi_rockchip *dsi = priv_data; 534 int ret; 535 536 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 537 if (ret) { 538 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 539 return; 540 } 541 542 phy_configure(dsi->phy, &dsi->phy_opts); 543 phy_power_on(dsi->phy); 544 } 545 546 static void dw_mipi_dsi_phy_power_off(void *priv_data) 547 { 548 struct dw_mipi_dsi_rockchip *dsi = priv_data; 549 550 phy_power_off(dsi->phy); 551 } 552 553 static int 554 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 555 unsigned long mode_flags, u32 lanes, u32 format, 556 unsigned int *lane_mbps) 557 { 558 struct dw_mipi_dsi_rockchip *dsi = priv_data; 559 int bpp; 560 unsigned long mpclk, tmp; 561 unsigned int target_mbps = 1000; 562 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 563 unsigned long best_freq = 0; 564 unsigned long fvco_min, fvco_max, fin, fout; 565 unsigned int min_prediv, max_prediv; 566 unsigned int _prediv, best_prediv; 567 unsigned long _fbdiv, best_fbdiv; 568 unsigned long min_delta = ULONG_MAX; 569 570 dsi->format = format; 571 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 572 if (bpp < 0) { 573 DRM_DEV_ERROR(dsi->dev, 574 "failed to get bpp for pixel format %d\n", 575 dsi->format); 576 return bpp; 577 } 578 579 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 580 if (mpclk) { 581 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 582 tmp = mpclk * (bpp / lanes) * 10 / 8; 583 if (tmp < max_mbps) 584 target_mbps = tmp; 585 else 586 DRM_DEV_ERROR(dsi->dev, 587 "DPHY clock frequency is out of range\n"); 588 } 589 590 /* for external phy only a the mipi_dphy_config is necessary */ 591 if (dsi->phy) { 592 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 593 bpp, lanes, 594 &dsi->phy_opts.mipi_dphy); 595 dsi->lane_mbps = target_mbps; 596 *lane_mbps = dsi->lane_mbps; 597 598 return 0; 599 } 600 601 fin = clk_get_rate(dsi->pllref_clk); 602 fout = target_mbps * USEC_PER_SEC; 603 604 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 605 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 606 max_prediv = fin / (5 * USEC_PER_SEC); 607 608 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 609 fvco_min = 80 * USEC_PER_SEC; 610 fvco_max = 1500 * USEC_PER_SEC; 611 612 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 613 u64 tmp; 614 u32 delta; 615 /* Fvco = Fref * M / N */ 616 tmp = (u64)fout * _prediv; 617 do_div(tmp, fin); 618 _fbdiv = tmp; 619 /* 620 * Due to the use of a "by 2 pre-scaler," the range of the 621 * feedback multiplication value M is limited to even division 622 * numbers, and m must be greater than 6, not bigger than 512. 623 */ 624 if (_fbdiv < 6 || _fbdiv > 512) 625 continue; 626 627 _fbdiv += _fbdiv % 2; 628 629 tmp = (u64)_fbdiv * fin; 630 do_div(tmp, _prediv); 631 if (tmp < fvco_min || tmp > fvco_max) 632 continue; 633 634 delta = abs(fout - tmp); 635 if (delta < min_delta) { 636 best_prediv = _prediv; 637 best_fbdiv = _fbdiv; 638 min_delta = delta; 639 best_freq = tmp; 640 } 641 } 642 643 if (best_freq) { 644 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 645 *lane_mbps = dsi->lane_mbps; 646 dsi->input_div = best_prediv; 647 dsi->feedback_div = best_fbdiv; 648 } else { 649 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 650 return -EINVAL; 651 } 652 653 return 0; 654 } 655 656 struct hstt { 657 unsigned int maxfreq; 658 struct dw_mipi_dsi_dphy_timing timing; 659 }; 660 661 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 662 { \ 663 .maxfreq = _maxfreq, \ 664 .timing = { \ 665 .clk_lp2hs = _c_lp2hs, \ 666 .clk_hs2lp = _c_hs2lp, \ 667 .data_lp2hs = _d_lp2hs, \ 668 .data_hs2lp = _d_hs2lp, \ 669 } \ 670 } 671 672 /* Table A-3 High-Speed Transition Times */ 673 static struct hstt hstt_table[] = { 674 HSTT( 90, 32, 20, 26, 13), 675 HSTT( 100, 35, 23, 28, 14), 676 HSTT( 110, 32, 22, 26, 13), 677 HSTT( 130, 31, 20, 27, 13), 678 HSTT( 140, 33, 22, 26, 14), 679 HSTT( 150, 33, 21, 26, 14), 680 HSTT( 170, 32, 20, 27, 13), 681 HSTT( 180, 36, 23, 30, 15), 682 HSTT( 200, 40, 22, 33, 15), 683 HSTT( 220, 40, 22, 33, 15), 684 HSTT( 240, 44, 24, 36, 16), 685 HSTT( 250, 48, 24, 38, 17), 686 HSTT( 270, 48, 24, 38, 17), 687 HSTT( 300, 50, 27, 41, 18), 688 HSTT( 330, 56, 28, 45, 18), 689 HSTT( 360, 59, 28, 48, 19), 690 HSTT( 400, 61, 30, 50, 20), 691 HSTT( 450, 67, 31, 55, 21), 692 HSTT( 500, 73, 31, 59, 22), 693 HSTT( 550, 79, 36, 63, 24), 694 HSTT( 600, 83, 37, 68, 25), 695 HSTT( 650, 90, 38, 73, 27), 696 HSTT( 700, 95, 40, 77, 28), 697 HSTT( 750, 102, 40, 84, 28), 698 HSTT( 800, 106, 42, 87, 30), 699 HSTT( 850, 113, 44, 93, 31), 700 HSTT( 900, 118, 47, 98, 32), 701 HSTT( 950, 124, 47, 102, 34), 702 HSTT(1000, 130, 49, 107, 35), 703 HSTT(1050, 135, 51, 111, 37), 704 HSTT(1100, 139, 51, 114, 38), 705 HSTT(1150, 146, 54, 120, 40), 706 HSTT(1200, 153, 57, 125, 41), 707 HSTT(1250, 158, 58, 130, 42), 708 HSTT(1300, 163, 58, 135, 44), 709 HSTT(1350, 168, 60, 140, 45), 710 HSTT(1400, 172, 64, 144, 47), 711 HSTT(1450, 176, 65, 148, 48), 712 HSTT(1500, 181, 66, 153, 50) 713 }; 714 715 static int 716 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 717 struct dw_mipi_dsi_dphy_timing *timing) 718 { 719 int i; 720 721 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 722 if (lane_mbps < hstt_table[i].maxfreq) 723 break; 724 725 if (i == ARRAY_SIZE(hstt_table)) 726 i--; 727 728 *timing = hstt_table[i].timing; 729 730 return 0; 731 } 732 733 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 734 .init = dw_mipi_dsi_phy_init, 735 .power_on = dw_mipi_dsi_phy_power_on, 736 .power_off = dw_mipi_dsi_phy_power_off, 737 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 738 .get_timing = dw_mipi_dsi_phy_get_timing, 739 }; 740 741 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 742 { 743 if (dsi->cdata->lanecfg1_grf_reg) 744 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 745 dsi->cdata->lanecfg1); 746 747 if (dsi->cdata->lanecfg2_grf_reg) 748 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 749 dsi->cdata->lanecfg2); 750 751 if (dsi->cdata->enable_grf_reg) 752 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 753 dsi->cdata->enable); 754 } 755 756 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 757 int mux) 758 { 759 if (dsi->cdata->lcdsel_grf_reg) 760 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 761 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 762 } 763 764 static int 765 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 766 struct drm_crtc_state *crtc_state, 767 struct drm_connector_state *conn_state) 768 { 769 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 770 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 771 772 switch (dsi->format) { 773 case MIPI_DSI_FMT_RGB888: 774 s->output_mode = ROCKCHIP_OUT_MODE_P888; 775 break; 776 case MIPI_DSI_FMT_RGB666: 777 s->output_mode = ROCKCHIP_OUT_MODE_P666; 778 break; 779 case MIPI_DSI_FMT_RGB565: 780 s->output_mode = ROCKCHIP_OUT_MODE_P565; 781 break; 782 default: 783 WARN_ON(1); 784 return -EINVAL; 785 } 786 787 s->output_type = DRM_MODE_CONNECTOR_DSI; 788 if (dsi->slave) 789 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 790 791 return 0; 792 } 793 794 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 795 { 796 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 797 int ret, mux; 798 799 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 800 &dsi->encoder.encoder); 801 if (mux < 0) 802 return; 803 804 /* 805 * For the RK3399, the clk of grf must be enabled before writing grf 806 * register. And for RK3288 or other soc, this grf_clk must be NULL, 807 * the clk_prepare_enable return true directly. 808 */ 809 ret = clk_prepare_enable(dsi->grf_clk); 810 if (ret) { 811 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 812 return; 813 } 814 815 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 816 if (dsi->slave) 817 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 818 819 clk_disable_unprepare(dsi->grf_clk); 820 } 821 822 static const struct drm_encoder_helper_funcs 823 dw_mipi_dsi_encoder_helper_funcs = { 824 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 825 .enable = dw_mipi_dsi_encoder_enable, 826 }; 827 828 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 829 struct drm_device *drm_dev) 830 { 831 struct drm_encoder *encoder = &dsi->encoder.encoder; 832 int ret; 833 834 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 835 dsi->dev->of_node); 836 837 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 838 if (ret) { 839 DRM_ERROR("Failed to initialize encoder with drm\n"); 840 return ret; 841 } 842 843 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 844 845 return 0; 846 } 847 848 static struct device 849 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 850 { 851 const struct of_device_id *match; 852 struct device_node *node = NULL, *local; 853 854 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 855 856 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 857 if (!local) 858 return NULL; 859 860 while ((node = of_find_compatible_node(node, NULL, 861 match->compatible))) { 862 struct device_node *remote; 863 864 /* found ourself */ 865 if (node == dsi->dev->of_node) 866 continue; 867 868 remote = of_graph_get_remote_node(node, 1, 0); 869 if (!remote) 870 continue; 871 872 /* same display device in port1-ep0 for both */ 873 if (remote == local) { 874 struct dw_mipi_dsi_rockchip *dsi2; 875 struct platform_device *pdev; 876 877 pdev = of_find_device_by_node(node); 878 879 /* 880 * we have found the second, so will either return it 881 * or return with an error. In any case won't need the 882 * nodes anymore nor continue the loop. 883 */ 884 of_node_put(remote); 885 of_node_put(node); 886 of_node_put(local); 887 888 if (!pdev) 889 return ERR_PTR(-EPROBE_DEFER); 890 891 dsi2 = platform_get_drvdata(pdev); 892 if (!dsi2) { 893 platform_device_put(pdev); 894 return ERR_PTR(-EPROBE_DEFER); 895 } 896 897 return &pdev->dev; 898 } 899 900 of_node_put(remote); 901 } 902 903 of_node_put(local); 904 905 return NULL; 906 } 907 908 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 909 struct device *master, 910 void *data) 911 { 912 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 913 struct drm_device *drm_dev = data; 914 struct device *second; 915 bool master1, master2; 916 int ret; 917 918 second = dw_mipi_dsi_rockchip_find_second(dsi); 919 if (IS_ERR(second)) 920 return PTR_ERR(second); 921 922 if (second) { 923 master1 = of_property_read_bool(dsi->dev->of_node, 924 "clock-master"); 925 master2 = of_property_read_bool(second->of_node, 926 "clock-master"); 927 928 if (master1 && master2) { 929 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 930 return -EINVAL; 931 } 932 933 if (!master1 && !master2) { 934 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 935 return -EINVAL; 936 } 937 938 /* we are the slave in dual-DSI */ 939 if (!master1) { 940 dsi->is_slave = true; 941 return 0; 942 } 943 944 dsi->slave = dev_get_drvdata(second); 945 if (!dsi->slave) { 946 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 947 return -ENODEV; 948 } 949 950 dsi->slave->is_slave = true; 951 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 952 put_device(second); 953 } 954 955 pm_runtime_get_sync(dsi->dev); 956 if (dsi->slave) 957 pm_runtime_get_sync(dsi->slave->dev); 958 959 ret = clk_prepare_enable(dsi->pllref_clk); 960 if (ret) { 961 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 962 goto out_pm_runtime; 963 } 964 965 /* 966 * With the GRF clock running, write lane and dual-mode configurations 967 * that won't change immediately. If we waited until enable() to do 968 * this, things like panel preparation would not be able to send 969 * commands over DSI. 970 */ 971 ret = clk_prepare_enable(dsi->grf_clk); 972 if (ret) { 973 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 974 goto out_pll_clk; 975 } 976 977 dw_mipi_dsi_rockchip_config(dsi); 978 if (dsi->slave) 979 dw_mipi_dsi_rockchip_config(dsi->slave); 980 981 clk_disable_unprepare(dsi->grf_clk); 982 983 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 984 if (ret) { 985 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 986 goto out_pll_clk; 987 } 988 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 989 dev->of_node, 0, 0); 990 991 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 992 if (ret) { 993 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 994 goto out_pll_clk; 995 } 996 997 dsi->dsi_bound = true; 998 999 return 0; 1000 1001 out_pll_clk: 1002 clk_disable_unprepare(dsi->pllref_clk); 1003 out_pm_runtime: 1004 pm_runtime_put(dsi->dev); 1005 if (dsi->slave) 1006 pm_runtime_put(dsi->slave->dev); 1007 1008 return ret; 1009 } 1010 1011 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 1012 struct device *master, 1013 void *data) 1014 { 1015 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1016 1017 if (dsi->is_slave) 1018 return; 1019 1020 dsi->dsi_bound = false; 1021 1022 dw_mipi_dsi_unbind(dsi->dmd); 1023 1024 clk_disable_unprepare(dsi->pllref_clk); 1025 1026 pm_runtime_put(dsi->dev); 1027 if (dsi->slave) 1028 pm_runtime_put(dsi->slave->dev); 1029 } 1030 1031 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1032 .bind = dw_mipi_dsi_rockchip_bind, 1033 .unbind = dw_mipi_dsi_rockchip_unbind, 1034 }; 1035 1036 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1037 struct mipi_dsi_device *device) 1038 { 1039 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1040 struct device *second; 1041 int ret; 1042 1043 mutex_lock(&dsi->usage_mutex); 1044 1045 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1046 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1047 mutex_unlock(&dsi->usage_mutex); 1048 return -EBUSY; 1049 } 1050 1051 dsi->usage_mode = DW_DSI_USAGE_DSI; 1052 mutex_unlock(&dsi->usage_mutex); 1053 1054 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1055 if (ret) { 1056 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1057 ret); 1058 goto out; 1059 } 1060 1061 second = dw_mipi_dsi_rockchip_find_second(dsi); 1062 if (IS_ERR(second)) { 1063 ret = PTR_ERR(second); 1064 goto out; 1065 } 1066 if (second) { 1067 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1068 if (ret) { 1069 DRM_DEV_ERROR(second, 1070 "Failed to register component: %d\n", 1071 ret); 1072 goto out; 1073 } 1074 } 1075 1076 return 0; 1077 1078 out: 1079 mutex_lock(&dsi->usage_mutex); 1080 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1081 mutex_unlock(&dsi->usage_mutex); 1082 return ret; 1083 } 1084 1085 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1086 struct mipi_dsi_device *device) 1087 { 1088 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1089 struct device *second; 1090 1091 second = dw_mipi_dsi_rockchip_find_second(dsi); 1092 if (second && !IS_ERR(second)) 1093 component_del(second, &dw_mipi_dsi_rockchip_ops); 1094 1095 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1096 1097 mutex_lock(&dsi->usage_mutex); 1098 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1099 mutex_unlock(&dsi->usage_mutex); 1100 1101 return 0; 1102 } 1103 1104 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1105 .attach = dw_mipi_dsi_rockchip_host_attach, 1106 .detach = dw_mipi_dsi_rockchip_host_detach, 1107 }; 1108 1109 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1110 struct device *master, 1111 void *data) 1112 { 1113 /* 1114 * Nothing to do when used as a dphy. 1115 * Just make the rest of Rockchip-DRM happy 1116 * by being here. 1117 */ 1118 1119 return 0; 1120 } 1121 1122 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1123 struct device *master, 1124 void *data) 1125 { 1126 /* Nothing to do when used as a dphy. */ 1127 } 1128 1129 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1130 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1131 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1132 }; 1133 1134 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1135 { 1136 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1137 int ret; 1138 1139 mutex_lock(&dsi->usage_mutex); 1140 1141 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1142 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1143 mutex_unlock(&dsi->usage_mutex); 1144 return -EBUSY; 1145 } 1146 1147 dsi->usage_mode = DW_DSI_USAGE_PHY; 1148 mutex_unlock(&dsi->usage_mutex); 1149 1150 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1151 if (ret < 0) 1152 goto err_graph; 1153 1154 if (dsi->cdata->dphy_rx_init) { 1155 ret = clk_prepare_enable(dsi->pclk); 1156 if (ret < 0) 1157 goto err_init; 1158 1159 ret = clk_prepare_enable(dsi->grf_clk); 1160 if (ret) { 1161 clk_disable_unprepare(dsi->pclk); 1162 goto err_init; 1163 } 1164 1165 ret = dsi->cdata->dphy_rx_init(phy); 1166 clk_disable_unprepare(dsi->grf_clk); 1167 clk_disable_unprepare(dsi->pclk); 1168 if (ret < 0) 1169 goto err_init; 1170 } 1171 1172 return 0; 1173 1174 err_init: 1175 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1176 err_graph: 1177 mutex_lock(&dsi->usage_mutex); 1178 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1179 mutex_unlock(&dsi->usage_mutex); 1180 1181 return ret; 1182 } 1183 1184 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1185 { 1186 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1187 1188 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1189 1190 mutex_lock(&dsi->usage_mutex); 1191 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1192 mutex_unlock(&dsi->usage_mutex); 1193 1194 return 0; 1195 } 1196 1197 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1198 { 1199 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1200 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1201 int ret; 1202 1203 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1204 if (ret) 1205 return ret; 1206 1207 dsi->dphy_config = *config; 1208 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1209 1210 return 0; 1211 } 1212 1213 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1214 { 1215 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1216 int i, ret; 1217 1218 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1219 dsi->dphy_config.lanes, dsi->lane_mbps); 1220 1221 i = max_mbps_to_parameter(dsi->lane_mbps); 1222 if (i < 0) { 1223 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1224 dsi->lane_mbps); 1225 return i; 1226 } 1227 1228 ret = pm_runtime_resume_and_get(dsi->dev); 1229 if (ret < 0) { 1230 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1231 return ret; 1232 } 1233 1234 ret = clk_prepare_enable(dsi->pclk); 1235 if (ret) { 1236 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1237 goto err_pclk; 1238 } 1239 1240 ret = clk_prepare_enable(dsi->grf_clk); 1241 if (ret) { 1242 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1243 goto err_grf_clk; 1244 } 1245 1246 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1247 if (ret) { 1248 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1249 goto err_phy_cfg_clk; 1250 } 1251 1252 /* do soc-variant specific init */ 1253 if (dsi->cdata->dphy_rx_power_on) { 1254 ret = dsi->cdata->dphy_rx_power_on(phy); 1255 if (ret < 0) { 1256 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1257 goto err_pwr_on; 1258 } 1259 } 1260 1261 /* 1262 * Configure hsfreqrange according to frequency values 1263 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1264 */ 1265 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1266 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1267 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1268 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1269 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1270 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1271 1272 /* Normal operation */ 1273 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1274 1275 clk_disable_unprepare(dsi->phy_cfg_clk); 1276 clk_disable_unprepare(dsi->grf_clk); 1277 1278 return ret; 1279 1280 err_pwr_on: 1281 clk_disable_unprepare(dsi->phy_cfg_clk); 1282 err_phy_cfg_clk: 1283 clk_disable_unprepare(dsi->grf_clk); 1284 err_grf_clk: 1285 clk_disable_unprepare(dsi->pclk); 1286 err_pclk: 1287 pm_runtime_put(dsi->dev); 1288 return ret; 1289 } 1290 1291 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1292 { 1293 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1294 int ret; 1295 1296 ret = clk_prepare_enable(dsi->grf_clk); 1297 if (ret) { 1298 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1299 return ret; 1300 } 1301 1302 if (dsi->cdata->dphy_rx_power_off) { 1303 ret = dsi->cdata->dphy_rx_power_off(phy); 1304 if (ret < 0) 1305 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1306 } 1307 1308 clk_disable_unprepare(dsi->grf_clk); 1309 clk_disable_unprepare(dsi->pclk); 1310 1311 pm_runtime_put(dsi->dev); 1312 1313 return ret; 1314 } 1315 1316 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1317 .configure = dw_mipi_dsi_dphy_configure, 1318 .power_on = dw_mipi_dsi_dphy_power_on, 1319 .power_off = dw_mipi_dsi_dphy_power_off, 1320 .init = dw_mipi_dsi_dphy_init, 1321 .exit = dw_mipi_dsi_dphy_exit, 1322 }; 1323 1324 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1325 { 1326 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1327 int ret; 1328 1329 /* 1330 * Re-configure DSI state, if we were previously initialized. We need 1331 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1332 */ 1333 if (dsi->dsi_bound) { 1334 ret = clk_prepare_enable(dsi->grf_clk); 1335 if (ret) { 1336 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1337 return ret; 1338 } 1339 1340 dw_mipi_dsi_rockchip_config(dsi); 1341 if (dsi->slave) 1342 dw_mipi_dsi_rockchip_config(dsi->slave); 1343 1344 clk_disable_unprepare(dsi->grf_clk); 1345 } 1346 1347 return 0; 1348 } 1349 1350 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1351 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1352 }; 1353 1354 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1355 { 1356 struct device *dev = &pdev->dev; 1357 struct device_node *np = dev->of_node; 1358 struct dw_mipi_dsi_rockchip *dsi; 1359 struct phy_provider *phy_provider; 1360 struct resource *res; 1361 const struct rockchip_dw_dsi_chip_data *cdata = 1362 of_device_get_match_data(dev); 1363 int ret, i; 1364 1365 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1366 if (!dsi) 1367 return -ENOMEM; 1368 1369 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1370 if (IS_ERR(dsi->base)) { 1371 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1372 return PTR_ERR(dsi->base); 1373 } 1374 1375 i = 0; 1376 while (cdata[i].reg) { 1377 if (cdata[i].reg == res->start) { 1378 dsi->cdata = &cdata[i]; 1379 break; 1380 } 1381 1382 i++; 1383 } 1384 1385 if (!dsi->cdata) { 1386 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1387 return -EINVAL; 1388 } 1389 1390 /* try to get a possible external dphy */ 1391 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1392 if (IS_ERR(dsi->phy)) { 1393 ret = PTR_ERR(dsi->phy); 1394 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1395 return ret; 1396 } 1397 1398 dsi->pclk = devm_clk_get(dev, "pclk"); 1399 if (IS_ERR(dsi->pclk)) { 1400 ret = PTR_ERR(dsi->pclk); 1401 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1402 return ret; 1403 } 1404 1405 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1406 if (IS_ERR(dsi->pllref_clk)) { 1407 if (dsi->phy) { 1408 /* 1409 * if external phy is present, pll will be 1410 * generated there. 1411 */ 1412 dsi->pllref_clk = NULL; 1413 } else { 1414 ret = PTR_ERR(dsi->pllref_clk); 1415 DRM_DEV_ERROR(dev, 1416 "Unable to get pll reference clock: %d\n", 1417 ret); 1418 return ret; 1419 } 1420 } 1421 1422 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1423 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1424 if (IS_ERR(dsi->phy_cfg_clk)) { 1425 ret = PTR_ERR(dsi->phy_cfg_clk); 1426 DRM_DEV_ERROR(dev, 1427 "Unable to get phy_cfg_clk: %d\n", ret); 1428 return ret; 1429 } 1430 } 1431 1432 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1433 dsi->grf_clk = devm_clk_get(dev, "grf"); 1434 if (IS_ERR(dsi->grf_clk)) { 1435 ret = PTR_ERR(dsi->grf_clk); 1436 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1437 return ret; 1438 } 1439 } 1440 1441 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1442 if (IS_ERR(dsi->grf_regmap)) { 1443 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1444 return PTR_ERR(dsi->grf_regmap); 1445 } 1446 1447 dsi->dev = dev; 1448 dsi->pdata.base = dsi->base; 1449 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1450 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1451 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1452 dsi->pdata.priv_data = dsi; 1453 platform_set_drvdata(pdev, dsi); 1454 1455 mutex_init(&dsi->usage_mutex); 1456 1457 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1458 if (IS_ERR(dsi->dphy)) { 1459 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1460 return PTR_ERR(dsi->dphy); 1461 } 1462 1463 phy_set_drvdata(dsi->dphy, dsi); 1464 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1465 if (IS_ERR(phy_provider)) 1466 return PTR_ERR(phy_provider); 1467 1468 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1469 if (IS_ERR(dsi->dmd)) { 1470 ret = PTR_ERR(dsi->dmd); 1471 if (ret != -EPROBE_DEFER) 1472 DRM_DEV_ERROR(dev, 1473 "Failed to probe dw_mipi_dsi: %d\n", ret); 1474 return ret; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1481 { 1482 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1483 1484 dw_mipi_dsi_remove(dsi->dmd); 1485 } 1486 1487 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1488 { 1489 .reg = 0xff450000, 1490 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1491 .lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0), 1492 .lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1), 1493 1494 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1495 .lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE | 1496 PX30_DSI_FORCERXMODE | 1497 PX30_DSI_FORCETXSTOPMODE), 0), 1498 1499 .max_data_lanes = 4, 1500 }, 1501 { /* sentinel */ } 1502 }; 1503 1504 static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { 1505 { 1506 .reg = 0x10110000, 1507 .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0, 1508 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE | 1509 RK3128_DSI_FORCERXMODE | 1510 RK3128_DSI_FORCETXSTOPMODE), 0), 1511 .max_data_lanes = 4, 1512 }, 1513 { /* sentinel */ } 1514 }; 1515 1516 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1517 { 1518 .reg = 0xff960000, 1519 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1520 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0), 1521 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), 1522 1523 .max_data_lanes = 4, 1524 }, 1525 { 1526 .reg = 0xff964000, 1527 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1528 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0), 1529 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), 1530 1531 .max_data_lanes = 4, 1532 }, 1533 { /* sentinel */ } 1534 }; 1535 1536 static const struct rockchip_dw_dsi_chip_data rk3368_chip_data[] = { 1537 { 1538 .reg = 0xff960000, 1539 .lanecfg1_grf_reg = RK3368_GRF_SOC_CON7, 1540 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3368_DSI_TURNDISABLE | 1541 RK3368_DSI_FORCETXSTOPMODE | 1542 RK3368_DSI_FORCERXMODE), 0), 1543 .max_data_lanes = 4, 1544 }, 1545 { /* sentinel */ } 1546 }; 1547 1548 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1549 { 1550 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1551 1552 /* 1553 * Set TX1RX1 source to isp1. 1554 * Assume ISP0 is supplied by the RX0 dphy. 1555 */ 1556 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1557 FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0)); 1558 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1559 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1560 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1561 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0)); 1562 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1563 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1564 1565 return 0; 1566 } 1567 1568 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1569 { 1570 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1571 1572 /* tester reset pulse */ 1573 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1574 usleep_range(100, 150); 1575 1576 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1577 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1578 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1579 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1)); 1580 1581 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1582 FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0)); 1583 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1584 FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0)); 1585 1586 /* Disable lane turn around, which is ignored in receive mode */ 1587 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1588 FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0)); 1589 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1590 FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf)); 1591 usleep_range(100, 150); 1592 1593 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1594 usleep_range(100, 150); 1595 1596 /* Enable dphy lanes */ 1597 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1598 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 1599 GENMASK(dsi->dphy_config.lanes - 1, 0))); 1600 1601 usleep_range(100, 150); 1602 1603 return 0; 1604 } 1605 1606 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1607 { 1608 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1609 1610 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1611 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1612 1613 return 0; 1614 } 1615 1616 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1617 { 1618 .reg = 0xff960000, 1619 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1620 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0), 1621 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1), 1622 1623 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1624 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST | 1625 RK3399_DSI0_TURNDISABLE | 1626 RK3399_DSI0_FORCETXSTOPMODE | 1627 RK3399_DSI0_FORCERXMODE), 0), 1628 1629 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1630 .max_data_lanes = 4, 1631 }, 1632 { 1633 .reg = 0xff968000, 1634 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1635 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0), 1636 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1), 1637 1638 1639 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1640 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE | 1641 RK3399_DSI1_FORCETXSTOPMODE | 1642 RK3399_DSI1_FORCERXMODE | 1643 RK3399_DSI1_ENABLE), 0), 1644 1645 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1646 .lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) | 1647 FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) | 1648 FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)), 1649 1650 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1651 .enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1652 1653 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1654 .max_data_lanes = 4, 1655 1656 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1657 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1658 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1659 }, 1660 { /* sentinel */ } 1661 }; 1662 1663 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1664 { 1665 .reg = 0xfe060000, 1666 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1667 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) | 1668 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) | 1669 FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | 1670 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), 1671 .max_data_lanes = 4, 1672 }, 1673 { 1674 .reg = 0xfe070000, 1675 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1676 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) | 1677 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) | 1678 FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | 1679 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), 1680 .max_data_lanes = 4, 1681 }, 1682 { /* sentinel */ } 1683 }; 1684 1685 static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { 1686 { 1687 .reg = 0xffb30000, 1688 .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON, 1689 .lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) | 1690 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | 1691 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), 1692 .max_data_lanes = 4, 1693 }, 1694 { /* sentinel */ } 1695 }; 1696 1697 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1698 { 1699 .compatible = "rockchip,px30-mipi-dsi", 1700 .data = &px30_chip_data, 1701 }, { 1702 .compatible = "rockchip,rk3128-mipi-dsi", 1703 .data = &rk3128_chip_data, 1704 }, { 1705 .compatible = "rockchip,rk3288-mipi-dsi", 1706 .data = &rk3288_chip_data, 1707 }, { 1708 .compatible = "rockchip,rk3368-mipi-dsi", 1709 .data = &rk3368_chip_data, 1710 }, { 1711 .compatible = "rockchip,rk3399-mipi-dsi", 1712 .data = &rk3399_chip_data, 1713 }, { 1714 .compatible = "rockchip,rk3568-mipi-dsi", 1715 .data = &rk3568_chip_data, 1716 }, { 1717 .compatible = "rockchip,rv1126-mipi-dsi", 1718 .data = &rv1126_chip_data, 1719 }, 1720 { /* sentinel */ } 1721 }; 1722 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1723 1724 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1725 .probe = dw_mipi_dsi_rockchip_probe, 1726 .remove = dw_mipi_dsi_rockchip_remove, 1727 .driver = { 1728 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1729 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1730 .name = "dw-mipi-dsi-rockchip", 1731 /* 1732 * For dual-DSI display, one DSI pokes at the other DSI's 1733 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1734 * safe for asynchronous probe. 1735 */ 1736 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1737 }, 1738 }; 1739