1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_platform.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/bridge/dw_mipi_dsi.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "rockchip_drm_drv.h" 29 #include "rockchip_drm_vop.h" 30 31 #define DSI_PHY_RSTZ 0xa0 32 #define PHY_DISFORCEPLL 0 33 #define PHY_ENFORCEPLL BIT(3) 34 #define PHY_DISABLECLK 0 35 #define PHY_ENABLECLK BIT(2) 36 #define PHY_RSTZ 0 37 #define PHY_UNRSTZ BIT(1) 38 #define PHY_SHUTDOWNZ 0 39 #define PHY_UNSHUTDOWNZ BIT(0) 40 41 #define DSI_PHY_IF_CFG 0xa4 42 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 43 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 44 45 #define DSI_PHY_STATUS 0xb0 46 #define LOCK BIT(0) 47 #define STOP_STATE_CLK_LANE BIT(2) 48 49 #define DSI_PHY_TST_CTRL0 0xb4 50 #define PHY_TESTCLK BIT(1) 51 #define PHY_UNTESTCLK 0 52 #define PHY_TESTCLR BIT(0) 53 #define PHY_UNTESTCLR 0 54 55 #define DSI_PHY_TST_CTRL1 0xb8 56 #define PHY_TESTEN BIT(16) 57 #define PHY_UNTESTEN 0 58 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 59 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 60 61 #define DSI_INT_ST0 0xbc 62 #define DSI_INT_ST1 0xc0 63 #define DSI_INT_MSK0 0xc4 64 #define DSI_INT_MSK1 0xc8 65 66 #define PHY_STATUS_TIMEOUT_US 10000 67 #define CMD_PKT_STATUS_TIMEOUT_US 20000 68 69 #define BYPASS_VCO_RANGE BIT(7) 70 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 71 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 72 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 73 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 74 #define REF_BIAS_CUR_SEL BIT(0) 75 76 #define CP_CURRENT_3UA 0x1 77 #define CP_CURRENT_4_5UA 0x2 78 #define CP_CURRENT_7_5UA 0x6 79 #define CP_CURRENT_6UA 0x9 80 #define CP_CURRENT_12UA 0xb 81 #define CP_CURRENT_SEL(val) ((val) & 0xf) 82 #define CP_PROGRAM_EN BIT(7) 83 84 #define LPF_RESISTORS_15_5KOHM 0x1 85 #define LPF_RESISTORS_13KOHM 0x2 86 #define LPF_RESISTORS_11_5KOHM 0x4 87 #define LPF_RESISTORS_10_5KOHM 0x8 88 #define LPF_RESISTORS_8KOHM 0x10 89 #define LPF_PROGRAM_EN BIT(6) 90 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 91 92 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 93 94 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 95 #define LOW_PROGRAM_EN 0 96 #define HIGH_PROGRAM_EN BIT(7) 97 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 98 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 99 #define PLL_LOOP_DIV_EN BIT(5) 100 #define PLL_INPUT_DIV_EN BIT(4) 101 102 #define POWER_CONTROL BIT(6) 103 #define INTERNAL_REG_CURRENT BIT(3) 104 #define BIAS_BLOCK_ON BIT(2) 105 #define BANDGAP_ON BIT(0) 106 107 #define TER_RESISTOR_HIGH BIT(7) 108 #define TER_RESISTOR_LOW 0 109 #define LEVEL_SHIFTERS_ON BIT(6) 110 #define TER_CAL_DONE BIT(5) 111 #define SETRD_MAX (0x7 << 2) 112 #define POWER_MANAGE BIT(1) 113 #define TER_RESISTORS_ON BIT(0) 114 115 #define BIASEXTR_SEL(val) ((val) & 0x7) 116 #define BANDGAP_SEL(val) ((val) & 0x7) 117 #define TLP_PROGRAM_EN BIT(7) 118 #define THS_PRE_PROGRAM_EN BIT(7) 119 #define THS_ZERO_PROGRAM_EN BIT(6) 120 121 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 122 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 123 #define PLL_LPF_AND_CP_CONTROL 0x12 124 #define PLL_INPUT_DIVIDER_RATIO 0x17 125 #define PLL_LOOP_DIVIDER_RATIO 0x18 126 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 127 #define BANDGAP_AND_BIAS_CONTROL 0x20 128 #define TERMINATION_RESISTER_CONTROL 0x21 129 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 130 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 131 #define HS_RX_CONTROL_OF_LANE_0 0x44 132 #define HS_RX_CONTROL_OF_LANE_1 0x54 133 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 134 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 135 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 136 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 137 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 138 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 139 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 140 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 141 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 142 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 143 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 144 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 145 #define HS_RX_CONTROL_OF_LANE_2 0x84 146 #define HS_RX_CONTROL_OF_LANE_3 0x94 147 148 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 149 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 150 151 #define PX30_GRF_PD_VO_CON1 0x0438 152 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 153 #define PX30_DSI_FORCERXMODE BIT(6) 154 #define PX30_DSI_TURNDISABLE BIT(5) 155 #define PX30_DSI_LCDC_SEL BIT(0) 156 157 #define RK3288_GRF_SOC_CON6 0x025c 158 #define RK3288_DSI0_LCDC_SEL BIT(6) 159 #define RK3288_DSI1_LCDC_SEL BIT(9) 160 161 #define RK3399_GRF_SOC_CON20 0x6250 162 #define RK3399_DSI0_LCDC_SEL BIT(0) 163 #define RK3399_DSI1_LCDC_SEL BIT(4) 164 165 #define RK3399_GRF_SOC_CON22 0x6258 166 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 167 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 168 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 169 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 170 171 #define RK3399_GRF_SOC_CON23 0x625c 172 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 173 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 174 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 175 #define RK3399_DSI1_ENABLE (0xf << 0) 176 177 #define RK3399_GRF_SOC_CON24 0x6260 178 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 179 #define RK3399_TXRX_ENABLECLK BIT(6) 180 #define RK3399_TXRX_BASEDIR BIT(5) 181 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 182 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 183 184 #define RK3568_GRF_VO_CON2 0x0368 185 #define RK3568_DSI0_SKEWCALHS (0x1f << 11) 186 #define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) 187 #define RK3568_DSI0_TURNDISABLE BIT(2) 188 #define RK3568_DSI0_FORCERXMODE BIT(0) 189 190 /* 191 * Note these registers do not appear in the datasheet, they are 192 * however present in the BSP driver which is where these values 193 * come from. Name GRF_VO_CON3 is assumed. 194 */ 195 #define RK3568_GRF_VO_CON3 0x36c 196 #define RK3568_DSI1_SKEWCALHS (0x1f << 11) 197 #define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) 198 #define RK3568_DSI1_TURNDISABLE BIT(2) 199 #define RK3568_DSI1_FORCERXMODE BIT(0) 200 201 #define RV1126_GRF_DSIPHY_CON 0x10220 202 #define RV1126_DSI_FORCETXSTOPMODE (0xf << 4) 203 #define RV1126_DSI_TURNDISABLE BIT(2) 204 #define RV1126_DSI_FORCERXMODE BIT(0) 205 206 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 207 208 enum { 209 DW_DSI_USAGE_IDLE, 210 DW_DSI_USAGE_DSI, 211 DW_DSI_USAGE_PHY, 212 }; 213 214 enum { 215 BANDGAP_97_07, 216 BANDGAP_98_05, 217 BANDGAP_99_02, 218 BANDGAP_100_00, 219 BANDGAP_93_17, 220 BANDGAP_94_15, 221 BANDGAP_95_12, 222 BANDGAP_96_10, 223 }; 224 225 enum { 226 BIASEXTR_87_1, 227 BIASEXTR_91_5, 228 BIASEXTR_95_9, 229 BIASEXTR_100, 230 BIASEXTR_105_94, 231 BIASEXTR_111_88, 232 BIASEXTR_118_8, 233 BIASEXTR_127_7, 234 }; 235 236 struct rockchip_dw_dsi_chip_data { 237 u32 reg; 238 239 u32 lcdsel_grf_reg; 240 u32 lcdsel_big; 241 u32 lcdsel_lit; 242 243 u32 enable_grf_reg; 244 u32 enable; 245 246 u32 lanecfg1_grf_reg; 247 u32 lanecfg1; 248 u32 lanecfg2_grf_reg; 249 u32 lanecfg2; 250 251 int (*dphy_rx_init)(struct phy *phy); 252 int (*dphy_rx_power_on)(struct phy *phy); 253 int (*dphy_rx_power_off)(struct phy *phy); 254 255 unsigned int flags; 256 unsigned int max_data_lanes; 257 }; 258 259 struct dw_mipi_dsi_rockchip { 260 struct device *dev; 261 struct rockchip_encoder encoder; 262 void __iomem *base; 263 264 struct regmap *grf_regmap; 265 struct clk *pclk; 266 struct clk *pllref_clk; 267 struct clk *grf_clk; 268 struct clk *phy_cfg_clk; 269 270 /* dual-channel */ 271 bool is_slave; 272 struct dw_mipi_dsi_rockchip *slave; 273 274 /* optional external dphy */ 275 struct phy *phy; 276 union phy_configure_opts phy_opts; 277 278 /* being a phy for other mipi hosts */ 279 unsigned int usage_mode; 280 struct mutex usage_mutex; 281 struct phy *dphy; 282 struct phy_configure_opts_mipi_dphy dphy_config; 283 284 unsigned int lane_mbps; /* per lane */ 285 u16 input_div; 286 u16 feedback_div; 287 u32 format; 288 289 struct dw_mipi_dsi *dmd; 290 const struct rockchip_dw_dsi_chip_data *cdata; 291 struct dw_mipi_dsi_plat_data pdata; 292 293 bool dsi_bound; 294 }; 295 296 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 297 { 298 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 299 300 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 301 } 302 303 struct dphy_pll_parameter_map { 304 unsigned int max_mbps; 305 u8 hsfreqrange; 306 u8 icpctrl; 307 u8 lpfctrl; 308 }; 309 310 /* The table is based on 27MHz DPHY pll reference clock. */ 311 static const struct dphy_pll_parameter_map dppa_map[] = { 312 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 313 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 314 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 315 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 316 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 317 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 318 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 319 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 320 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 321 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 322 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 323 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 324 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 325 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 326 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 327 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 328 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 329 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 330 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 331 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 332 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 333 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 334 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 335 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 336 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 337 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 338 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 339 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 340 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 341 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 342 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 343 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 344 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 345 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 346 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 347 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 348 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 349 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 350 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 351 }; 352 353 static int max_mbps_to_parameter(unsigned int max_mbps) 354 { 355 int i; 356 357 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 358 if (dppa_map[i].max_mbps >= max_mbps) 359 return i; 360 361 return -EINVAL; 362 } 363 364 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 365 { 366 writel(val, dsi->base + reg); 367 } 368 369 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 370 u8 test_code, 371 u8 test_data) 372 { 373 /* 374 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 375 * is latched internally as the current test code. Test data is 376 * programmed internally by rising edge on TESTCLK. 377 */ 378 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 379 380 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 381 PHY_TESTDIN(test_code)); 382 383 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 384 385 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 386 PHY_TESTDIN(test_data)); 387 388 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 389 } 390 391 /* 392 * ns2bc - Nanoseconds to byte clock cycles 393 */ 394 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 395 { 396 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 397 } 398 399 /* 400 * ns2ui - Nanoseconds to UI time periods 401 */ 402 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 403 { 404 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 405 } 406 407 static int dw_mipi_dsi_phy_init(void *priv_data) 408 { 409 struct dw_mipi_dsi_rockchip *dsi = priv_data; 410 int ret, i, vco; 411 412 if (dsi->phy) 413 return 0; 414 415 /* 416 * Get vco from frequency(lane_mbps) 417 * vco frequency table 418 * 000 - between 80 and 200 MHz 419 * 001 - between 200 and 300 MHz 420 * 010 - between 300 and 500 MHz 421 * 011 - between 500 and 700 MHz 422 * 100 - between 700 and 900 MHz 423 * 101 - between 900 and 1100 MHz 424 * 110 - between 1100 and 1300 MHz 425 * 111 - between 1300 and 1500 MHz 426 */ 427 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 428 429 i = max_mbps_to_parameter(dsi->lane_mbps); 430 if (i < 0) { 431 DRM_DEV_ERROR(dsi->dev, 432 "failed to get parameter for %dmbps clock\n", 433 dsi->lane_mbps); 434 return i; 435 } 436 437 ret = clk_prepare_enable(dsi->phy_cfg_clk); 438 if (ret) { 439 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 440 return ret; 441 } 442 443 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 444 BYPASS_VCO_RANGE | 445 VCO_RANGE_CON_SEL(vco) | 446 VCO_IN_CAP_CON_LOW | 447 REF_BIAS_CUR_SEL); 448 449 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 450 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 451 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 452 CP_PROGRAM_EN | LPF_PROGRAM_EN | 453 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 454 455 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 456 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 457 458 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 459 INPUT_DIVIDER(dsi->input_div)); 460 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 461 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 462 LOW_PROGRAM_EN); 463 /* 464 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 465 * to make the configured LSB effective according to IP simulation 466 * and lab test results. 467 * Only in this way can we get correct mipi phy pll frequency. 468 */ 469 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 470 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 471 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 472 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 473 HIGH_PROGRAM_EN); 474 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 475 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 476 477 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 478 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 479 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 480 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 481 482 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 483 POWER_CONTROL | INTERNAL_REG_CURRENT | 484 BIAS_BLOCK_ON | BANDGAP_ON); 485 486 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 487 TER_RESISTOR_LOW | TER_CAL_DONE | 488 SETRD_MAX | TER_RESISTORS_ON); 489 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 490 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 491 SETRD_MAX | POWER_MANAGE | 492 TER_RESISTORS_ON); 493 494 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 495 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 496 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 497 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 498 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 499 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 500 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 501 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 502 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 503 BIT(5) | ns2bc(dsi, 100)); 504 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 505 BIT(5) | (ns2bc(dsi, 60) + 7)); 506 507 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 508 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 509 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 510 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 511 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 512 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 513 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 514 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 515 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 516 BIT(5) | ns2bc(dsi, 100)); 517 518 clk_disable_unprepare(dsi->phy_cfg_clk); 519 520 return ret; 521 } 522 523 static void dw_mipi_dsi_phy_power_on(void *priv_data) 524 { 525 struct dw_mipi_dsi_rockchip *dsi = priv_data; 526 int ret; 527 528 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 529 if (ret) { 530 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 531 return; 532 } 533 534 phy_configure(dsi->phy, &dsi->phy_opts); 535 phy_power_on(dsi->phy); 536 } 537 538 static void dw_mipi_dsi_phy_power_off(void *priv_data) 539 { 540 struct dw_mipi_dsi_rockchip *dsi = priv_data; 541 542 phy_power_off(dsi->phy); 543 } 544 545 static int 546 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 547 unsigned long mode_flags, u32 lanes, u32 format, 548 unsigned int *lane_mbps) 549 { 550 struct dw_mipi_dsi_rockchip *dsi = priv_data; 551 int bpp; 552 unsigned long mpclk, tmp; 553 unsigned int target_mbps = 1000; 554 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 555 unsigned long best_freq = 0; 556 unsigned long fvco_min, fvco_max, fin, fout; 557 unsigned int min_prediv, max_prediv; 558 unsigned int _prediv, best_prediv; 559 unsigned long _fbdiv, best_fbdiv; 560 unsigned long min_delta = ULONG_MAX; 561 562 dsi->format = format; 563 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 564 if (bpp < 0) { 565 DRM_DEV_ERROR(dsi->dev, 566 "failed to get bpp for pixel format %d\n", 567 dsi->format); 568 return bpp; 569 } 570 571 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 572 if (mpclk) { 573 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 574 tmp = mpclk * (bpp / lanes) * 10 / 8; 575 if (tmp < max_mbps) 576 target_mbps = tmp; 577 else 578 DRM_DEV_ERROR(dsi->dev, 579 "DPHY clock frequency is out of range\n"); 580 } 581 582 /* for external phy only a the mipi_dphy_config is necessary */ 583 if (dsi->phy) { 584 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 585 bpp, lanes, 586 &dsi->phy_opts.mipi_dphy); 587 dsi->lane_mbps = target_mbps; 588 *lane_mbps = dsi->lane_mbps; 589 590 return 0; 591 } 592 593 fin = clk_get_rate(dsi->pllref_clk); 594 fout = target_mbps * USEC_PER_SEC; 595 596 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 597 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 598 max_prediv = fin / (5 * USEC_PER_SEC); 599 600 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 601 fvco_min = 80 * USEC_PER_SEC; 602 fvco_max = 1500 * USEC_PER_SEC; 603 604 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 605 u64 tmp; 606 u32 delta; 607 /* Fvco = Fref * M / N */ 608 tmp = (u64)fout * _prediv; 609 do_div(tmp, fin); 610 _fbdiv = tmp; 611 /* 612 * Due to the use of a "by 2 pre-scaler," the range of the 613 * feedback multiplication value M is limited to even division 614 * numbers, and m must be greater than 6, not bigger than 512. 615 */ 616 if (_fbdiv < 6 || _fbdiv > 512) 617 continue; 618 619 _fbdiv += _fbdiv % 2; 620 621 tmp = (u64)_fbdiv * fin; 622 do_div(tmp, _prediv); 623 if (tmp < fvco_min || tmp > fvco_max) 624 continue; 625 626 delta = abs(fout - tmp); 627 if (delta < min_delta) { 628 best_prediv = _prediv; 629 best_fbdiv = _fbdiv; 630 min_delta = delta; 631 best_freq = tmp; 632 } 633 } 634 635 if (best_freq) { 636 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 637 *lane_mbps = dsi->lane_mbps; 638 dsi->input_div = best_prediv; 639 dsi->feedback_div = best_fbdiv; 640 } else { 641 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 642 return -EINVAL; 643 } 644 645 return 0; 646 } 647 648 struct hstt { 649 unsigned int maxfreq; 650 struct dw_mipi_dsi_dphy_timing timing; 651 }; 652 653 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 654 { \ 655 .maxfreq = _maxfreq, \ 656 .timing = { \ 657 .clk_lp2hs = _c_lp2hs, \ 658 .clk_hs2lp = _c_hs2lp, \ 659 .data_lp2hs = _d_lp2hs, \ 660 .data_hs2lp = _d_hs2lp, \ 661 } \ 662 } 663 664 /* Table A-3 High-Speed Transition Times */ 665 static struct hstt hstt_table[] = { 666 HSTT( 90, 32, 20, 26, 13), 667 HSTT( 100, 35, 23, 28, 14), 668 HSTT( 110, 32, 22, 26, 13), 669 HSTT( 130, 31, 20, 27, 13), 670 HSTT( 140, 33, 22, 26, 14), 671 HSTT( 150, 33, 21, 26, 14), 672 HSTT( 170, 32, 20, 27, 13), 673 HSTT( 180, 36, 23, 30, 15), 674 HSTT( 200, 40, 22, 33, 15), 675 HSTT( 220, 40, 22, 33, 15), 676 HSTT( 240, 44, 24, 36, 16), 677 HSTT( 250, 48, 24, 38, 17), 678 HSTT( 270, 48, 24, 38, 17), 679 HSTT( 300, 50, 27, 41, 18), 680 HSTT( 330, 56, 28, 45, 18), 681 HSTT( 360, 59, 28, 48, 19), 682 HSTT( 400, 61, 30, 50, 20), 683 HSTT( 450, 67, 31, 55, 21), 684 HSTT( 500, 73, 31, 59, 22), 685 HSTT( 550, 79, 36, 63, 24), 686 HSTT( 600, 83, 37, 68, 25), 687 HSTT( 650, 90, 38, 73, 27), 688 HSTT( 700, 95, 40, 77, 28), 689 HSTT( 750, 102, 40, 84, 28), 690 HSTT( 800, 106, 42, 87, 30), 691 HSTT( 850, 113, 44, 93, 31), 692 HSTT( 900, 118, 47, 98, 32), 693 HSTT( 950, 124, 47, 102, 34), 694 HSTT(1000, 130, 49, 107, 35), 695 HSTT(1050, 135, 51, 111, 37), 696 HSTT(1100, 139, 51, 114, 38), 697 HSTT(1150, 146, 54, 120, 40), 698 HSTT(1200, 153, 57, 125, 41), 699 HSTT(1250, 158, 58, 130, 42), 700 HSTT(1300, 163, 58, 135, 44), 701 HSTT(1350, 168, 60, 140, 45), 702 HSTT(1400, 172, 64, 144, 47), 703 HSTT(1450, 176, 65, 148, 48), 704 HSTT(1500, 181, 66, 153, 50) 705 }; 706 707 static int 708 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 709 struct dw_mipi_dsi_dphy_timing *timing) 710 { 711 int i; 712 713 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 714 if (lane_mbps < hstt_table[i].maxfreq) 715 break; 716 717 if (i == ARRAY_SIZE(hstt_table)) 718 i--; 719 720 *timing = hstt_table[i].timing; 721 722 return 0; 723 } 724 725 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 726 .init = dw_mipi_dsi_phy_init, 727 .power_on = dw_mipi_dsi_phy_power_on, 728 .power_off = dw_mipi_dsi_phy_power_off, 729 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 730 .get_timing = dw_mipi_dsi_phy_get_timing, 731 }; 732 733 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 734 { 735 if (dsi->cdata->lanecfg1_grf_reg) 736 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 737 dsi->cdata->lanecfg1); 738 739 if (dsi->cdata->lanecfg2_grf_reg) 740 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 741 dsi->cdata->lanecfg2); 742 743 if (dsi->cdata->enable_grf_reg) 744 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 745 dsi->cdata->enable); 746 } 747 748 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 749 int mux) 750 { 751 if (dsi->cdata->lcdsel_grf_reg) 752 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 753 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 754 } 755 756 static int 757 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 758 struct drm_crtc_state *crtc_state, 759 struct drm_connector_state *conn_state) 760 { 761 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 762 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 763 764 switch (dsi->format) { 765 case MIPI_DSI_FMT_RGB888: 766 s->output_mode = ROCKCHIP_OUT_MODE_P888; 767 break; 768 case MIPI_DSI_FMT_RGB666: 769 s->output_mode = ROCKCHIP_OUT_MODE_P666; 770 break; 771 case MIPI_DSI_FMT_RGB565: 772 s->output_mode = ROCKCHIP_OUT_MODE_P565; 773 break; 774 default: 775 WARN_ON(1); 776 return -EINVAL; 777 } 778 779 s->output_type = DRM_MODE_CONNECTOR_DSI; 780 if (dsi->slave) 781 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 782 783 return 0; 784 } 785 786 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 787 { 788 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 789 int ret, mux; 790 791 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 792 &dsi->encoder.encoder); 793 if (mux < 0) 794 return; 795 796 /* 797 * For the RK3399, the clk of grf must be enabled before writing grf 798 * register. And for RK3288 or other soc, this grf_clk must be NULL, 799 * the clk_prepare_enable return true directly. 800 */ 801 ret = clk_prepare_enable(dsi->grf_clk); 802 if (ret) { 803 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 804 return; 805 } 806 807 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 808 if (dsi->slave) 809 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 810 811 clk_disable_unprepare(dsi->grf_clk); 812 } 813 814 static const struct drm_encoder_helper_funcs 815 dw_mipi_dsi_encoder_helper_funcs = { 816 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 817 .enable = dw_mipi_dsi_encoder_enable, 818 }; 819 820 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 821 struct drm_device *drm_dev) 822 { 823 struct drm_encoder *encoder = &dsi->encoder.encoder; 824 int ret; 825 826 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 827 dsi->dev->of_node); 828 829 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 830 if (ret) { 831 DRM_ERROR("Failed to initialize encoder with drm\n"); 832 return ret; 833 } 834 835 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 836 837 return 0; 838 } 839 840 static struct device 841 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 842 { 843 const struct of_device_id *match; 844 struct device_node *node = NULL, *local; 845 846 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 847 848 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 849 if (!local) 850 return NULL; 851 852 while ((node = of_find_compatible_node(node, NULL, 853 match->compatible))) { 854 struct device_node *remote; 855 856 /* found ourself */ 857 if (node == dsi->dev->of_node) 858 continue; 859 860 remote = of_graph_get_remote_node(node, 1, 0); 861 if (!remote) 862 continue; 863 864 /* same display device in port1-ep0 for both */ 865 if (remote == local) { 866 struct dw_mipi_dsi_rockchip *dsi2; 867 struct platform_device *pdev; 868 869 pdev = of_find_device_by_node(node); 870 871 /* 872 * we have found the second, so will either return it 873 * or return with an error. In any case won't need the 874 * nodes anymore nor continue the loop. 875 */ 876 of_node_put(remote); 877 of_node_put(node); 878 of_node_put(local); 879 880 if (!pdev) 881 return ERR_PTR(-EPROBE_DEFER); 882 883 dsi2 = platform_get_drvdata(pdev); 884 if (!dsi2) { 885 platform_device_put(pdev); 886 return ERR_PTR(-EPROBE_DEFER); 887 } 888 889 return &pdev->dev; 890 } 891 892 of_node_put(remote); 893 } 894 895 of_node_put(local); 896 897 return NULL; 898 } 899 900 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 901 struct device *master, 902 void *data) 903 { 904 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 905 struct drm_device *drm_dev = data; 906 struct device *second; 907 bool master1, master2; 908 int ret; 909 910 second = dw_mipi_dsi_rockchip_find_second(dsi); 911 if (IS_ERR(second)) 912 return PTR_ERR(second); 913 914 if (second) { 915 master1 = of_property_read_bool(dsi->dev->of_node, 916 "clock-master"); 917 master2 = of_property_read_bool(second->of_node, 918 "clock-master"); 919 920 if (master1 && master2) { 921 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 922 return -EINVAL; 923 } 924 925 if (!master1 && !master2) { 926 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 927 return -EINVAL; 928 } 929 930 /* we are the slave in dual-DSI */ 931 if (!master1) { 932 dsi->is_slave = true; 933 return 0; 934 } 935 936 dsi->slave = dev_get_drvdata(second); 937 if (!dsi->slave) { 938 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 939 return -ENODEV; 940 } 941 942 dsi->slave->is_slave = true; 943 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 944 put_device(second); 945 } 946 947 pm_runtime_get_sync(dsi->dev); 948 if (dsi->slave) 949 pm_runtime_get_sync(dsi->slave->dev); 950 951 ret = clk_prepare_enable(dsi->pllref_clk); 952 if (ret) { 953 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 954 goto out_pm_runtime; 955 } 956 957 /* 958 * With the GRF clock running, write lane and dual-mode configurations 959 * that won't change immediately. If we waited until enable() to do 960 * this, things like panel preparation would not be able to send 961 * commands over DSI. 962 */ 963 ret = clk_prepare_enable(dsi->grf_clk); 964 if (ret) { 965 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 966 goto out_pll_clk; 967 } 968 969 dw_mipi_dsi_rockchip_config(dsi); 970 if (dsi->slave) 971 dw_mipi_dsi_rockchip_config(dsi->slave); 972 973 clk_disable_unprepare(dsi->grf_clk); 974 975 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 976 if (ret) { 977 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 978 goto out_pll_clk; 979 } 980 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 981 dev->of_node, 0, 0); 982 983 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 984 if (ret) { 985 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 986 goto out_pll_clk; 987 } 988 989 dsi->dsi_bound = true; 990 991 return 0; 992 993 out_pll_clk: 994 clk_disable_unprepare(dsi->pllref_clk); 995 out_pm_runtime: 996 pm_runtime_put(dsi->dev); 997 if (dsi->slave) 998 pm_runtime_put(dsi->slave->dev); 999 1000 return ret; 1001 } 1002 1003 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 1004 struct device *master, 1005 void *data) 1006 { 1007 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1008 1009 if (dsi->is_slave) 1010 return; 1011 1012 dsi->dsi_bound = false; 1013 1014 dw_mipi_dsi_unbind(dsi->dmd); 1015 1016 clk_disable_unprepare(dsi->pllref_clk); 1017 1018 pm_runtime_put(dsi->dev); 1019 if (dsi->slave) 1020 pm_runtime_put(dsi->slave->dev); 1021 } 1022 1023 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1024 .bind = dw_mipi_dsi_rockchip_bind, 1025 .unbind = dw_mipi_dsi_rockchip_unbind, 1026 }; 1027 1028 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1029 struct mipi_dsi_device *device) 1030 { 1031 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1032 struct device *second; 1033 int ret; 1034 1035 mutex_lock(&dsi->usage_mutex); 1036 1037 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1038 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1039 mutex_unlock(&dsi->usage_mutex); 1040 return -EBUSY; 1041 } 1042 1043 dsi->usage_mode = DW_DSI_USAGE_DSI; 1044 mutex_unlock(&dsi->usage_mutex); 1045 1046 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1047 if (ret) { 1048 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1049 ret); 1050 goto out; 1051 } 1052 1053 second = dw_mipi_dsi_rockchip_find_second(dsi); 1054 if (IS_ERR(second)) { 1055 ret = PTR_ERR(second); 1056 goto out; 1057 } 1058 if (second) { 1059 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1060 if (ret) { 1061 DRM_DEV_ERROR(second, 1062 "Failed to register component: %d\n", 1063 ret); 1064 goto out; 1065 } 1066 } 1067 1068 return 0; 1069 1070 out: 1071 mutex_lock(&dsi->usage_mutex); 1072 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1073 mutex_unlock(&dsi->usage_mutex); 1074 return ret; 1075 } 1076 1077 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1078 struct mipi_dsi_device *device) 1079 { 1080 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1081 struct device *second; 1082 1083 second = dw_mipi_dsi_rockchip_find_second(dsi); 1084 if (second && !IS_ERR(second)) 1085 component_del(second, &dw_mipi_dsi_rockchip_ops); 1086 1087 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1088 1089 mutex_lock(&dsi->usage_mutex); 1090 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1091 mutex_unlock(&dsi->usage_mutex); 1092 1093 return 0; 1094 } 1095 1096 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1097 .attach = dw_mipi_dsi_rockchip_host_attach, 1098 .detach = dw_mipi_dsi_rockchip_host_detach, 1099 }; 1100 1101 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1102 struct device *master, 1103 void *data) 1104 { 1105 /* 1106 * Nothing to do when used as a dphy. 1107 * Just make the rest of Rockchip-DRM happy 1108 * by being here. 1109 */ 1110 1111 return 0; 1112 } 1113 1114 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1115 struct device *master, 1116 void *data) 1117 { 1118 /* Nothing to do when used as a dphy. */ 1119 } 1120 1121 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1122 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1123 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1124 }; 1125 1126 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1127 { 1128 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1129 int ret; 1130 1131 mutex_lock(&dsi->usage_mutex); 1132 1133 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1134 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1135 mutex_unlock(&dsi->usage_mutex); 1136 return -EBUSY; 1137 } 1138 1139 dsi->usage_mode = DW_DSI_USAGE_PHY; 1140 mutex_unlock(&dsi->usage_mutex); 1141 1142 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1143 if (ret < 0) 1144 goto err_graph; 1145 1146 if (dsi->cdata->dphy_rx_init) { 1147 ret = clk_prepare_enable(dsi->pclk); 1148 if (ret < 0) 1149 goto err_init; 1150 1151 ret = clk_prepare_enable(dsi->grf_clk); 1152 if (ret) { 1153 clk_disable_unprepare(dsi->pclk); 1154 goto err_init; 1155 } 1156 1157 ret = dsi->cdata->dphy_rx_init(phy); 1158 clk_disable_unprepare(dsi->grf_clk); 1159 clk_disable_unprepare(dsi->pclk); 1160 if (ret < 0) 1161 goto err_init; 1162 } 1163 1164 return 0; 1165 1166 err_init: 1167 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1168 err_graph: 1169 mutex_lock(&dsi->usage_mutex); 1170 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1171 mutex_unlock(&dsi->usage_mutex); 1172 1173 return ret; 1174 } 1175 1176 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1177 { 1178 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1179 1180 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1181 1182 mutex_lock(&dsi->usage_mutex); 1183 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1184 mutex_unlock(&dsi->usage_mutex); 1185 1186 return 0; 1187 } 1188 1189 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1190 { 1191 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1192 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1193 int ret; 1194 1195 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1196 if (ret) 1197 return ret; 1198 1199 dsi->dphy_config = *config; 1200 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1201 1202 return 0; 1203 } 1204 1205 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1206 { 1207 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1208 int i, ret; 1209 1210 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1211 dsi->dphy_config.lanes, dsi->lane_mbps); 1212 1213 i = max_mbps_to_parameter(dsi->lane_mbps); 1214 if (i < 0) { 1215 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1216 dsi->lane_mbps); 1217 return i; 1218 } 1219 1220 ret = pm_runtime_resume_and_get(dsi->dev); 1221 if (ret < 0) { 1222 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1223 return ret; 1224 } 1225 1226 ret = clk_prepare_enable(dsi->pclk); 1227 if (ret) { 1228 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1229 goto err_pclk; 1230 } 1231 1232 ret = clk_prepare_enable(dsi->grf_clk); 1233 if (ret) { 1234 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1235 goto err_grf_clk; 1236 } 1237 1238 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1239 if (ret) { 1240 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1241 goto err_phy_cfg_clk; 1242 } 1243 1244 /* do soc-variant specific init */ 1245 if (dsi->cdata->dphy_rx_power_on) { 1246 ret = dsi->cdata->dphy_rx_power_on(phy); 1247 if (ret < 0) { 1248 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1249 goto err_pwr_on; 1250 } 1251 } 1252 1253 /* 1254 * Configure hsfreqrange according to frequency values 1255 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1256 */ 1257 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1258 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1259 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1260 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1261 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1262 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1263 1264 /* Normal operation */ 1265 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1266 1267 clk_disable_unprepare(dsi->phy_cfg_clk); 1268 clk_disable_unprepare(dsi->grf_clk); 1269 1270 return ret; 1271 1272 err_pwr_on: 1273 clk_disable_unprepare(dsi->phy_cfg_clk); 1274 err_phy_cfg_clk: 1275 clk_disable_unprepare(dsi->grf_clk); 1276 err_grf_clk: 1277 clk_disable_unprepare(dsi->pclk); 1278 err_pclk: 1279 pm_runtime_put(dsi->dev); 1280 return ret; 1281 } 1282 1283 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1284 { 1285 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1286 int ret; 1287 1288 ret = clk_prepare_enable(dsi->grf_clk); 1289 if (ret) { 1290 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1291 return ret; 1292 } 1293 1294 if (dsi->cdata->dphy_rx_power_off) { 1295 ret = dsi->cdata->dphy_rx_power_off(phy); 1296 if (ret < 0) 1297 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1298 } 1299 1300 clk_disable_unprepare(dsi->grf_clk); 1301 clk_disable_unprepare(dsi->pclk); 1302 1303 pm_runtime_put(dsi->dev); 1304 1305 return ret; 1306 } 1307 1308 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1309 .configure = dw_mipi_dsi_dphy_configure, 1310 .power_on = dw_mipi_dsi_dphy_power_on, 1311 .power_off = dw_mipi_dsi_dphy_power_off, 1312 .init = dw_mipi_dsi_dphy_init, 1313 .exit = dw_mipi_dsi_dphy_exit, 1314 }; 1315 1316 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1317 { 1318 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1319 int ret; 1320 1321 /* 1322 * Re-configure DSI state, if we were previously initialized. We need 1323 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1324 */ 1325 if (dsi->dsi_bound) { 1326 ret = clk_prepare_enable(dsi->grf_clk); 1327 if (ret) { 1328 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1329 return ret; 1330 } 1331 1332 dw_mipi_dsi_rockchip_config(dsi); 1333 if (dsi->slave) 1334 dw_mipi_dsi_rockchip_config(dsi->slave); 1335 1336 clk_disable_unprepare(dsi->grf_clk); 1337 } 1338 1339 return 0; 1340 } 1341 1342 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1343 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1344 }; 1345 1346 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1347 { 1348 struct device *dev = &pdev->dev; 1349 struct device_node *np = dev->of_node; 1350 struct dw_mipi_dsi_rockchip *dsi; 1351 struct phy_provider *phy_provider; 1352 struct resource *res; 1353 const struct rockchip_dw_dsi_chip_data *cdata = 1354 of_device_get_match_data(dev); 1355 int ret, i; 1356 1357 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1358 if (!dsi) 1359 return -ENOMEM; 1360 1361 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1362 if (IS_ERR(dsi->base)) { 1363 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1364 return PTR_ERR(dsi->base); 1365 } 1366 1367 i = 0; 1368 while (cdata[i].reg) { 1369 if (cdata[i].reg == res->start) { 1370 dsi->cdata = &cdata[i]; 1371 break; 1372 } 1373 1374 i++; 1375 } 1376 1377 if (!dsi->cdata) { 1378 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1379 return -EINVAL; 1380 } 1381 1382 /* try to get a possible external dphy */ 1383 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1384 if (IS_ERR(dsi->phy)) { 1385 ret = PTR_ERR(dsi->phy); 1386 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1387 return ret; 1388 } 1389 1390 dsi->pclk = devm_clk_get(dev, "pclk"); 1391 if (IS_ERR(dsi->pclk)) { 1392 ret = PTR_ERR(dsi->pclk); 1393 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1394 return ret; 1395 } 1396 1397 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1398 if (IS_ERR(dsi->pllref_clk)) { 1399 if (dsi->phy) { 1400 /* 1401 * if external phy is present, pll will be 1402 * generated there. 1403 */ 1404 dsi->pllref_clk = NULL; 1405 } else { 1406 ret = PTR_ERR(dsi->pllref_clk); 1407 DRM_DEV_ERROR(dev, 1408 "Unable to get pll reference clock: %d\n", 1409 ret); 1410 return ret; 1411 } 1412 } 1413 1414 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1415 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1416 if (IS_ERR(dsi->phy_cfg_clk)) { 1417 ret = PTR_ERR(dsi->phy_cfg_clk); 1418 DRM_DEV_ERROR(dev, 1419 "Unable to get phy_cfg_clk: %d\n", ret); 1420 return ret; 1421 } 1422 } 1423 1424 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1425 dsi->grf_clk = devm_clk_get(dev, "grf"); 1426 if (IS_ERR(dsi->grf_clk)) { 1427 ret = PTR_ERR(dsi->grf_clk); 1428 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1429 return ret; 1430 } 1431 } 1432 1433 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1434 if (IS_ERR(dsi->grf_regmap)) { 1435 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1436 return PTR_ERR(dsi->grf_regmap); 1437 } 1438 1439 dsi->dev = dev; 1440 dsi->pdata.base = dsi->base; 1441 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1442 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1443 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1444 dsi->pdata.priv_data = dsi; 1445 platform_set_drvdata(pdev, dsi); 1446 1447 mutex_init(&dsi->usage_mutex); 1448 1449 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1450 if (IS_ERR(dsi->dphy)) { 1451 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1452 return PTR_ERR(dsi->dphy); 1453 } 1454 1455 phy_set_drvdata(dsi->dphy, dsi); 1456 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1457 if (IS_ERR(phy_provider)) 1458 return PTR_ERR(phy_provider); 1459 1460 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1461 if (IS_ERR(dsi->dmd)) { 1462 ret = PTR_ERR(dsi->dmd); 1463 if (ret != -EPROBE_DEFER) 1464 DRM_DEV_ERROR(dev, 1465 "Failed to probe dw_mipi_dsi: %d\n", ret); 1466 return ret; 1467 } 1468 1469 return 0; 1470 } 1471 1472 static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1473 { 1474 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1475 1476 dw_mipi_dsi_remove(dsi->dmd); 1477 } 1478 1479 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1480 { 1481 .reg = 0xff450000, 1482 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1483 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1484 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1485 PX30_DSI_LCDC_SEL), 1486 1487 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1488 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1489 PX30_DSI_FORCERXMODE | 1490 PX30_DSI_FORCETXSTOPMODE), 1491 1492 .max_data_lanes = 4, 1493 }, 1494 { /* sentinel */ } 1495 }; 1496 1497 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1498 { 1499 .reg = 0xff960000, 1500 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1501 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1502 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1503 1504 .max_data_lanes = 4, 1505 }, 1506 { 1507 .reg = 0xff964000, 1508 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1509 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1510 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1511 1512 .max_data_lanes = 4, 1513 }, 1514 { /* sentinel */ } 1515 }; 1516 1517 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1518 { 1519 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1520 1521 /* 1522 * Set TX1RX1 source to isp1. 1523 * Assume ISP0 is supplied by the RX0 dphy. 1524 */ 1525 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1526 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); 1527 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1528 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1529 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1530 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); 1531 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1532 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1533 1534 return 0; 1535 } 1536 1537 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1538 { 1539 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1540 1541 /* tester reset pulse */ 1542 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1543 usleep_range(100, 150); 1544 1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1546 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); 1547 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1548 HIWORD_UPDATE(RK3399_TXRX_BASEDIR, RK3399_TXRX_BASEDIR)); 1549 1550 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1551 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); 1552 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1553 HIWORD_UPDATE(0, RK3399_DSI1_FORCETXSTOPMODE)); 1554 1555 /* Disable lane turn around, which is ignored in receive mode */ 1556 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1557 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); 1558 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1559 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, 1560 RK3399_DSI1_TURNDISABLE)); 1561 usleep_range(100, 150); 1562 1563 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1564 usleep_range(100, 150); 1565 1566 /* Enable dphy lanes */ 1567 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1568 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), 1569 RK3399_DSI1_ENABLE)); 1570 1571 usleep_range(100, 150); 1572 1573 return 0; 1574 } 1575 1576 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1577 { 1578 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1579 1580 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1581 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); 1582 1583 return 0; 1584 } 1585 1586 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1587 { 1588 .reg = 0xff960000, 1589 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1590 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1591 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1592 RK3399_DSI0_LCDC_SEL), 1593 1594 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1595 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1596 RK3399_DSI0_TURNDISABLE | 1597 RK3399_DSI0_FORCETXSTOPMODE | 1598 RK3399_DSI0_FORCERXMODE), 1599 1600 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1601 .max_data_lanes = 4, 1602 }, 1603 { 1604 .reg = 0xff968000, 1605 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1606 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1607 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1608 RK3399_DSI1_LCDC_SEL), 1609 1610 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1611 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1612 RK3399_DSI1_FORCETXSTOPMODE | 1613 RK3399_DSI1_FORCERXMODE | 1614 RK3399_DSI1_ENABLE), 1615 1616 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1617 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1618 RK3399_TXRX_ENABLECLK, 1619 RK3399_TXRX_MASTERSLAVEZ | 1620 RK3399_TXRX_ENABLECLK | 1621 RK3399_TXRX_BASEDIR), 1622 1623 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1624 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1625 1626 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1627 .max_data_lanes = 4, 1628 1629 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1630 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1631 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1632 }, 1633 { /* sentinel */ } 1634 }; 1635 1636 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1637 { 1638 .reg = 0xfe060000, 1639 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1640 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | 1641 RK3568_DSI0_FORCETXSTOPMODE | 1642 RK3568_DSI0_TURNDISABLE | 1643 RK3568_DSI0_FORCERXMODE), 1644 .max_data_lanes = 4, 1645 }, 1646 { 1647 .reg = 0xfe070000, 1648 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1649 .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | 1650 RK3568_DSI1_FORCETXSTOPMODE | 1651 RK3568_DSI1_TURNDISABLE | 1652 RK3568_DSI1_FORCERXMODE), 1653 .max_data_lanes = 4, 1654 }, 1655 { /* sentinel */ } 1656 }; 1657 1658 static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { 1659 { 1660 .reg = 0xffb30000, 1661 .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON, 1662 .lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE | 1663 RV1126_DSI_FORCERXMODE | 1664 RV1126_DSI_FORCETXSTOPMODE), 1665 .max_data_lanes = 4, 1666 }, 1667 { /* sentinel */ } 1668 }; 1669 1670 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1671 { 1672 .compatible = "rockchip,px30-mipi-dsi", 1673 .data = &px30_chip_data, 1674 }, { 1675 .compatible = "rockchip,rk3288-mipi-dsi", 1676 .data = &rk3288_chip_data, 1677 }, { 1678 .compatible = "rockchip,rk3399-mipi-dsi", 1679 .data = &rk3399_chip_data, 1680 }, { 1681 .compatible = "rockchip,rk3568-mipi-dsi", 1682 .data = &rk3568_chip_data, 1683 }, { 1684 .compatible = "rockchip,rv1126-mipi-dsi", 1685 .data = &rv1126_chip_data, 1686 }, 1687 { /* sentinel */ } 1688 }; 1689 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1690 1691 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1692 .probe = dw_mipi_dsi_rockchip_probe, 1693 .remove_new = dw_mipi_dsi_rockchip_remove, 1694 .driver = { 1695 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1696 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1697 .name = "dw-mipi-dsi-rockchip", 1698 /* 1699 * For dual-DSI display, one DSI pokes at the other DSI's 1700 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1701 * safe for asynchronous probe. 1702 */ 1703 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1704 }, 1705 }; 1706