1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/hw_bitfield.h> 11 #include <linux/iopoll.h> 12 #include <linux/math64.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/of_platform.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/bridge/dw_mipi_dsi.h> 25 #include <drm/drm_mipi_dsi.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_simple_kms_helper.h> 28 29 #include "rockchip_drm_drv.h" 30 31 #define DSI_PHY_RSTZ 0xa0 32 #define PHY_DISFORCEPLL 0 33 #define PHY_ENFORCEPLL BIT(3) 34 #define PHY_DISABLECLK 0 35 #define PHY_ENABLECLK BIT(2) 36 #define PHY_RSTZ 0 37 #define PHY_UNRSTZ BIT(1) 38 #define PHY_SHUTDOWNZ 0 39 #define PHY_UNSHUTDOWNZ BIT(0) 40 41 #define DSI_PHY_IF_CFG 0xa4 42 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 43 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 44 45 #define DSI_PHY_STATUS 0xb0 46 #define LOCK BIT(0) 47 #define STOP_STATE_CLK_LANE BIT(2) 48 49 #define DSI_PHY_TST_CTRL0 0xb4 50 #define PHY_TESTCLK BIT(1) 51 #define PHY_UNTESTCLK 0 52 #define PHY_TESTCLR BIT(0) 53 #define PHY_UNTESTCLR 0 54 55 #define DSI_PHY_TST_CTRL1 0xb8 56 #define PHY_TESTEN BIT(16) 57 #define PHY_UNTESTEN 0 58 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 59 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 60 61 #define DSI_INT_ST0 0xbc 62 #define DSI_INT_ST1 0xc0 63 #define DSI_INT_MSK0 0xc4 64 #define DSI_INT_MSK1 0xc8 65 66 #define PHY_STATUS_TIMEOUT_US 10000 67 #define CMD_PKT_STATUS_TIMEOUT_US 20000 68 69 #define BYPASS_VCO_RANGE BIT(7) 70 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 71 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 72 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 73 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 74 #define REF_BIAS_CUR_SEL BIT(0) 75 76 #define CP_CURRENT_3UA 0x1 77 #define CP_CURRENT_4_5UA 0x2 78 #define CP_CURRENT_7_5UA 0x6 79 #define CP_CURRENT_6UA 0x9 80 #define CP_CURRENT_12UA 0xb 81 #define CP_CURRENT_SEL(val) ((val) & 0xf) 82 #define CP_PROGRAM_EN BIT(7) 83 84 #define LPF_RESISTORS_15_5KOHM 0x1 85 #define LPF_RESISTORS_13KOHM 0x2 86 #define LPF_RESISTORS_11_5KOHM 0x4 87 #define LPF_RESISTORS_10_5KOHM 0x8 88 #define LPF_RESISTORS_8KOHM 0x10 89 #define LPF_PROGRAM_EN BIT(6) 90 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 91 92 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 93 94 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 95 #define LOW_PROGRAM_EN 0 96 #define HIGH_PROGRAM_EN BIT(7) 97 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 98 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 99 #define PLL_LOOP_DIV_EN BIT(5) 100 #define PLL_INPUT_DIV_EN BIT(4) 101 102 #define POWER_CONTROL BIT(6) 103 #define INTERNAL_REG_CURRENT BIT(3) 104 #define BIAS_BLOCK_ON BIT(2) 105 #define BANDGAP_ON BIT(0) 106 107 #define TER_RESISTOR_HIGH BIT(7) 108 #define TER_RESISTOR_LOW 0 109 #define LEVEL_SHIFTERS_ON BIT(6) 110 #define TER_CAL_DONE BIT(5) 111 #define SETRD_MAX (0x7 << 2) 112 #define POWER_MANAGE BIT(1) 113 #define TER_RESISTORS_ON BIT(0) 114 115 #define BIASEXTR_SEL(val) ((val) & 0x7) 116 #define BANDGAP_SEL(val) ((val) & 0x7) 117 #define TLP_PROGRAM_EN BIT(7) 118 #define THS_PRE_PROGRAM_EN BIT(7) 119 #define THS_ZERO_PROGRAM_EN BIT(6) 120 121 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 122 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 123 #define PLL_LPF_AND_CP_CONTROL 0x12 124 #define PLL_INPUT_DIVIDER_RATIO 0x17 125 #define PLL_LOOP_DIVIDER_RATIO 0x18 126 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 127 #define BANDGAP_AND_BIAS_CONTROL 0x20 128 #define TERMINATION_RESISTER_CONTROL 0x21 129 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 130 #define HS_RX_CONTROL_OF_LANE_CLK 0x34 131 #define HS_RX_CONTROL_OF_LANE_0 0x44 132 #define HS_RX_CONTROL_OF_LANE_1 0x54 133 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 134 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 135 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 136 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 137 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 138 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 139 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 140 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 141 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 142 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 143 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 144 #define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75 145 #define HS_RX_CONTROL_OF_LANE_2 0x84 146 #define HS_RX_CONTROL_OF_LANE_3 0x94 147 148 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 149 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 150 151 #define PX30_GRF_PD_VO_CON1 0x0438 152 #define PX30_DSI_FORCETXSTOPMODE (0xfUL << 7) 153 #define PX30_DSI_FORCERXMODE BIT(6) 154 #define PX30_DSI_TURNDISABLE BIT(5) 155 #define PX30_DSI_LCDC_SEL BIT(0) 156 157 #define RK3128_GRF_LVDS_CON0 0x0150 158 #define RK3128_DSI_FORCETXSTOPMODE GENMASK(13, 10) 159 #define RK3128_DSI_FORCERXMODE BIT(9) 160 #define RK3128_DSI_TURNDISABLE BIT(8) 161 162 #define RK3288_GRF_SOC_CON6 0x025c 163 #define RK3288_DSI0_LCDC_SEL BIT(6) 164 #define RK3288_DSI1_LCDC_SEL BIT(9) 165 166 #define RK3399_GRF_SOC_CON20 0x6250 167 #define RK3399_DSI0_LCDC_SEL BIT(0) 168 #define RK3399_DSI1_LCDC_SEL BIT(4) 169 170 #define RK3399_GRF_SOC_CON22 0x6258 171 #define RK3399_DSI0_TURNREQUEST (0xfUL << 12) 172 #define RK3399_DSI0_TURNDISABLE (0xfUL << 8) 173 #define RK3399_DSI0_FORCETXSTOPMODE (0xfUL << 4) 174 #define RK3399_DSI0_FORCERXMODE (0xfUL << 0) 175 176 #define RK3399_GRF_SOC_CON23 0x625c 177 #define RK3399_DSI1_TURNDISABLE (0xfUL << 12) 178 #define RK3399_DSI1_FORCETXSTOPMODE (0xfUL << 8) 179 #define RK3399_DSI1_FORCERXMODE (0xfUL << 4) 180 #define RK3399_DSI1_ENABLE (0xfUL << 0) 181 182 #define RK3399_GRF_SOC_CON24 0x6260 183 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 184 #define RK3399_TXRX_ENABLECLK BIT(6) 185 #define RK3399_TXRX_BASEDIR BIT(5) 186 #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) 187 #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) 188 189 #define RK3568_GRF_VO_CON2 0x0368 190 #define RK3568_DSI0_SKEWCALHS (0x1fUL << 11) 191 #define RK3568_DSI0_FORCETXSTOPMODE (0xfUL << 4) 192 #define RK3568_DSI0_TURNDISABLE BIT(2) 193 #define RK3568_DSI0_FORCERXMODE BIT(0) 194 195 /* 196 * Note these registers do not appear in the datasheet, they are 197 * however present in the BSP driver which is where these values 198 * come from. Name GRF_VO_CON3 is assumed. 199 */ 200 #define RK3568_GRF_VO_CON3 0x36c 201 #define RK3568_DSI1_SKEWCALHS (0x1fUL << 11) 202 #define RK3568_DSI1_FORCETXSTOPMODE (0xfUL << 4) 203 #define RK3568_DSI1_TURNDISABLE BIT(2) 204 #define RK3568_DSI1_FORCERXMODE BIT(0) 205 206 #define RV1126_GRF_DSIPHY_CON 0x10220 207 #define RV1126_DSI_FORCETXSTOPMODE (0xfUL << 4) 208 #define RV1126_DSI_TURNDISABLE BIT(2) 209 #define RV1126_DSI_FORCERXMODE BIT(0) 210 211 enum { 212 DW_DSI_USAGE_IDLE, 213 DW_DSI_USAGE_DSI, 214 DW_DSI_USAGE_PHY, 215 }; 216 217 enum { 218 BANDGAP_97_07, 219 BANDGAP_98_05, 220 BANDGAP_99_02, 221 BANDGAP_100_00, 222 BANDGAP_93_17, 223 BANDGAP_94_15, 224 BANDGAP_95_12, 225 BANDGAP_96_10, 226 }; 227 228 enum { 229 BIASEXTR_87_1, 230 BIASEXTR_91_5, 231 BIASEXTR_95_9, 232 BIASEXTR_100, 233 BIASEXTR_105_94, 234 BIASEXTR_111_88, 235 BIASEXTR_118_8, 236 BIASEXTR_127_7, 237 }; 238 239 struct rockchip_dw_dsi_chip_data { 240 u32 reg; 241 242 u32 lcdsel_grf_reg; 243 u32 lcdsel_big; 244 u32 lcdsel_lit; 245 246 u32 enable_grf_reg; 247 u32 enable; 248 249 u32 lanecfg1_grf_reg; 250 u32 lanecfg1; 251 u32 lanecfg2_grf_reg; 252 u32 lanecfg2; 253 254 int (*dphy_rx_init)(struct phy *phy); 255 int (*dphy_rx_power_on)(struct phy *phy); 256 int (*dphy_rx_power_off)(struct phy *phy); 257 258 unsigned int flags; 259 unsigned int max_data_lanes; 260 }; 261 262 struct dw_mipi_dsi_rockchip { 263 struct device *dev; 264 struct rockchip_encoder encoder; 265 void __iomem *base; 266 267 struct regmap *grf_regmap; 268 struct clk *pclk; 269 struct clk *pllref_clk; 270 struct clk *grf_clk; 271 struct clk *phy_cfg_clk; 272 273 /* dual-channel */ 274 bool is_slave; 275 struct dw_mipi_dsi_rockchip *slave; 276 277 /* optional external dphy */ 278 struct phy *phy; 279 union phy_configure_opts phy_opts; 280 281 /* being a phy for other mipi hosts */ 282 unsigned int usage_mode; 283 struct mutex usage_mutex; 284 struct phy *dphy; 285 struct phy_configure_opts_mipi_dphy dphy_config; 286 287 unsigned int lane_mbps; /* per lane */ 288 u16 input_div; 289 u16 feedback_div; 290 u32 format; 291 292 struct dw_mipi_dsi *dmd; 293 const struct rockchip_dw_dsi_chip_data *cdata; 294 struct dw_mipi_dsi_plat_data pdata; 295 296 bool dsi_bound; 297 }; 298 299 static struct dw_mipi_dsi_rockchip *to_dsi(struct drm_encoder *encoder) 300 { 301 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 302 303 return container_of(rkencoder, struct dw_mipi_dsi_rockchip, encoder); 304 } 305 306 struct dphy_pll_parameter_map { 307 unsigned int max_mbps; 308 u8 hsfreqrange; 309 u8 icpctrl; 310 u8 lpfctrl; 311 }; 312 313 /* The table is based on 27MHz DPHY pll reference clock. */ 314 static const struct dphy_pll_parameter_map dppa_map[] = { 315 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 316 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 317 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 318 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 319 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 320 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 321 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 322 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 323 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 324 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 325 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 326 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 327 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 328 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 329 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 330 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 331 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 332 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 333 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 334 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 335 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 336 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 337 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 338 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 339 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 340 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 341 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 342 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 343 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 344 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 345 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 346 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 347 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 348 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 349 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 350 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 351 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 352 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 353 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 354 }; 355 356 static int max_mbps_to_parameter(unsigned int max_mbps) 357 { 358 int i; 359 360 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 361 if (dppa_map[i].max_mbps >= max_mbps) 362 return i; 363 364 return -EINVAL; 365 } 366 367 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 368 { 369 writel(val, dsi->base + reg); 370 } 371 372 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 373 u8 test_code, 374 u8 test_data) 375 { 376 /* 377 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 378 * is latched internally as the current test code. Test data is 379 * programmed internally by rising edge on TESTCLK. 380 */ 381 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 382 383 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 384 PHY_TESTDIN(test_code)); 385 386 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 387 388 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 389 PHY_TESTDIN(test_data)); 390 391 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 392 } 393 394 /* 395 * ns2bc - Nanoseconds to byte clock cycles 396 */ 397 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 398 { 399 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 400 } 401 402 /* 403 * ns2ui - Nanoseconds to UI time periods 404 */ 405 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 406 { 407 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 408 } 409 410 static int dw_mipi_dsi_phy_init(void *priv_data) 411 { 412 struct dw_mipi_dsi_rockchip *dsi = priv_data; 413 int ret, i, vco; 414 415 if (dsi->phy) 416 return 0; 417 418 /* 419 * Get vco from frequency(lane_mbps) 420 * vco frequency table 421 * 000 - between 80 and 200 MHz 422 * 001 - between 200 and 300 MHz 423 * 010 - between 300 and 500 MHz 424 * 011 - between 500 and 700 MHz 425 * 100 - between 700 and 900 MHz 426 * 101 - between 900 and 1100 MHz 427 * 110 - between 1100 and 1300 MHz 428 * 111 - between 1300 and 1500 MHz 429 */ 430 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 431 432 i = max_mbps_to_parameter(dsi->lane_mbps); 433 if (i < 0) { 434 DRM_DEV_ERROR(dsi->dev, 435 "failed to get parameter for %dmbps clock\n", 436 dsi->lane_mbps); 437 return i; 438 } 439 440 ret = clk_prepare_enable(dsi->phy_cfg_clk); 441 if (ret) { 442 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 443 return ret; 444 } 445 446 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 447 BYPASS_VCO_RANGE | 448 VCO_RANGE_CON_SEL(vco) | 449 VCO_IN_CAP_CON_LOW | 450 REF_BIAS_CUR_SEL); 451 452 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 453 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 454 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 455 CP_PROGRAM_EN | LPF_PROGRAM_EN | 456 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 457 458 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 459 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 460 461 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 462 INPUT_DIVIDER(dsi->input_div)); 463 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 464 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 465 LOW_PROGRAM_EN); 466 /* 467 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 468 * to make the configured LSB effective according to IP simulation 469 * and lab test results. 470 * Only in this way can we get correct mipi phy pll frequency. 471 */ 472 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 473 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 474 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 475 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 476 HIGH_PROGRAM_EN); 477 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 478 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 479 480 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 481 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 482 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 483 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 484 485 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 486 POWER_CONTROL | INTERNAL_REG_CURRENT | 487 BIAS_BLOCK_ON | BANDGAP_ON); 488 489 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 490 TER_RESISTOR_LOW | TER_CAL_DONE | 491 SETRD_MAX | TER_RESISTORS_ON); 492 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 493 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 494 SETRD_MAX | POWER_MANAGE | 495 TER_RESISTORS_ON); 496 497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 498 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 499 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 500 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 501 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 502 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 503 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 504 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 505 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 506 BIT(5) | ns2bc(dsi, 100)); 507 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 508 BIT(5) | (ns2bc(dsi, 60) + 7)); 509 510 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 511 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 512 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 513 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 514 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 515 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 516 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 517 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 518 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 519 BIT(5) | ns2bc(dsi, 100)); 520 521 clk_disable_unprepare(dsi->phy_cfg_clk); 522 523 return ret; 524 } 525 526 static void dw_mipi_dsi_phy_power_on(void *priv_data) 527 { 528 struct dw_mipi_dsi_rockchip *dsi = priv_data; 529 int ret; 530 531 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 532 if (ret) { 533 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 534 return; 535 } 536 537 phy_configure(dsi->phy, &dsi->phy_opts); 538 phy_power_on(dsi->phy); 539 } 540 541 static void dw_mipi_dsi_phy_power_off(void *priv_data) 542 { 543 struct dw_mipi_dsi_rockchip *dsi = priv_data; 544 545 phy_power_off(dsi->phy); 546 } 547 548 static int 549 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 550 unsigned long mode_flags, u32 lanes, u32 format, 551 unsigned int *lane_mbps) 552 { 553 struct dw_mipi_dsi_rockchip *dsi = priv_data; 554 int bpp; 555 unsigned long mpclk, tmp; 556 unsigned int target_mbps = 1000; 557 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 558 unsigned long best_freq = 0; 559 unsigned long fvco_min, fvco_max, fin, fout; 560 unsigned int min_prediv, max_prediv; 561 unsigned int _prediv, best_prediv; 562 unsigned long _fbdiv, best_fbdiv; 563 unsigned long min_delta = ULONG_MAX; 564 565 dsi->format = format; 566 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 567 if (bpp < 0) { 568 DRM_DEV_ERROR(dsi->dev, 569 "failed to get bpp for pixel format %d\n", 570 dsi->format); 571 return bpp; 572 } 573 574 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 575 if (mpclk) { 576 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 577 tmp = mpclk * (bpp / lanes) * 10 / 8; 578 if (tmp < max_mbps) 579 target_mbps = tmp; 580 else 581 DRM_DEV_ERROR(dsi->dev, 582 "DPHY clock frequency is out of range\n"); 583 } 584 585 /* for external phy only a the mipi_dphy_config is necessary */ 586 if (dsi->phy) { 587 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 588 bpp, lanes, 589 &dsi->phy_opts.mipi_dphy); 590 dsi->lane_mbps = target_mbps; 591 *lane_mbps = dsi->lane_mbps; 592 593 return 0; 594 } 595 596 fin = clk_get_rate(dsi->pllref_clk); 597 fout = target_mbps * USEC_PER_SEC; 598 599 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 600 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 601 max_prediv = fin / (5 * USEC_PER_SEC); 602 603 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 604 fvco_min = 80 * USEC_PER_SEC; 605 fvco_max = 1500 * USEC_PER_SEC; 606 607 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 608 u64 tmp; 609 u32 delta; 610 /* Fvco = Fref * M / N */ 611 tmp = (u64)fout * _prediv; 612 do_div(tmp, fin); 613 _fbdiv = tmp; 614 /* 615 * Due to the use of a "by 2 pre-scaler," the range of the 616 * feedback multiplication value M is limited to even division 617 * numbers, and m must be greater than 6, not bigger than 512. 618 */ 619 if (_fbdiv < 6 || _fbdiv > 512) 620 continue; 621 622 _fbdiv += _fbdiv % 2; 623 624 tmp = (u64)_fbdiv * fin; 625 do_div(tmp, _prediv); 626 if (tmp < fvco_min || tmp > fvco_max) 627 continue; 628 629 delta = abs(fout - tmp); 630 if (delta < min_delta) { 631 best_prediv = _prediv; 632 best_fbdiv = _fbdiv; 633 min_delta = delta; 634 best_freq = tmp; 635 } 636 } 637 638 if (best_freq) { 639 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 640 *lane_mbps = dsi->lane_mbps; 641 dsi->input_div = best_prediv; 642 dsi->feedback_div = best_fbdiv; 643 } else { 644 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 645 return -EINVAL; 646 } 647 648 return 0; 649 } 650 651 struct hstt { 652 unsigned int maxfreq; 653 struct dw_mipi_dsi_dphy_timing timing; 654 }; 655 656 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 657 { \ 658 .maxfreq = _maxfreq, \ 659 .timing = { \ 660 .clk_lp2hs = _c_lp2hs, \ 661 .clk_hs2lp = _c_hs2lp, \ 662 .data_lp2hs = _d_lp2hs, \ 663 .data_hs2lp = _d_hs2lp, \ 664 } \ 665 } 666 667 /* Table A-3 High-Speed Transition Times */ 668 static struct hstt hstt_table[] = { 669 HSTT( 90, 32, 20, 26, 13), 670 HSTT( 100, 35, 23, 28, 14), 671 HSTT( 110, 32, 22, 26, 13), 672 HSTT( 130, 31, 20, 27, 13), 673 HSTT( 140, 33, 22, 26, 14), 674 HSTT( 150, 33, 21, 26, 14), 675 HSTT( 170, 32, 20, 27, 13), 676 HSTT( 180, 36, 23, 30, 15), 677 HSTT( 200, 40, 22, 33, 15), 678 HSTT( 220, 40, 22, 33, 15), 679 HSTT( 240, 44, 24, 36, 16), 680 HSTT( 250, 48, 24, 38, 17), 681 HSTT( 270, 48, 24, 38, 17), 682 HSTT( 300, 50, 27, 41, 18), 683 HSTT( 330, 56, 28, 45, 18), 684 HSTT( 360, 59, 28, 48, 19), 685 HSTT( 400, 61, 30, 50, 20), 686 HSTT( 450, 67, 31, 55, 21), 687 HSTT( 500, 73, 31, 59, 22), 688 HSTT( 550, 79, 36, 63, 24), 689 HSTT( 600, 83, 37, 68, 25), 690 HSTT( 650, 90, 38, 73, 27), 691 HSTT( 700, 95, 40, 77, 28), 692 HSTT( 750, 102, 40, 84, 28), 693 HSTT( 800, 106, 42, 87, 30), 694 HSTT( 850, 113, 44, 93, 31), 695 HSTT( 900, 118, 47, 98, 32), 696 HSTT( 950, 124, 47, 102, 34), 697 HSTT(1000, 130, 49, 107, 35), 698 HSTT(1050, 135, 51, 111, 37), 699 HSTT(1100, 139, 51, 114, 38), 700 HSTT(1150, 146, 54, 120, 40), 701 HSTT(1200, 153, 57, 125, 41), 702 HSTT(1250, 158, 58, 130, 42), 703 HSTT(1300, 163, 58, 135, 44), 704 HSTT(1350, 168, 60, 140, 45), 705 HSTT(1400, 172, 64, 144, 47), 706 HSTT(1450, 176, 65, 148, 48), 707 HSTT(1500, 181, 66, 153, 50) 708 }; 709 710 static int 711 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 712 struct dw_mipi_dsi_dphy_timing *timing) 713 { 714 int i; 715 716 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 717 if (lane_mbps < hstt_table[i].maxfreq) 718 break; 719 720 if (i == ARRAY_SIZE(hstt_table)) 721 i--; 722 723 *timing = hstt_table[i].timing; 724 725 return 0; 726 } 727 728 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 729 .init = dw_mipi_dsi_phy_init, 730 .power_on = dw_mipi_dsi_phy_power_on, 731 .power_off = dw_mipi_dsi_phy_power_off, 732 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 733 .get_timing = dw_mipi_dsi_phy_get_timing, 734 }; 735 736 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 737 { 738 if (dsi->cdata->lanecfg1_grf_reg) 739 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 740 dsi->cdata->lanecfg1); 741 742 if (dsi->cdata->lanecfg2_grf_reg) 743 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 744 dsi->cdata->lanecfg2); 745 746 if (dsi->cdata->enable_grf_reg) 747 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 748 dsi->cdata->enable); 749 } 750 751 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 752 int mux) 753 { 754 if (dsi->cdata->lcdsel_grf_reg) 755 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 756 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 757 } 758 759 static int 760 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 761 struct drm_crtc_state *crtc_state, 762 struct drm_connector_state *conn_state) 763 { 764 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 765 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 766 767 switch (dsi->format) { 768 case MIPI_DSI_FMT_RGB888: 769 s->output_mode = ROCKCHIP_OUT_MODE_P888; 770 break; 771 case MIPI_DSI_FMT_RGB666: 772 s->output_mode = ROCKCHIP_OUT_MODE_P666; 773 break; 774 case MIPI_DSI_FMT_RGB565: 775 s->output_mode = ROCKCHIP_OUT_MODE_P565; 776 break; 777 default: 778 WARN_ON(1); 779 return -EINVAL; 780 } 781 782 s->output_type = DRM_MODE_CONNECTOR_DSI; 783 if (dsi->slave) 784 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 785 786 return 0; 787 } 788 789 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 790 { 791 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 792 int ret, mux; 793 794 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 795 &dsi->encoder.encoder); 796 if (mux < 0) 797 return; 798 799 /* 800 * For the RK3399, the clk of grf must be enabled before writing grf 801 * register. And for RK3288 or other soc, this grf_clk must be NULL, 802 * the clk_prepare_enable return true directly. 803 */ 804 ret = clk_prepare_enable(dsi->grf_clk); 805 if (ret) { 806 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 807 return; 808 } 809 810 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 811 if (dsi->slave) 812 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 813 814 clk_disable_unprepare(dsi->grf_clk); 815 } 816 817 static const struct drm_encoder_helper_funcs 818 dw_mipi_dsi_encoder_helper_funcs = { 819 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 820 .enable = dw_mipi_dsi_encoder_enable, 821 }; 822 823 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 824 struct drm_device *drm_dev) 825 { 826 struct drm_encoder *encoder = &dsi->encoder.encoder; 827 int ret; 828 829 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 830 dsi->dev->of_node); 831 832 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 833 if (ret) { 834 DRM_ERROR("Failed to initialize encoder with drm\n"); 835 return ret; 836 } 837 838 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 839 840 return 0; 841 } 842 843 static struct device 844 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 845 { 846 const struct of_device_id *match; 847 struct device_node *node = NULL, *local; 848 849 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 850 851 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 852 if (!local) 853 return NULL; 854 855 while ((node = of_find_compatible_node(node, NULL, 856 match->compatible))) { 857 struct device_node *remote; 858 859 /* found ourself */ 860 if (node == dsi->dev->of_node) 861 continue; 862 863 remote = of_graph_get_remote_node(node, 1, 0); 864 if (!remote) 865 continue; 866 867 /* same display device in port1-ep0 for both */ 868 if (remote == local) { 869 struct dw_mipi_dsi_rockchip *dsi2; 870 struct platform_device *pdev; 871 872 pdev = of_find_device_by_node(node); 873 874 /* 875 * we have found the second, so will either return it 876 * or return with an error. In any case won't need the 877 * nodes anymore nor continue the loop. 878 */ 879 of_node_put(remote); 880 of_node_put(node); 881 of_node_put(local); 882 883 if (!pdev) 884 return ERR_PTR(-EPROBE_DEFER); 885 886 dsi2 = platform_get_drvdata(pdev); 887 if (!dsi2) { 888 platform_device_put(pdev); 889 return ERR_PTR(-EPROBE_DEFER); 890 } 891 892 return &pdev->dev; 893 } 894 895 of_node_put(remote); 896 } 897 898 of_node_put(local); 899 900 return NULL; 901 } 902 903 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 904 struct device *master, 905 void *data) 906 { 907 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 908 struct drm_device *drm_dev = data; 909 struct device *second; 910 bool master1, master2; 911 int ret; 912 913 second = dw_mipi_dsi_rockchip_find_second(dsi); 914 if (IS_ERR(second)) 915 return PTR_ERR(second); 916 917 if (second) { 918 master1 = of_property_read_bool(dsi->dev->of_node, 919 "clock-master"); 920 master2 = of_property_read_bool(second->of_node, 921 "clock-master"); 922 923 if (master1 && master2) { 924 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 925 return -EINVAL; 926 } 927 928 if (!master1 && !master2) { 929 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 930 return -EINVAL; 931 } 932 933 /* we are the slave in dual-DSI */ 934 if (!master1) { 935 dsi->is_slave = true; 936 return 0; 937 } 938 939 dsi->slave = dev_get_drvdata(second); 940 if (!dsi->slave) { 941 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 942 return -ENODEV; 943 } 944 945 dsi->slave->is_slave = true; 946 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 947 put_device(second); 948 } 949 950 pm_runtime_get_sync(dsi->dev); 951 if (dsi->slave) 952 pm_runtime_get_sync(dsi->slave->dev); 953 954 ret = clk_prepare_enable(dsi->pllref_clk); 955 if (ret) { 956 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 957 goto out_pm_runtime; 958 } 959 960 /* 961 * With the GRF clock running, write lane and dual-mode configurations 962 * that won't change immediately. If we waited until enable() to do 963 * this, things like panel preparation would not be able to send 964 * commands over DSI. 965 */ 966 ret = clk_prepare_enable(dsi->grf_clk); 967 if (ret) { 968 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 969 goto out_pll_clk; 970 } 971 972 dw_mipi_dsi_rockchip_config(dsi); 973 if (dsi->slave) 974 dw_mipi_dsi_rockchip_config(dsi->slave); 975 976 clk_disable_unprepare(dsi->grf_clk); 977 978 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 979 if (ret) { 980 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 981 goto out_pll_clk; 982 } 983 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, 984 dev->of_node, 0, 0); 985 986 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); 987 if (ret) { 988 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 989 goto out_pll_clk; 990 } 991 992 dsi->dsi_bound = true; 993 994 return 0; 995 996 out_pll_clk: 997 clk_disable_unprepare(dsi->pllref_clk); 998 out_pm_runtime: 999 pm_runtime_put(dsi->dev); 1000 if (dsi->slave) 1001 pm_runtime_put(dsi->slave->dev); 1002 1003 return ret; 1004 } 1005 1006 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 1007 struct device *master, 1008 void *data) 1009 { 1010 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1011 1012 if (dsi->is_slave) 1013 return; 1014 1015 dsi->dsi_bound = false; 1016 1017 dw_mipi_dsi_unbind(dsi->dmd); 1018 1019 clk_disable_unprepare(dsi->pllref_clk); 1020 1021 pm_runtime_put(dsi->dev); 1022 if (dsi->slave) 1023 pm_runtime_put(dsi->slave->dev); 1024 } 1025 1026 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 1027 .bind = dw_mipi_dsi_rockchip_bind, 1028 .unbind = dw_mipi_dsi_rockchip_unbind, 1029 }; 1030 1031 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 1032 struct mipi_dsi_device *device) 1033 { 1034 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1035 struct device *second; 1036 int ret; 1037 1038 mutex_lock(&dsi->usage_mutex); 1039 1040 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1041 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1042 mutex_unlock(&dsi->usage_mutex); 1043 return -EBUSY; 1044 } 1045 1046 dsi->usage_mode = DW_DSI_USAGE_DSI; 1047 mutex_unlock(&dsi->usage_mutex); 1048 1049 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1050 if (ret) { 1051 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 1052 ret); 1053 goto out; 1054 } 1055 1056 second = dw_mipi_dsi_rockchip_find_second(dsi); 1057 if (IS_ERR(second)) { 1058 ret = PTR_ERR(second); 1059 goto out; 1060 } 1061 if (second) { 1062 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 1063 if (ret) { 1064 DRM_DEV_ERROR(second, 1065 "Failed to register component: %d\n", 1066 ret); 1067 goto out; 1068 } 1069 } 1070 1071 return 0; 1072 1073 out: 1074 mutex_lock(&dsi->usage_mutex); 1075 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1076 mutex_unlock(&dsi->usage_mutex); 1077 return ret; 1078 } 1079 1080 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1081 struct mipi_dsi_device *device) 1082 { 1083 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1084 struct device *second; 1085 1086 second = dw_mipi_dsi_rockchip_find_second(dsi); 1087 if (second && !IS_ERR(second)) 1088 component_del(second, &dw_mipi_dsi_rockchip_ops); 1089 1090 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1091 1092 mutex_lock(&dsi->usage_mutex); 1093 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1094 mutex_unlock(&dsi->usage_mutex); 1095 1096 return 0; 1097 } 1098 1099 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1100 .attach = dw_mipi_dsi_rockchip_host_attach, 1101 .detach = dw_mipi_dsi_rockchip_host_detach, 1102 }; 1103 1104 static int dw_mipi_dsi_rockchip_dphy_bind(struct device *dev, 1105 struct device *master, 1106 void *data) 1107 { 1108 /* 1109 * Nothing to do when used as a dphy. 1110 * Just make the rest of Rockchip-DRM happy 1111 * by being here. 1112 */ 1113 1114 return 0; 1115 } 1116 1117 static void dw_mipi_dsi_rockchip_dphy_unbind(struct device *dev, 1118 struct device *master, 1119 void *data) 1120 { 1121 /* Nothing to do when used as a dphy. */ 1122 } 1123 1124 static const struct component_ops dw_mipi_dsi_rockchip_dphy_ops = { 1125 .bind = dw_mipi_dsi_rockchip_dphy_bind, 1126 .unbind = dw_mipi_dsi_rockchip_dphy_unbind, 1127 }; 1128 1129 static int dw_mipi_dsi_dphy_init(struct phy *phy) 1130 { 1131 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1132 int ret; 1133 1134 mutex_lock(&dsi->usage_mutex); 1135 1136 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { 1137 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); 1138 mutex_unlock(&dsi->usage_mutex); 1139 return -EBUSY; 1140 } 1141 1142 dsi->usage_mode = DW_DSI_USAGE_PHY; 1143 mutex_unlock(&dsi->usage_mutex); 1144 1145 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1146 if (ret < 0) 1147 goto err_graph; 1148 1149 if (dsi->cdata->dphy_rx_init) { 1150 ret = clk_prepare_enable(dsi->pclk); 1151 if (ret < 0) 1152 goto err_init; 1153 1154 ret = clk_prepare_enable(dsi->grf_clk); 1155 if (ret) { 1156 clk_disable_unprepare(dsi->pclk); 1157 goto err_init; 1158 } 1159 1160 ret = dsi->cdata->dphy_rx_init(phy); 1161 clk_disable_unprepare(dsi->grf_clk); 1162 clk_disable_unprepare(dsi->pclk); 1163 if (ret < 0) 1164 goto err_init; 1165 } 1166 1167 return 0; 1168 1169 err_init: 1170 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1171 err_graph: 1172 mutex_lock(&dsi->usage_mutex); 1173 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1174 mutex_unlock(&dsi->usage_mutex); 1175 1176 return ret; 1177 } 1178 1179 static int dw_mipi_dsi_dphy_exit(struct phy *phy) 1180 { 1181 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1182 1183 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); 1184 1185 mutex_lock(&dsi->usage_mutex); 1186 dsi->usage_mode = DW_DSI_USAGE_IDLE; 1187 mutex_unlock(&dsi->usage_mutex); 1188 1189 return 0; 1190 } 1191 1192 static int dw_mipi_dsi_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 1193 { 1194 struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy; 1195 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1196 int ret; 1197 1198 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 1199 if (ret) 1200 return ret; 1201 1202 dsi->dphy_config = *config; 1203 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); 1204 1205 return 0; 1206 } 1207 1208 static int dw_mipi_dsi_dphy_power_on(struct phy *phy) 1209 { 1210 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1211 int i, ret; 1212 1213 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", 1214 dsi->dphy_config.lanes, dsi->lane_mbps); 1215 1216 i = max_mbps_to_parameter(dsi->lane_mbps); 1217 if (i < 0) { 1218 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", 1219 dsi->lane_mbps); 1220 return i; 1221 } 1222 1223 ret = pm_runtime_resume_and_get(dsi->dev); 1224 if (ret < 0) { 1225 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); 1226 return ret; 1227 } 1228 1229 ret = clk_prepare_enable(dsi->pclk); 1230 if (ret) { 1231 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); 1232 goto err_pclk; 1233 } 1234 1235 ret = clk_prepare_enable(dsi->grf_clk); 1236 if (ret) { 1237 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1238 goto err_grf_clk; 1239 } 1240 1241 ret = clk_prepare_enable(dsi->phy_cfg_clk); 1242 if (ret) { 1243 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); 1244 goto err_phy_cfg_clk; 1245 } 1246 1247 /* do soc-variant specific init */ 1248 if (dsi->cdata->dphy_rx_power_on) { 1249 ret = dsi->cdata->dphy_rx_power_on(phy); 1250 if (ret < 0) { 1251 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); 1252 goto err_pwr_on; 1253 } 1254 } 1255 1256 /* 1257 * Configure hsfreqrange according to frequency values 1258 * Set clock lane and hsfreqrange by lane0(test code 0x44) 1259 */ 1260 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); 1261 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 1262 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 1263 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); 1264 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); 1265 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); 1266 1267 /* Normal operation */ 1268 dw_mipi_dsi_phy_write(dsi, 0x0, 0); 1269 1270 clk_disable_unprepare(dsi->phy_cfg_clk); 1271 clk_disable_unprepare(dsi->grf_clk); 1272 1273 return ret; 1274 1275 err_pwr_on: 1276 clk_disable_unprepare(dsi->phy_cfg_clk); 1277 err_phy_cfg_clk: 1278 clk_disable_unprepare(dsi->grf_clk); 1279 err_grf_clk: 1280 clk_disable_unprepare(dsi->pclk); 1281 err_pclk: 1282 pm_runtime_put(dsi->dev); 1283 return ret; 1284 } 1285 1286 static int dw_mipi_dsi_dphy_power_off(struct phy *phy) 1287 { 1288 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1289 int ret; 1290 1291 ret = clk_prepare_enable(dsi->grf_clk); 1292 if (ret) { 1293 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1294 return ret; 1295 } 1296 1297 if (dsi->cdata->dphy_rx_power_off) { 1298 ret = dsi->cdata->dphy_rx_power_off(phy); 1299 if (ret < 0) 1300 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); 1301 } 1302 1303 clk_disable_unprepare(dsi->grf_clk); 1304 clk_disable_unprepare(dsi->pclk); 1305 1306 pm_runtime_put(dsi->dev); 1307 1308 return ret; 1309 } 1310 1311 static const struct phy_ops dw_mipi_dsi_dphy_ops = { 1312 .configure = dw_mipi_dsi_dphy_configure, 1313 .power_on = dw_mipi_dsi_dphy_power_on, 1314 .power_off = dw_mipi_dsi_dphy_power_off, 1315 .init = dw_mipi_dsi_dphy_init, 1316 .exit = dw_mipi_dsi_dphy_exit, 1317 }; 1318 1319 static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev) 1320 { 1321 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 1322 int ret; 1323 1324 /* 1325 * Re-configure DSI state, if we were previously initialized. We need 1326 * to do this before rockchip_drm_drv tries to re-enable() any panels. 1327 */ 1328 if (dsi->dsi_bound) { 1329 ret = clk_prepare_enable(dsi->grf_clk); 1330 if (ret) { 1331 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 1332 return ret; 1333 } 1334 1335 dw_mipi_dsi_rockchip_config(dsi); 1336 if (dsi->slave) 1337 dw_mipi_dsi_rockchip_config(dsi->slave); 1338 1339 clk_disable_unprepare(dsi->grf_clk); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = { 1346 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume) 1347 }; 1348 1349 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1350 { 1351 struct device *dev = &pdev->dev; 1352 struct device_node *np = dev->of_node; 1353 struct dw_mipi_dsi_rockchip *dsi; 1354 struct phy_provider *phy_provider; 1355 struct resource *res; 1356 const struct rockchip_dw_dsi_chip_data *cdata = 1357 of_device_get_match_data(dev); 1358 int ret, i; 1359 1360 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1361 if (!dsi) 1362 return -ENOMEM; 1363 1364 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1365 if (IS_ERR(dsi->base)) { 1366 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1367 return PTR_ERR(dsi->base); 1368 } 1369 1370 i = 0; 1371 while (cdata[i].reg) { 1372 if (cdata[i].reg == res->start) { 1373 dsi->cdata = &cdata[i]; 1374 break; 1375 } 1376 1377 i++; 1378 } 1379 1380 if (!dsi->cdata) { 1381 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1382 return -EINVAL; 1383 } 1384 1385 /* try to get a possible external dphy */ 1386 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1387 if (IS_ERR(dsi->phy)) { 1388 ret = PTR_ERR(dsi->phy); 1389 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1390 return ret; 1391 } 1392 1393 dsi->pclk = devm_clk_get(dev, "pclk"); 1394 if (IS_ERR(dsi->pclk)) { 1395 ret = PTR_ERR(dsi->pclk); 1396 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret); 1397 return ret; 1398 } 1399 1400 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1401 if (IS_ERR(dsi->pllref_clk)) { 1402 if (dsi->phy) { 1403 /* 1404 * if external phy is present, pll will be 1405 * generated there. 1406 */ 1407 dsi->pllref_clk = NULL; 1408 } else { 1409 ret = PTR_ERR(dsi->pllref_clk); 1410 DRM_DEV_ERROR(dev, 1411 "Unable to get pll reference clock: %d\n", 1412 ret); 1413 return ret; 1414 } 1415 } 1416 1417 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1418 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1419 if (IS_ERR(dsi->phy_cfg_clk)) { 1420 ret = PTR_ERR(dsi->phy_cfg_clk); 1421 DRM_DEV_ERROR(dev, 1422 "Unable to get phy_cfg_clk: %d\n", ret); 1423 return ret; 1424 } 1425 } 1426 1427 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1428 dsi->grf_clk = devm_clk_get(dev, "grf"); 1429 if (IS_ERR(dsi->grf_clk)) { 1430 ret = PTR_ERR(dsi->grf_clk); 1431 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1432 return ret; 1433 } 1434 } 1435 1436 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1437 if (IS_ERR(dsi->grf_regmap)) { 1438 DRM_DEV_ERROR(dev, "Unable to get rockchip,grf\n"); 1439 return PTR_ERR(dsi->grf_regmap); 1440 } 1441 1442 dsi->dev = dev; 1443 dsi->pdata.base = dsi->base; 1444 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1445 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1446 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1447 dsi->pdata.priv_data = dsi; 1448 platform_set_drvdata(pdev, dsi); 1449 1450 mutex_init(&dsi->usage_mutex); 1451 1452 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); 1453 if (IS_ERR(dsi->dphy)) { 1454 DRM_DEV_ERROR(&pdev->dev, "failed to create PHY\n"); 1455 return PTR_ERR(dsi->dphy); 1456 } 1457 1458 phy_set_drvdata(dsi->dphy, dsi); 1459 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1460 if (IS_ERR(phy_provider)) 1461 return PTR_ERR(phy_provider); 1462 1463 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1464 if (IS_ERR(dsi->dmd)) { 1465 ret = PTR_ERR(dsi->dmd); 1466 if (ret != -EPROBE_DEFER) 1467 DRM_DEV_ERROR(dev, 1468 "Failed to probe dw_mipi_dsi: %d\n", ret); 1469 return ret; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static void dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1476 { 1477 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1478 1479 dw_mipi_dsi_remove(dsi->dmd); 1480 } 1481 1482 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1483 { 1484 .reg = 0xff450000, 1485 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1486 .lcdsel_big = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 0), 1487 .lcdsel_lit = FIELD_PREP_WM16_CONST(PX30_DSI_LCDC_SEL, 1), 1488 1489 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1490 .lanecfg1 = FIELD_PREP_WM16_CONST((PX30_DSI_TURNDISABLE | 1491 PX30_DSI_FORCERXMODE | 1492 PX30_DSI_FORCETXSTOPMODE), 0), 1493 1494 .max_data_lanes = 4, 1495 }, 1496 { /* sentinel */ } 1497 }; 1498 1499 static const struct rockchip_dw_dsi_chip_data rk3128_chip_data[] = { 1500 { 1501 .reg = 0x10110000, 1502 .lanecfg1_grf_reg = RK3128_GRF_LVDS_CON0, 1503 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3128_DSI_TURNDISABLE | 1504 RK3128_DSI_FORCERXMODE | 1505 RK3128_DSI_FORCETXSTOPMODE), 0), 1506 .max_data_lanes = 4, 1507 }, 1508 { /* sentinel */ } 1509 }; 1510 1511 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1512 { 1513 .reg = 0xff960000, 1514 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1515 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 0), 1516 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI0_LCDC_SEL, 1), 1517 1518 .max_data_lanes = 4, 1519 }, 1520 { 1521 .reg = 0xff964000, 1522 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1523 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 0), 1524 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3288_DSI1_LCDC_SEL, 1), 1525 1526 .max_data_lanes = 4, 1527 }, 1528 { /* sentinel */ } 1529 }; 1530 1531 static int rk3399_dphy_tx1rx1_init(struct phy *phy) 1532 { 1533 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1534 1535 /* 1536 * Set TX1RX1 source to isp1. 1537 * Assume ISP0 is supplied by the RX0 dphy. 1538 */ 1539 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1540 FIELD_PREP_WM16(RK3399_TXRX_SRC_SEL_ISP0, 0)); 1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1542 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1544 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 0)); 1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1546 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1547 1548 return 0; 1549 } 1550 1551 static int rk3399_dphy_tx1rx1_power_on(struct phy *phy) 1552 { 1553 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1554 1555 /* tester reset pulse */ 1556 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); 1557 usleep_range(100, 150); 1558 1559 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1560 FIELD_PREP_WM16(RK3399_TXRX_MASTERSLAVEZ, 0)); 1561 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1562 FIELD_PREP_WM16(RK3399_TXRX_BASEDIR, 1)); 1563 1564 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1565 FIELD_PREP_WM16(RK3399_DSI1_FORCERXMODE, 0)); 1566 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1567 FIELD_PREP_WM16(RK3399_DSI1_FORCETXSTOPMODE, 0)); 1568 1569 /* Disable lane turn around, which is ignored in receive mode */ 1570 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, 1571 FIELD_PREP_WM16(RK3399_TXRX_TURNREQUEST, 0)); 1572 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1573 FIELD_PREP_WM16(RK3399_DSI1_TURNDISABLE, 0xf)); 1574 usleep_range(100, 150); 1575 1576 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 1577 usleep_range(100, 150); 1578 1579 /* Enable dphy lanes */ 1580 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1581 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 1582 GENMASK(dsi->dphy_config.lanes - 1, 0))); 1583 1584 usleep_range(100, 150); 1585 1586 return 0; 1587 } 1588 1589 static int rk3399_dphy_tx1rx1_power_off(struct phy *phy) 1590 { 1591 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); 1592 1593 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, 1594 FIELD_PREP_WM16(RK3399_DSI1_ENABLE, 0)); 1595 1596 return 0; 1597 } 1598 1599 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1600 { 1601 .reg = 0xff960000, 1602 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1603 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 0), 1604 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI0_LCDC_SEL, 1), 1605 1606 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1607 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI0_TURNREQUEST | 1608 RK3399_DSI0_TURNDISABLE | 1609 RK3399_DSI0_FORCETXSTOPMODE | 1610 RK3399_DSI0_FORCERXMODE), 0), 1611 1612 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1613 .max_data_lanes = 4, 1614 }, 1615 { 1616 .reg = 0xff968000, 1617 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1618 .lcdsel_big = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 0), 1619 .lcdsel_lit = FIELD_PREP_WM16_CONST(RK3399_DSI1_LCDC_SEL, 1), 1620 1621 1622 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1623 .lanecfg1 = FIELD_PREP_WM16_CONST((RK3399_DSI1_TURNDISABLE | 1624 RK3399_DSI1_FORCETXSTOPMODE | 1625 RK3399_DSI1_FORCERXMODE | 1626 RK3399_DSI1_ENABLE), 0), 1627 1628 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1629 .lanecfg2 = (FIELD_PREP_WM16_CONST(RK3399_TXRX_MASTERSLAVEZ, 1) | 1630 FIELD_PREP_WM16_CONST(RK3399_TXRX_ENABLECLK, 1) | 1631 FIELD_PREP_WM16_CONST(RK3399_TXRX_BASEDIR, 0)), 1632 1633 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1634 .enable = FIELD_PREP_WM16_CONST(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1635 1636 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1637 .max_data_lanes = 4, 1638 1639 .dphy_rx_init = rk3399_dphy_tx1rx1_init, 1640 .dphy_rx_power_on = rk3399_dphy_tx1rx1_power_on, 1641 .dphy_rx_power_off = rk3399_dphy_tx1rx1_power_off, 1642 }, 1643 { /* sentinel */ } 1644 }; 1645 1646 static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { 1647 { 1648 .reg = 0xfe060000, 1649 .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, 1650 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI0_SKEWCALHS, 0) | 1651 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCETXSTOPMODE, 0) | 1652 FIELD_PREP_WM16_CONST(RK3568_DSI0_TURNDISABLE, 0) | 1653 FIELD_PREP_WM16_CONST(RK3568_DSI0_FORCERXMODE, 0)), 1654 .max_data_lanes = 4, 1655 }, 1656 { 1657 .reg = 0xfe070000, 1658 .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, 1659 .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3568_DSI1_SKEWCALHS, 0) | 1660 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCETXSTOPMODE, 0) | 1661 FIELD_PREP_WM16_CONST(RK3568_DSI1_TURNDISABLE, 0) | 1662 FIELD_PREP_WM16_CONST(RK3568_DSI1_FORCERXMODE, 0)), 1663 .max_data_lanes = 4, 1664 }, 1665 { /* sentinel */ } 1666 }; 1667 1668 static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { 1669 { 1670 .reg = 0xffb30000, 1671 .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON, 1672 .lanecfg1 = (FIELD_PREP_WM16_CONST(RV1126_DSI_TURNDISABLE, 0) | 1673 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCERXMODE, 0) | 1674 FIELD_PREP_WM16_CONST(RV1126_DSI_FORCETXSTOPMODE, 0)), 1675 .max_data_lanes = 4, 1676 }, 1677 { /* sentinel */ } 1678 }; 1679 1680 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1681 { 1682 .compatible = "rockchip,px30-mipi-dsi", 1683 .data = &px30_chip_data, 1684 }, { 1685 .compatible = "rockchip,rk3128-mipi-dsi", 1686 .data = &rk3128_chip_data, 1687 }, { 1688 .compatible = "rockchip,rk3288-mipi-dsi", 1689 .data = &rk3288_chip_data, 1690 }, { 1691 .compatible = "rockchip,rk3399-mipi-dsi", 1692 .data = &rk3399_chip_data, 1693 }, { 1694 .compatible = "rockchip,rk3568-mipi-dsi", 1695 .data = &rk3568_chip_data, 1696 }, { 1697 .compatible = "rockchip,rv1126-mipi-dsi", 1698 .data = &rv1126_chip_data, 1699 }, 1700 { /* sentinel */ } 1701 }; 1702 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1703 1704 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1705 .probe = dw_mipi_dsi_rockchip_probe, 1706 .remove = dw_mipi_dsi_rockchip_remove, 1707 .driver = { 1708 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1709 .pm = &dw_mipi_dsi_rockchip_pm_ops, 1710 .name = "dw-mipi-dsi-rockchip", 1711 /* 1712 * For dual-DSI display, one DSI pokes at the other DSI's 1713 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1714 * safe for asynchronous probe. 1715 */ 1716 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1717 }, 1718 }; 1719