xref: /linux/drivers/gpu/drm/rockchip/cdn-dp-core.h (revision a1c3be890440a1769ed6f822376a3e3ab0d42994)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2016 Chris Zhong <zyw@rock-chips.com>
4  * Copyright (C) 2016 ROCKCHIP, Inc.
5  */
6 
7 #ifndef _CDN_DP_CORE_H
8 #define _CDN_DP_CORE_H
9 
10 #include <drm/drm_dp_helper.h>
11 #include <drm/drm_panel.h>
12 #include <drm/drm_probe_helper.h>
13 
14 #include "rockchip_drm_drv.h"
15 
16 #define MAX_PHY		2
17 
18 enum audio_format {
19 	AFMT_I2S = 0,
20 	AFMT_SPDIF = 1,
21 	AFMT_UNUSED,
22 };
23 
24 struct audio_info {
25 	enum audio_format format;
26 	int sample_rate;
27 	int channels;
28 	int sample_width;
29 };
30 
31 enum vic_pxl_encoding_format {
32 	PXL_RGB = 0x1,
33 	YCBCR_4_4_4 = 0x2,
34 	YCBCR_4_2_2 = 0x4,
35 	YCBCR_4_2_0 = 0x8,
36 	Y_ONLY = 0x10,
37 };
38 
39 struct video_info {
40 	bool h_sync_polarity;
41 	bool v_sync_polarity;
42 	bool interlaced;
43 	int color_depth;
44 	enum vic_pxl_encoding_format color_fmt;
45 };
46 
47 struct cdn_firmware_header {
48 	u32 size_bytes; /* size of the entire header+image(s) in bytes */
49 	u32 header_size; /* size of just the header in bytes */
50 	u32 iram_size; /* size of iram */
51 	u32 dram_size; /* size of dram */
52 };
53 
54 struct cdn_dp_port {
55 	struct cdn_dp_device *dp;
56 	struct notifier_block event_nb;
57 	struct extcon_dev *extcon;
58 	struct phy *phy;
59 	u8 lanes;
60 	bool phy_enabled;
61 	u8 id;
62 };
63 
64 struct cdn_dp_device {
65 	struct device *dev;
66 	struct drm_device *drm_dev;
67 	struct drm_connector connector;
68 	struct drm_encoder encoder;
69 	struct drm_display_mode mode;
70 	struct platform_device *audio_pdev;
71 	struct work_struct event_work;
72 	struct edid *edid;
73 
74 	struct mutex lock;
75 	bool connected;
76 	bool active;
77 	bool suspended;
78 
79 	const struct firmware *fw;	/* cdn dp firmware */
80 	unsigned int fw_version;	/* cdn fw version */
81 	bool fw_loaded;
82 
83 	void __iomem *regs;
84 	struct regmap *grf;
85 	struct clk *core_clk;
86 	struct clk *pclk;
87 	struct clk *spdif_clk;
88 	struct clk *grf_clk;
89 	struct reset_control *spdif_rst;
90 	struct reset_control *dptx_rst;
91 	struct reset_control *apb_rst;
92 	struct reset_control *core_rst;
93 	struct audio_info audio_info;
94 	struct video_info video_info;
95 	struct cdn_dp_port *port[MAX_PHY];
96 	u8 ports;
97 	u8 max_lanes;
98 	unsigned int max_rate;
99 	u8 lanes;
100 	int active_port;
101 
102 	u8 dpcd[DP_RECEIVER_CAP_SIZE];
103 	bool sink_has_audio;
104 };
105 #endif  /* _CDN_DP_CORE_H */
106