1 /* 2 * Rockchip SoC DP (Display Port) interface driver. 3 * 4 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd. 5 * Author: Andy Yan <andy.yan@rock-chips.com> 6 * Yakir Yang <ykk@rock-chips.com> 7 * Jeff Chen <jeff.chen@rock-chips.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/component.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/of_device.h> 18 #include <linux/of_graph.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/clk.h> 22 23 #include <drm/drmP.h> 24 #include <drm/drm_dp_helper.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_probe_helper.h> 28 29 #include <video/of_videomode.h> 30 #include <video/videomode.h> 31 32 #include <drm/bridge/analogix_dp.h> 33 34 #include "rockchip_drm_drv.h" 35 #include "rockchip_drm_psr.h" 36 #include "rockchip_drm_vop.h" 37 38 #define RK3288_GRF_SOC_CON6 0x25c 39 #define RK3288_EDP_LCDC_SEL BIT(5) 40 #define RK3399_GRF_SOC_CON20 0x6250 41 #define RK3399_EDP_LCDC_SEL BIT(5) 42 43 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 44 45 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 46 47 #define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm) 48 49 /** 50 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 51 * @lcdsel_grf_reg: grf register offset of lcdc select 52 * @lcdsel_big: reg value of selecting vop big for eDP 53 * @lcdsel_lit: reg value of selecting vop little for eDP 54 * @chip_type: specific chip type 55 */ 56 struct rockchip_dp_chip_data { 57 u32 lcdsel_grf_reg; 58 u32 lcdsel_big; 59 u32 lcdsel_lit; 60 u32 chip_type; 61 }; 62 63 struct rockchip_dp_device { 64 struct drm_device *drm_dev; 65 struct device *dev; 66 struct drm_encoder encoder; 67 struct drm_display_mode mode; 68 69 struct clk *pclk; 70 struct clk *grfclk; 71 struct regmap *grf; 72 struct reset_control *rst; 73 74 const struct rockchip_dp_chip_data *data; 75 76 struct analogix_dp_device *adp; 77 struct analogix_dp_plat_data plat_data; 78 }; 79 80 static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) 81 { 82 struct rockchip_dp_device *dp = to_dp(encoder); 83 int ret; 84 85 if (!analogix_dp_psr_enabled(dp->adp)) 86 return 0; 87 88 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); 89 90 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, 91 PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 92 if (ret) { 93 DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n"); 94 return -ETIMEDOUT; 95 } 96 97 if (enabled) 98 return analogix_dp_enable_psr(dp->adp); 99 else 100 return analogix_dp_disable_psr(dp->adp); 101 } 102 103 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 104 { 105 reset_control_assert(dp->rst); 106 usleep_range(10, 20); 107 reset_control_deassert(dp->rst); 108 109 return 0; 110 } 111 112 static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data) 113 { 114 struct rockchip_dp_device *dp = to_dp(plat_data); 115 int ret; 116 117 ret = clk_prepare_enable(dp->pclk); 118 if (ret < 0) { 119 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret); 120 return ret; 121 } 122 123 ret = rockchip_dp_pre_init(dp); 124 if (ret < 0) { 125 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret); 126 clk_disable_unprepare(dp->pclk); 127 return ret; 128 } 129 130 return ret; 131 } 132 133 static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data) 134 { 135 struct rockchip_dp_device *dp = to_dp(plat_data); 136 137 return rockchip_drm_psr_inhibit_put(&dp->encoder); 138 } 139 140 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) 141 { 142 struct rockchip_dp_device *dp = to_dp(plat_data); 143 int ret; 144 145 ret = rockchip_drm_psr_inhibit_get(&dp->encoder); 146 if (ret != 0) 147 return ret; 148 149 clk_disable_unprepare(dp->pclk); 150 151 return 0; 152 } 153 154 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data, 155 struct drm_connector *connector) 156 { 157 struct drm_display_info *di = &connector->display_info; 158 /* VOP couldn't output YUV video format for eDP rightly */ 159 u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; 160 161 if ((di->color_formats & mask)) { 162 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n"); 163 di->color_formats &= ~mask; 164 di->color_formats |= DRM_COLOR_FORMAT_RGB444; 165 di->bpc = 8; 166 } 167 168 return 0; 169 } 170 171 static bool 172 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder, 173 const struct drm_display_mode *mode, 174 struct drm_display_mode *adjusted_mode) 175 { 176 /* do nothing */ 177 return true; 178 } 179 180 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, 181 struct drm_display_mode *mode, 182 struct drm_display_mode *adjusted) 183 { 184 /* do nothing */ 185 } 186 187 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) 188 { 189 struct rockchip_dp_device *dp = to_dp(encoder); 190 int ret; 191 u32 val; 192 193 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder); 194 if (ret < 0) 195 return; 196 197 if (ret) 198 val = dp->data->lcdsel_lit; 199 else 200 val = dp->data->lcdsel_big; 201 202 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 203 204 ret = clk_prepare_enable(dp->grfclk); 205 if (ret < 0) { 206 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret); 207 return; 208 } 209 210 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); 211 if (ret != 0) 212 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); 213 214 clk_disable_unprepare(dp->grfclk); 215 } 216 217 static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) 218 { 219 /* do nothing */ 220 } 221 222 static int 223 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, 224 struct drm_crtc_state *crtc_state, 225 struct drm_connector_state *conn_state) 226 { 227 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 228 struct drm_display_info *di = &conn_state->connector->display_info; 229 230 /* 231 * The hardware IC designed that VOP must output the RGB10 video 232 * format to eDP controller, and if eDP panel only support RGB8, 233 * then eDP controller should cut down the video data, not via VOP 234 * controller, that's why we need to hardcode the VOP output mode 235 * to RGA10 here. 236 */ 237 238 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; 239 s->output_type = DRM_MODE_CONNECTOR_eDP; 240 s->output_bpc = di->bpc; 241 242 return 0; 243 } 244 245 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { 246 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, 247 .mode_set = rockchip_dp_drm_encoder_mode_set, 248 .enable = rockchip_dp_drm_encoder_enable, 249 .disable = rockchip_dp_drm_encoder_nop, 250 .atomic_check = rockchip_dp_drm_encoder_atomic_check, 251 }; 252 253 static struct drm_encoder_funcs rockchip_dp_encoder_funcs = { 254 .destroy = drm_encoder_cleanup, 255 }; 256 257 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) 258 { 259 struct device *dev = dp->dev; 260 struct device_node *np = dev->of_node; 261 262 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 263 if (IS_ERR(dp->grf)) { 264 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n"); 265 return PTR_ERR(dp->grf); 266 } 267 268 dp->grfclk = devm_clk_get(dev, "grf"); 269 if (PTR_ERR(dp->grfclk) == -ENOENT) { 270 dp->grfclk = NULL; 271 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { 272 return -EPROBE_DEFER; 273 } else if (IS_ERR(dp->grfclk)) { 274 DRM_DEV_ERROR(dev, "failed to get grf clock\n"); 275 return PTR_ERR(dp->grfclk); 276 } 277 278 dp->pclk = devm_clk_get(dev, "pclk"); 279 if (IS_ERR(dp->pclk)) { 280 DRM_DEV_ERROR(dev, "failed to get pclk property\n"); 281 return PTR_ERR(dp->pclk); 282 } 283 284 dp->rst = devm_reset_control_get(dev, "dp"); 285 if (IS_ERR(dp->rst)) { 286 DRM_DEV_ERROR(dev, "failed to get dp reset control\n"); 287 return PTR_ERR(dp->rst); 288 } 289 290 return 0; 291 } 292 293 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) 294 { 295 struct drm_encoder *encoder = &dp->encoder; 296 struct drm_device *drm_dev = dp->drm_dev; 297 struct device *dev = dp->dev; 298 int ret; 299 300 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 301 dev->of_node); 302 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 303 304 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs, 305 DRM_MODE_ENCODER_TMDS, NULL); 306 if (ret) { 307 DRM_ERROR("failed to initialize encoder with drm\n"); 308 return ret; 309 } 310 311 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs); 312 313 return 0; 314 } 315 316 static int rockchip_dp_bind(struct device *dev, struct device *master, 317 void *data) 318 { 319 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 320 const struct rockchip_dp_chip_data *dp_data; 321 struct drm_device *drm_dev = data; 322 int ret; 323 324 dp_data = of_device_get_match_data(dev); 325 if (!dp_data) 326 return -ENODEV; 327 328 dp->data = dp_data; 329 dp->drm_dev = drm_dev; 330 331 ret = rockchip_dp_drm_create_encoder(dp); 332 if (ret) { 333 DRM_ERROR("failed to create drm encoder\n"); 334 return ret; 335 } 336 337 dp->plat_data.encoder = &dp->encoder; 338 339 dp->plat_data.dev_type = dp->data->chip_type; 340 dp->plat_data.power_on_start = rockchip_dp_poweron_start; 341 dp->plat_data.power_on_end = rockchip_dp_poweron_end; 342 dp->plat_data.power_off = rockchip_dp_powerdown; 343 dp->plat_data.get_modes = rockchip_dp_get_modes; 344 345 ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set); 346 if (ret < 0) 347 goto err_cleanup_encoder; 348 349 dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data); 350 if (IS_ERR(dp->adp)) { 351 ret = PTR_ERR(dp->adp); 352 goto err_unreg_psr; 353 } 354 355 return 0; 356 err_unreg_psr: 357 rockchip_drm_psr_unregister(&dp->encoder); 358 err_cleanup_encoder: 359 dp->encoder.funcs->destroy(&dp->encoder); 360 return ret; 361 } 362 363 static void rockchip_dp_unbind(struct device *dev, struct device *master, 364 void *data) 365 { 366 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 367 368 analogix_dp_unbind(dp->adp); 369 rockchip_drm_psr_unregister(&dp->encoder); 370 dp->encoder.funcs->destroy(&dp->encoder); 371 372 dp->adp = ERR_PTR(-ENODEV); 373 } 374 375 static const struct component_ops rockchip_dp_component_ops = { 376 .bind = rockchip_dp_bind, 377 .unbind = rockchip_dp_unbind, 378 }; 379 380 static int rockchip_dp_probe(struct platform_device *pdev) 381 { 382 struct device *dev = &pdev->dev; 383 struct drm_panel *panel = NULL; 384 struct rockchip_dp_device *dp; 385 int ret; 386 387 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL); 388 if (ret < 0) 389 return ret; 390 391 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); 392 if (!dp) 393 return -ENOMEM; 394 395 dp->dev = dev; 396 dp->adp = ERR_PTR(-ENODEV); 397 dp->plat_data.panel = panel; 398 399 ret = rockchip_dp_of_probe(dp); 400 if (ret < 0) 401 return ret; 402 403 platform_set_drvdata(pdev, dp); 404 405 return component_add(dev, &rockchip_dp_component_ops); 406 } 407 408 static int rockchip_dp_remove(struct platform_device *pdev) 409 { 410 component_del(&pdev->dev, &rockchip_dp_component_ops); 411 412 return 0; 413 } 414 415 #ifdef CONFIG_PM_SLEEP 416 static int rockchip_dp_suspend(struct device *dev) 417 { 418 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 419 420 if (IS_ERR(dp->adp)) 421 return 0; 422 423 return analogix_dp_suspend(dp->adp); 424 } 425 426 static int rockchip_dp_resume(struct device *dev) 427 { 428 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 429 430 if (IS_ERR(dp->adp)) 431 return 0; 432 433 return analogix_dp_resume(dp->adp); 434 } 435 #endif 436 437 static const struct dev_pm_ops rockchip_dp_pm_ops = { 438 #ifdef CONFIG_PM_SLEEP 439 .suspend = rockchip_dp_suspend, 440 .resume_early = rockchip_dp_resume, 441 #endif 442 }; 443 444 static const struct rockchip_dp_chip_data rk3399_edp = { 445 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 446 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL), 447 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL), 448 .chip_type = RK3399_EDP, 449 }; 450 451 static const struct rockchip_dp_chip_data rk3288_dp = { 452 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 453 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL), 454 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL), 455 .chip_type = RK3288_DP, 456 }; 457 458 static const struct of_device_id rockchip_dp_dt_ids[] = { 459 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, 460 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, 461 {} 462 }; 463 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); 464 465 struct platform_driver rockchip_dp_driver = { 466 .probe = rockchip_dp_probe, 467 .remove = rockchip_dp_remove, 468 .driver = { 469 .name = "rockchip-dp", 470 .pm = &rockchip_dp_pm_ops, 471 .of_match_table = of_match_ptr(rockchip_dp_dt_ids), 472 }, 473 }; 474