1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip SoC DP (Display Port) interface driver. 4 * 5 * Copyright (C) Rockchip Electronics Co., Ltd. 6 * Author: Andy Yan <andy.yan@rock-chips.com> 7 * Yakir Yang <ykk@rock-chips.com> 8 * Jeff Chen <jeff.chen@rock-chips.com> 9 */ 10 11 #include <linux/cleanup.h> 12 #include <linux/component.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/of.h> 15 #include <linux/of_graph.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/clk.h> 21 22 #include <video/of_videomode.h> 23 #include <video/videomode.h> 24 25 #include <drm/display/drm_dp_helper.h> 26 #include <drm/drm_atomic.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_bridge_connector.h> 29 #include <drm/bridge/analogix_dp.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_panel.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include "rockchip_drm_drv.h" 36 37 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 38 39 #define GRF_REG_FIELD(_reg, _lsb, _msb) { \ 40 .reg = _reg, \ 41 .lsb = _lsb, \ 42 .msb = _msb, \ 43 .valid = true, \ 44 } 45 46 struct rockchip_grf_reg_field { 47 u32 reg; 48 u32 lsb; 49 u32 msb; 50 bool valid; 51 }; 52 53 /** 54 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 55 * @lcdc_sel: grf register field of lcdc_sel 56 * @edp_mode: grf register field of edp_mode 57 * @chip_type: specific chip type 58 * @reg: register base address 59 */ 60 struct rockchip_dp_chip_data { 61 const struct rockchip_grf_reg_field lcdc_sel; 62 const struct rockchip_grf_reg_field edp_mode; 63 u32 chip_type; 64 u32 reg; 65 }; 66 67 struct rockchip_dp_device { 68 struct drm_device *drm_dev; 69 struct device *dev; 70 struct rockchip_encoder encoder; 71 struct drm_display_mode mode; 72 73 struct clk *pclk; 74 struct clk *grfclk; 75 struct regmap *grf; 76 struct reset_control *rst; 77 struct reset_control *apbrst; 78 79 const struct rockchip_dp_chip_data *data; 80 81 struct analogix_dp_device *adp; 82 struct analogix_dp_plat_data plat_data; 83 }; 84 85 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) 86 { 87 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 88 89 return container_of(rkencoder, struct rockchip_dp_device, encoder); 90 } 91 92 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) 93 { 94 return container_of(plat_data, struct rockchip_dp_device, plat_data); 95 } 96 97 static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 val) 98 { 99 return regmap_write(grf, reg, (mask << 16) | (val & mask)); 100 } 101 102 static int rockchip_grf_field_write(struct regmap *grf, 103 const struct rockchip_grf_reg_field *field, 104 u32 val) 105 { 106 u32 mask; 107 108 if (!field->valid) 109 return 0; 110 111 mask = GENMASK(field->msb, field->lsb); 112 val <<= field->lsb; 113 114 return rockchip_grf_write(grf, field->reg, mask, val); 115 } 116 117 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 118 { 119 reset_control_assert(dp->rst); 120 usleep_range(10, 20); 121 reset_control_deassert(dp->rst); 122 123 reset_control_assert(dp->apbrst); 124 usleep_range(10, 20); 125 reset_control_deassert(dp->apbrst); 126 127 return 0; 128 } 129 130 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data) 131 { 132 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); 133 int ret; 134 135 ret = clk_prepare_enable(dp->pclk); 136 if (ret < 0) { 137 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret); 138 return ret; 139 } 140 141 ret = rockchip_dp_pre_init(dp); 142 if (ret < 0) { 143 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret); 144 clk_disable_unprepare(dp->pclk); 145 return ret; 146 } 147 148 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 1); 149 if (ret != 0) 150 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret); 151 152 return ret; 153 } 154 155 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) 156 { 157 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); 158 int ret; 159 160 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 0); 161 if (ret != 0) 162 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret); 163 164 clk_disable_unprepare(dp->pclk); 165 166 return 0; 167 } 168 169 static bool 170 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder, 171 const struct drm_display_mode *mode, 172 struct drm_display_mode *adjusted_mode) 173 { 174 /* do nothing */ 175 return true; 176 } 177 178 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, 179 struct drm_display_mode *mode, 180 struct drm_display_mode *adjusted) 181 { 182 /* do nothing */ 183 } 184 185 static 186 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, 187 struct drm_atomic_commit *state) 188 { 189 struct drm_connector *connector; 190 struct drm_connector_state *conn_state; 191 192 connector = drm_atomic_get_new_connector_for_encoder(state, encoder); 193 if (!connector) 194 return NULL; 195 196 conn_state = drm_atomic_get_new_connector_state(state, connector); 197 if (!conn_state) 198 return NULL; 199 200 return conn_state->crtc; 201 } 202 203 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, 204 struct drm_atomic_commit *state) 205 { 206 struct rockchip_dp_device *dp = encoder_to_dp(encoder); 207 struct drm_crtc *crtc; 208 struct drm_crtc_state *old_crtc_state; 209 struct of_endpoint endpoint; 210 char name[32]; 211 u32 port_id; 212 int ret; 213 214 crtc = rockchip_dp_drm_get_new_crtc(encoder, state); 215 if (!crtc) 216 return; 217 218 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 219 /* Coming back from self refresh, nothing to do */ 220 if (old_crtc_state && old_crtc_state->self_refresh_active) 221 return; 222 223 ret = clk_prepare_enable(dp->grfclk); 224 if (ret < 0) { 225 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret); 226 return; 227 } 228 229 ret = drm_of_encoder_active_endpoint(dp->dev->of_node, encoder, &endpoint); 230 if (ret < 0) 231 return; 232 233 struct device_node *remote_port_parent __free(device_node) = 234 of_graph_get_remote_port_parent(endpoint.local_node); 235 if (remote_port_parent) { 236 struct device_node *ports __free(device_node) = 237 of_get_child_by_name(remote_port_parent, "ports"); 238 239 if (ports) { 240 struct device_node *remote_port __free(device_node) = 241 of_graph_get_remote_port(endpoint.local_node); 242 243 of_property_read_u32(remote_port, "reg", &port_id); 244 sprintf(name, "%s vp%d", remote_port_parent->full_name, port_id); 245 } else { 246 sprintf(name, "%s %s", 247 remote_port_parent->full_name, endpoint.id ? "vopl" : "vopb"); 248 } 249 250 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 251 } 252 253 ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, endpoint.id); 254 if (ret != 0) 255 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); 256 257 clk_disable_unprepare(dp->grfclk); 258 } 259 260 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, 261 struct drm_atomic_commit *state) 262 { 263 struct rockchip_dp_device *dp = encoder_to_dp(encoder); 264 struct drm_crtc *crtc; 265 struct drm_crtc_state *new_crtc_state = NULL; 266 int ret; 267 268 crtc = rockchip_dp_drm_get_new_crtc(encoder, state); 269 /* No crtc means we're doing a full shutdown */ 270 if (!crtc) 271 return; 272 273 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 274 /* If we're not entering self-refresh, no need to wait for vact */ 275 if (!new_crtc_state || !new_crtc_state->self_refresh_active) 276 return; 277 278 ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 279 if (ret) 280 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n"); 281 } 282 283 static int 284 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, 285 struct drm_crtc_state *crtc_state, 286 struct drm_connector_state *conn_state) 287 { 288 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 289 struct drm_display_info *di = &conn_state->connector->display_info; 290 291 /* 292 * The hardware IC designed that VOP must output the RGB10 video 293 * format to eDP controller, and if eDP panel only support RGB8, 294 * then eDP controller should cut down the video data, not via VOP 295 * controller, that's why we need to hardcode the VOP output mode 296 * to RGA10 here. 297 */ 298 299 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; 300 s->output_type = DRM_MODE_CONNECTOR_eDP; 301 s->output_bpc = di->bpc; 302 303 return 0; 304 } 305 306 static const struct drm_encoder_funcs rockchip_dp_encoder_funcs = { 307 .destroy = drm_encoder_cleanup, 308 }; 309 310 static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { 311 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, 312 .mode_set = rockchip_dp_drm_encoder_mode_set, 313 .atomic_enable = rockchip_dp_drm_encoder_enable, 314 .atomic_disable = rockchip_dp_drm_encoder_disable, 315 .atomic_check = rockchip_dp_drm_encoder_atomic_check, 316 }; 317 318 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) 319 { 320 struct device *dev = dp->dev; 321 struct device_node *np = dev->of_node; 322 struct clk *clk; 323 324 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 325 if (IS_ERR(dp->grf)) 326 return dev_err_probe(dev, PTR_ERR(dp->grf), 327 "failed to get rockchip,grf property\n"); 328 329 dp->grfclk = devm_clk_get_optional(dev, "grf"); 330 if (IS_ERR(dp->grfclk)) 331 return dev_err_probe(dev, PTR_ERR(dp->grfclk), 332 "failed to get grf clock\n"); 333 334 dp->pclk = devm_clk_get(dev, "pclk"); 335 if (IS_ERR(dp->pclk)) 336 return dev_err_probe(dev, PTR_ERR(dp->pclk), 337 "failed to get pclk property\n"); 338 339 clk = devm_clk_get_optional_enabled(dev, "hclk"); 340 if (IS_ERR(clk)) 341 return dev_err_probe(dev, PTR_ERR(clk), 342 "failed to get hclk property\n"); 343 344 dp->rst = devm_reset_control_get(dev, "dp"); 345 if (IS_ERR(dp->rst)) 346 return dev_err_probe(dev, PTR_ERR(dp->rst), 347 "failed to get dp reset control\n"); 348 349 dp->apbrst = devm_reset_control_get_optional(dev, "apb"); 350 if (IS_ERR(dp->apbrst)) 351 return dev_err_probe(dev, PTR_ERR(dp->apbrst), 352 "failed to get apb reset control\n"); 353 354 return 0; 355 } 356 357 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) 358 { 359 struct drm_encoder *encoder = &dp->encoder.encoder; 360 struct drm_device *drm_dev = dp->drm_dev; 361 struct device *dev = dp->dev; 362 int ret; 363 364 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 365 dev->of_node); 366 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 367 368 ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs, 369 DRM_MODE_ENCODER_TMDS, NULL); 370 if (ret) { 371 DRM_ERROR("failed to initialize encoder with drm\n"); 372 return ret; 373 } 374 375 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs); 376 377 return 0; 378 } 379 380 static int rockchip_dp_bind(struct device *dev, struct device *master, 381 void *data) 382 { 383 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 384 struct drm_device *drm_dev = data; 385 struct drm_connector *connector; 386 int ret; 387 388 dp->drm_dev = drm_dev; 389 390 ret = rockchip_dp_drm_create_encoder(dp); 391 if (ret) { 392 DRM_ERROR("failed to create drm encoder\n"); 393 return ret; 394 } 395 396 rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, 397 dev->of_node, 0, 0); 398 399 dp->plat_data.encoder = &dp->encoder.encoder; 400 401 ret = analogix_dp_bind(dp->adp, drm_dev); 402 if (ret) 403 goto err_cleanup_encoder; 404 405 connector = drm_bridge_connector_init(dp->drm_dev, dp->plat_data.encoder); 406 if (IS_ERR(connector)) { 407 ret = PTR_ERR(connector); 408 dev_err(dp->dev, "Failed to initialize bridge_connector\n"); 409 goto err_cleanup_encoder; 410 } 411 412 return 0; 413 err_cleanup_encoder: 414 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); 415 return ret; 416 } 417 418 static void rockchip_dp_unbind(struct device *dev, struct device *master, 419 void *data) 420 { 421 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 422 423 analogix_dp_unbind(dp->adp); 424 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); 425 } 426 427 static const struct component_ops rockchip_dp_component_ops = { 428 .bind = rockchip_dp_bind, 429 .unbind = rockchip_dp_unbind, 430 }; 431 432 static int rockchip_dp_probe(struct platform_device *pdev) 433 { 434 struct device *dev = &pdev->dev; 435 const struct rockchip_dp_chip_data *dp_data; 436 struct rockchip_dp_device *dp; 437 struct resource *res; 438 int i; 439 int ret; 440 441 dp_data = of_device_get_match_data(dev); 442 if (!dp_data) 443 return -ENODEV; 444 445 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); 446 if (!dp) 447 return -ENOMEM; 448 449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 450 if (!res) 451 return -EINVAL; 452 453 i = 0; 454 while (dp_data[i].reg) { 455 if (dp_data[i].reg == res->start) { 456 dp->data = &dp_data[i]; 457 break; 458 } 459 460 i++; 461 } 462 463 if (!dp->data) 464 return dev_err_probe(dev, -EINVAL, "no chip-data for %s node\n", 465 dev->of_node->name); 466 467 dp->dev = dev; 468 dp->adp = ERR_PTR(-ENODEV); 469 dp->plat_data.dev_type = dp->data->chip_type; 470 dp->plat_data.power_on = rockchip_dp_poweron; 471 dp->plat_data.power_off = rockchip_dp_powerdown; 472 dp->plat_data.ops = &rockchip_dp_component_ops; 473 474 ret = rockchip_dp_of_probe(dp); 475 if (ret < 0) 476 return ret; 477 478 platform_set_drvdata(pdev, dp); 479 480 dp->adp = analogix_dp_probe(dev, &dp->plat_data); 481 if (IS_ERR(dp->adp)) 482 return PTR_ERR(dp->adp); 483 484 return analogix_dp_finish_probe(dp->adp); 485 } 486 487 static void rockchip_dp_remove(struct platform_device *pdev) 488 { 489 struct rockchip_dp_device *dp = platform_get_drvdata(pdev); 490 491 /* 492 * Release the probe-time reference from of_drm_find_panel(). If bind 493 * ran, the panel_bridge holds a second reference that devm cleanup 494 * will release when the bridge is destroyed after remove() returns. 495 */ 496 if (dp->plat_data.panel) 497 drm_panel_put(dp->plat_data.panel); 498 499 component_del(&pdev->dev, &rockchip_dp_component_ops); 500 } 501 502 static int rockchip_dp_suspend(struct device *dev) 503 { 504 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 505 506 if (IS_ERR(dp->adp)) 507 return 0; 508 509 return analogix_dp_suspend(dp->adp); 510 } 511 512 static int rockchip_dp_resume(struct device *dev) 513 { 514 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 515 516 if (IS_ERR(dp->adp)) 517 return 0; 518 519 return analogix_dp_resume(dp->adp); 520 } 521 522 static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend, 523 rockchip_dp_resume, NULL); 524 525 static const struct rockchip_dp_chip_data rk3399_edp[] = { 526 { 527 .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5), 528 .chip_type = RK3399_EDP, 529 .reg = 0xff970000, 530 }, 531 { /* sentinel */ } 532 }; 533 534 static const struct rockchip_dp_chip_data rk3288_dp[] = { 535 { 536 .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5), 537 .chip_type = RK3288_DP, 538 .reg = 0xff970000, 539 }, 540 { /* sentinel */ } 541 }; 542 543 static const struct rockchip_dp_chip_data rk3576_edp[] = { 544 { 545 .chip_type = RK3576_EDP, 546 .reg = 0x27dc0000, 547 }, 548 { /* sentinel */ } 549 }; 550 551 static const struct rockchip_dp_chip_data rk3588_edp[] = { 552 { 553 .edp_mode = GRF_REG_FIELD(0x0000, 0, 0), 554 .chip_type = RK3588_EDP, 555 .reg = 0xfdec0000, 556 }, 557 { 558 .edp_mode = GRF_REG_FIELD(0x0004, 0, 0), 559 .chip_type = RK3588_EDP, 560 .reg = 0xfded0000, 561 }, 562 { /* sentinel */ } 563 }; 564 565 static const struct of_device_id rockchip_dp_dt_ids[] = { 566 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, 567 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, 568 {.compatible = "rockchip,rk3576-edp", .data = &rk3576_edp }, 569 {.compatible = "rockchip,rk3588-edp", .data = &rk3588_edp }, 570 {} 571 }; 572 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); 573 574 struct platform_driver rockchip_dp_driver = { 575 .probe = rockchip_dp_probe, 576 .remove = rockchip_dp_remove, 577 .driver = { 578 .name = "rockchip-dp", 579 .pm = pm_ptr(&rockchip_dp_pm_ops), 580 .of_match_table = rockchip_dp_dt_ids, 581 }, 582 }; 583