1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip SoC DP (Display Port) interface driver. 4 * 5 * Copyright (C) Rockchip Electronics Co., Ltd. 6 * Author: Andy Yan <andy.yan@rock-chips.com> 7 * Yakir Yang <ykk@rock-chips.com> 8 * Jeff Chen <jeff.chen@rock-chips.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/clk.h> 20 21 #include <video/of_videomode.h> 22 #include <video/videomode.h> 23 24 #include <drm/display/drm_dp_helper.h> 25 #include <drm/drm_atomic.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge_connector.h> 28 #include <drm/bridge/analogix_dp.h> 29 #include <drm/drm_of.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_simple_kms_helper.h> 33 34 #include "rockchip_drm_drv.h" 35 36 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100 37 38 #define GRF_REG_FIELD(_reg, _lsb, _msb) { \ 39 .reg = _reg, \ 40 .lsb = _lsb, \ 41 .msb = _msb, \ 42 .valid = true, \ 43 } 44 45 struct rockchip_grf_reg_field { 46 u32 reg; 47 u32 lsb; 48 u32 msb; 49 bool valid; 50 }; 51 52 /** 53 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips 54 * @lcdc_sel: grf register field of lcdc_sel 55 * @edp_mode: grf register field of edp_mode 56 * @chip_type: specific chip type 57 * @reg: register base address 58 */ 59 struct rockchip_dp_chip_data { 60 const struct rockchip_grf_reg_field lcdc_sel; 61 const struct rockchip_grf_reg_field edp_mode; 62 u32 chip_type; 63 u32 reg; 64 }; 65 66 struct rockchip_dp_device { 67 struct drm_device *drm_dev; 68 struct device *dev; 69 struct rockchip_encoder encoder; 70 struct drm_display_mode mode; 71 72 struct clk *pclk; 73 struct clk *grfclk; 74 struct regmap *grf; 75 struct reset_control *rst; 76 struct reset_control *apbrst; 77 78 const struct rockchip_dp_chip_data *data; 79 80 struct analogix_dp_device *adp; 81 struct analogix_dp_plat_data plat_data; 82 }; 83 84 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder) 85 { 86 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); 87 88 return container_of(rkencoder, struct rockchip_dp_device, encoder); 89 } 90 91 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data) 92 { 93 return container_of(plat_data, struct rockchip_dp_device, plat_data); 94 } 95 96 static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 val) 97 { 98 return regmap_write(grf, reg, (mask << 16) | (val & mask)); 99 } 100 101 static int rockchip_grf_field_write(struct regmap *grf, 102 const struct rockchip_grf_reg_field *field, 103 u32 val) 104 { 105 u32 mask; 106 107 if (!field->valid) 108 return 0; 109 110 mask = GENMASK(field->msb, field->lsb); 111 val <<= field->lsb; 112 113 return rockchip_grf_write(grf, field->reg, mask, val); 114 } 115 116 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 117 { 118 reset_control_assert(dp->rst); 119 usleep_range(10, 20); 120 reset_control_deassert(dp->rst); 121 122 reset_control_assert(dp->apbrst); 123 usleep_range(10, 20); 124 reset_control_deassert(dp->apbrst); 125 126 return 0; 127 } 128 129 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data) 130 { 131 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); 132 int ret; 133 134 ret = clk_prepare_enable(dp->pclk); 135 if (ret < 0) { 136 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret); 137 return ret; 138 } 139 140 ret = rockchip_dp_pre_init(dp); 141 if (ret < 0) { 142 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret); 143 clk_disable_unprepare(dp->pclk); 144 return ret; 145 } 146 147 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 1); 148 if (ret != 0) 149 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret); 150 151 return ret; 152 } 153 154 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data) 155 { 156 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data); 157 int ret; 158 159 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 0); 160 if (ret != 0) 161 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret); 162 163 clk_disable_unprepare(dp->pclk); 164 165 return 0; 166 } 167 168 static bool 169 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder, 170 const struct drm_display_mode *mode, 171 struct drm_display_mode *adjusted_mode) 172 { 173 /* do nothing */ 174 return true; 175 } 176 177 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder, 178 struct drm_display_mode *mode, 179 struct drm_display_mode *adjusted) 180 { 181 /* do nothing */ 182 } 183 184 static 185 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder, 186 struct drm_atomic_commit *state) 187 { 188 struct drm_connector *connector; 189 struct drm_connector_state *conn_state; 190 191 connector = drm_atomic_get_new_connector_for_encoder(state, encoder); 192 if (!connector) 193 return NULL; 194 195 conn_state = drm_atomic_get_new_connector_state(state, connector); 196 if (!conn_state) 197 return NULL; 198 199 return conn_state->crtc; 200 } 201 202 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder, 203 struct drm_atomic_commit *state) 204 { 205 struct rockchip_dp_device *dp = encoder_to_dp(encoder); 206 struct drm_crtc *crtc; 207 struct drm_crtc_state *old_crtc_state; 208 struct of_endpoint endpoint; 209 struct device_node *remote_port, *remote_port_parent; 210 char name[32]; 211 u32 port_id; 212 int ret; 213 214 crtc = rockchip_dp_drm_get_new_crtc(encoder, state); 215 if (!crtc) 216 return; 217 218 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 219 /* Coming back from self refresh, nothing to do */ 220 if (old_crtc_state && old_crtc_state->self_refresh_active) 221 return; 222 223 ret = clk_prepare_enable(dp->grfclk); 224 if (ret < 0) { 225 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret); 226 return; 227 } 228 229 ret = drm_of_encoder_active_endpoint(dp->dev->of_node, encoder, &endpoint); 230 if (ret < 0) 231 return; 232 233 remote_port_parent = of_graph_get_remote_port_parent(endpoint.local_node); 234 if (remote_port_parent) { 235 if (of_get_child_by_name(remote_port_parent, "ports")) { 236 remote_port = of_graph_get_remote_port(endpoint.local_node); 237 of_property_read_u32(remote_port, "reg", &port_id); 238 of_node_put(remote_port); 239 sprintf(name, "%s vp%d", remote_port_parent->full_name, port_id); 240 } else { 241 sprintf(name, "%s %s", 242 remote_port_parent->full_name, endpoint.id ? "vopl" : "vopb"); 243 } 244 of_node_put(remote_port_parent); 245 246 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); 247 } 248 249 ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, endpoint.id); 250 if (ret != 0) 251 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); 252 253 clk_disable_unprepare(dp->grfclk); 254 } 255 256 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder, 257 struct drm_atomic_commit *state) 258 { 259 struct rockchip_dp_device *dp = encoder_to_dp(encoder); 260 struct drm_crtc *crtc; 261 struct drm_crtc_state *new_crtc_state = NULL; 262 int ret; 263 264 crtc = rockchip_dp_drm_get_new_crtc(encoder, state); 265 /* No crtc means we're doing a full shutdown */ 266 if (!crtc) 267 return; 268 269 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 270 /* If we're not entering self-refresh, no need to wait for vact */ 271 if (!new_crtc_state || !new_crtc_state->self_refresh_active) 272 return; 273 274 ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 275 if (ret) 276 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n"); 277 } 278 279 static int 280 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, 281 struct drm_crtc_state *crtc_state, 282 struct drm_connector_state *conn_state) 283 { 284 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 285 struct drm_display_info *di = &conn_state->connector->display_info; 286 287 /* 288 * The hardware IC designed that VOP must output the RGB10 video 289 * format to eDP controller, and if eDP panel only support RGB8, 290 * then eDP controller should cut down the video data, not via VOP 291 * controller, that's why we need to hardcode the VOP output mode 292 * to RGA10 here. 293 */ 294 295 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; 296 s->output_type = DRM_MODE_CONNECTOR_eDP; 297 s->output_bpc = di->bpc; 298 299 return 0; 300 } 301 302 static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = { 303 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup, 304 .mode_set = rockchip_dp_drm_encoder_mode_set, 305 .atomic_enable = rockchip_dp_drm_encoder_enable, 306 .atomic_disable = rockchip_dp_drm_encoder_disable, 307 .atomic_check = rockchip_dp_drm_encoder_atomic_check, 308 }; 309 310 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp) 311 { 312 struct device *dev = dp->dev; 313 struct device_node *np = dev->of_node; 314 315 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 316 if (IS_ERR(dp->grf)) 317 return dev_err_probe(dev, PTR_ERR(dp->grf), 318 "failed to get rockchip,grf property\n"); 319 320 dp->grfclk = devm_clk_get_optional(dev, "grf"); 321 if (IS_ERR(dp->grfclk)) 322 return dev_err_probe(dev, PTR_ERR(dp->grfclk), 323 "failed to get grf clock\n"); 324 325 dp->pclk = devm_clk_get(dev, "pclk"); 326 if (IS_ERR(dp->pclk)) 327 return dev_err_probe(dev, PTR_ERR(dp->pclk), 328 "failed to get pclk property\n"); 329 330 dp->rst = devm_reset_control_get(dev, "dp"); 331 if (IS_ERR(dp->rst)) 332 return dev_err_probe(dev, PTR_ERR(dp->rst), 333 "failed to get dp reset control\n"); 334 335 dp->apbrst = devm_reset_control_get_optional(dev, "apb"); 336 if (IS_ERR(dp->apbrst)) 337 return dev_err_probe(dev, PTR_ERR(dp->apbrst), 338 "failed to get apb reset control\n"); 339 340 return 0; 341 } 342 343 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp) 344 { 345 struct drm_encoder *encoder = &dp->encoder.encoder; 346 struct drm_device *drm_dev = dp->drm_dev; 347 struct device *dev = dp->dev; 348 int ret; 349 350 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 351 dev->of_node); 352 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 353 354 ret = drm_simple_encoder_init(drm_dev, encoder, 355 DRM_MODE_ENCODER_TMDS); 356 if (ret) { 357 DRM_ERROR("failed to initialize encoder with drm\n"); 358 return ret; 359 } 360 361 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs); 362 363 return 0; 364 } 365 366 static int rockchip_dp_bind(struct device *dev, struct device *master, 367 void *data) 368 { 369 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 370 struct drm_device *drm_dev = data; 371 struct drm_connector *connector; 372 int ret; 373 374 dp->drm_dev = drm_dev; 375 376 ret = rockchip_dp_drm_create_encoder(dp); 377 if (ret) { 378 DRM_ERROR("failed to create drm encoder\n"); 379 return ret; 380 } 381 382 rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, 383 dev->of_node, 0, 0); 384 385 dp->plat_data.encoder = &dp->encoder.encoder; 386 387 ret = analogix_dp_bind(dp->adp, drm_dev); 388 if (ret) 389 goto err_cleanup_encoder; 390 391 connector = drm_bridge_connector_init(dp->drm_dev, dp->plat_data.encoder); 392 if (IS_ERR(connector)) { 393 ret = PTR_ERR(connector); 394 dev_err(dp->dev, "Failed to initialize bridge_connector\n"); 395 goto err_cleanup_encoder; 396 } 397 398 return 0; 399 err_cleanup_encoder: 400 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); 401 return ret; 402 } 403 404 static void rockchip_dp_unbind(struct device *dev, struct device *master, 405 void *data) 406 { 407 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 408 409 analogix_dp_unbind(dp->adp); 410 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder); 411 } 412 413 static const struct component_ops rockchip_dp_component_ops = { 414 .bind = rockchip_dp_bind, 415 .unbind = rockchip_dp_unbind, 416 }; 417 418 static int rockchip_dp_probe(struct platform_device *pdev) 419 { 420 struct device *dev = &pdev->dev; 421 const struct rockchip_dp_chip_data *dp_data; 422 struct rockchip_dp_device *dp; 423 struct resource *res; 424 int i; 425 int ret; 426 427 dp_data = of_device_get_match_data(dev); 428 if (!dp_data) 429 return -ENODEV; 430 431 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); 432 if (!dp) 433 return -ENOMEM; 434 435 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 436 if (!res) 437 return -EINVAL; 438 439 i = 0; 440 while (dp_data[i].reg) { 441 if (dp_data[i].reg == res->start) { 442 dp->data = &dp_data[i]; 443 break; 444 } 445 446 i++; 447 } 448 449 if (!dp->data) 450 return dev_err_probe(dev, -EINVAL, "no chip-data for %s node\n", 451 dev->of_node->name); 452 453 dp->dev = dev; 454 dp->adp = ERR_PTR(-ENODEV); 455 dp->plat_data.dev_type = dp->data->chip_type; 456 dp->plat_data.power_on = rockchip_dp_poweron; 457 dp->plat_data.power_off = rockchip_dp_powerdown; 458 dp->plat_data.ops = &rockchip_dp_component_ops; 459 460 ret = rockchip_dp_of_probe(dp); 461 if (ret < 0) 462 return ret; 463 464 platform_set_drvdata(pdev, dp); 465 466 dp->adp = analogix_dp_probe(dev, &dp->plat_data); 467 if (IS_ERR(dp->adp)) 468 return PTR_ERR(dp->adp); 469 470 return analogix_dp_finish_probe(dp->adp); 471 } 472 473 static void rockchip_dp_remove(struct platform_device *pdev) 474 { 475 component_del(&pdev->dev, &rockchip_dp_component_ops); 476 } 477 478 static int rockchip_dp_suspend(struct device *dev) 479 { 480 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 481 482 if (IS_ERR(dp->adp)) 483 return 0; 484 485 return analogix_dp_suspend(dp->adp); 486 } 487 488 static int rockchip_dp_resume(struct device *dev) 489 { 490 struct rockchip_dp_device *dp = dev_get_drvdata(dev); 491 492 if (IS_ERR(dp->adp)) 493 return 0; 494 495 return analogix_dp_resume(dp->adp); 496 } 497 498 static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend, 499 rockchip_dp_resume, NULL); 500 501 static const struct rockchip_dp_chip_data rk3399_edp[] = { 502 { 503 .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5), 504 .chip_type = RK3399_EDP, 505 .reg = 0xff970000, 506 }, 507 { /* sentinel */ } 508 }; 509 510 static const struct rockchip_dp_chip_data rk3288_dp[] = { 511 { 512 .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5), 513 .chip_type = RK3288_DP, 514 .reg = 0xff970000, 515 }, 516 { /* sentinel */ } 517 }; 518 519 static const struct rockchip_dp_chip_data rk3588_edp[] = { 520 { 521 .edp_mode = GRF_REG_FIELD(0x0000, 0, 0), 522 .chip_type = RK3588_EDP, 523 .reg = 0xfdec0000, 524 }, 525 { 526 .edp_mode = GRF_REG_FIELD(0x0004, 0, 0), 527 .chip_type = RK3588_EDP, 528 .reg = 0xfded0000, 529 }, 530 { /* sentinel */ } 531 }; 532 533 static const struct of_device_id rockchip_dp_dt_ids[] = { 534 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, 535 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, 536 {.compatible = "rockchip,rk3588-edp", .data = &rk3588_edp }, 537 {} 538 }; 539 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); 540 541 struct platform_driver rockchip_dp_driver = { 542 .probe = rockchip_dp_probe, 543 .remove = rockchip_dp_remove, 544 .driver = { 545 .name = "rockchip-dp", 546 .pm = pm_ptr(&rockchip_dp_pm_ops), 547 .of_match_table = rockchip_dp_dt_ids, 548 }, 549 }; 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