1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * RZ/G2L Display Unit Mode Setting 4 * 5 * Copyright (C) 2023 Renesas Electronics Corporation 6 * 7 * Based on rcar_du_kms.c 8 */ 9 10 #include <drm/drm_atomic.h> 11 #include <drm/drm_atomic_helper.h> 12 #include <drm/drm_crtc.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_framebuffer.h> 15 #include <drm/drm_gem_dma_helper.h> 16 #include <drm/drm_gem_framebuffer_helper.h> 17 #include <drm/drm_managed.h> 18 #include <drm/drm_probe_helper.h> 19 #include <drm/drm_vblank.h> 20 21 #include <linux/device.h> 22 #include <linux/of.h> 23 #include <linux/of_graph.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 27 #include "rzg2l_du_crtc.h" 28 #include "rzg2l_du_drv.h" 29 #include "rzg2l_du_encoder.h" 30 #include "rzg2l_du_kms.h" 31 #include "rzg2l_du_vsp.h" 32 33 /* ----------------------------------------------------------------------------- 34 * Format helpers 35 */ 36 37 static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = { 38 { 39 .fourcc = DRM_FORMAT_RGB332, 40 .v4l2 = V4L2_PIX_FMT_RGB332, 41 .planes = 1, 42 .hsub = 1, 43 }, { 44 .fourcc = DRM_FORMAT_ARGB4444, 45 .v4l2 = V4L2_PIX_FMT_ARGB444, 46 .planes = 1, 47 .hsub = 1, 48 }, { 49 .fourcc = DRM_FORMAT_XRGB4444, 50 .v4l2 = V4L2_PIX_FMT_XRGB444, 51 .planes = 1, 52 .hsub = 1, 53 }, { 54 .fourcc = DRM_FORMAT_ARGB1555, 55 .v4l2 = V4L2_PIX_FMT_ARGB555, 56 .planes = 1, 57 .hsub = 1, 58 }, { 59 .fourcc = DRM_FORMAT_XRGB1555, 60 .v4l2 = V4L2_PIX_FMT_XRGB555, 61 .planes = 1, 62 }, { 63 .fourcc = DRM_FORMAT_RGB565, 64 .v4l2 = V4L2_PIX_FMT_RGB565, 65 .planes = 1, 66 .hsub = 1, 67 }, { 68 .fourcc = DRM_FORMAT_BGR888, 69 .v4l2 = V4L2_PIX_FMT_RGB24, 70 .planes = 1, 71 .hsub = 1, 72 }, { 73 .fourcc = DRM_FORMAT_RGB888, 74 .v4l2 = V4L2_PIX_FMT_BGR24, 75 .planes = 1, 76 .hsub = 1, 77 }, { 78 .fourcc = DRM_FORMAT_BGRA8888, 79 .v4l2 = V4L2_PIX_FMT_ARGB32, 80 .planes = 1, 81 .hsub = 1, 82 }, { 83 .fourcc = DRM_FORMAT_BGRX8888, 84 .v4l2 = V4L2_PIX_FMT_XRGB32, 85 .planes = 1, 86 .hsub = 1, 87 }, { 88 .fourcc = DRM_FORMAT_ARGB8888, 89 .v4l2 = V4L2_PIX_FMT_ABGR32, 90 .planes = 1, 91 .hsub = 1, 92 }, { 93 .fourcc = DRM_FORMAT_XRGB8888, 94 .v4l2 = V4L2_PIX_FMT_XBGR32, 95 .planes = 1, 96 .hsub = 1, 97 }, { 98 .fourcc = DRM_FORMAT_UYVY, 99 .v4l2 = V4L2_PIX_FMT_UYVY, 100 .planes = 1, 101 .hsub = 2, 102 }, { 103 .fourcc = DRM_FORMAT_YUYV, 104 .v4l2 = V4L2_PIX_FMT_YUYV, 105 .planes = 1, 106 .hsub = 2, 107 }, { 108 .fourcc = DRM_FORMAT_YVYU, 109 .v4l2 = V4L2_PIX_FMT_YVYU, 110 .planes = 1, 111 .hsub = 2, 112 }, { 113 .fourcc = DRM_FORMAT_NV12, 114 .v4l2 = V4L2_PIX_FMT_NV12M, 115 .planes = 2, 116 .hsub = 2, 117 }, { 118 .fourcc = DRM_FORMAT_NV21, 119 .v4l2 = V4L2_PIX_FMT_NV21M, 120 .planes = 2, 121 .hsub = 2, 122 }, { 123 .fourcc = DRM_FORMAT_NV16, 124 .v4l2 = V4L2_PIX_FMT_NV16M, 125 .planes = 2, 126 .hsub = 2, 127 }, { 128 .fourcc = DRM_FORMAT_NV61, 129 .v4l2 = V4L2_PIX_FMT_NV61M, 130 .planes = 2, 131 .hsub = 2, 132 }, { 133 .fourcc = DRM_FORMAT_YUV420, 134 .v4l2 = V4L2_PIX_FMT_YUV420M, 135 .planes = 3, 136 .hsub = 2, 137 }, { 138 .fourcc = DRM_FORMAT_YVU420, 139 .v4l2 = V4L2_PIX_FMT_YVU420M, 140 .planes = 3, 141 .hsub = 2, 142 }, { 143 .fourcc = DRM_FORMAT_YUV422, 144 .v4l2 = V4L2_PIX_FMT_YUV422M, 145 .planes = 3, 146 .hsub = 2, 147 }, { 148 .fourcc = DRM_FORMAT_YVU422, 149 .v4l2 = V4L2_PIX_FMT_YVU422M, 150 .planes = 3, 151 .hsub = 2, 152 }, { 153 .fourcc = DRM_FORMAT_YUV444, 154 .v4l2 = V4L2_PIX_FMT_YUV444M, 155 .planes = 3, 156 .hsub = 1, 157 }, { 158 .fourcc = DRM_FORMAT_YVU444, 159 .v4l2 = V4L2_PIX_FMT_YVU444M, 160 .planes = 3, 161 .hsub = 1, 162 } 163 }; 164 165 const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc) 166 { 167 unsigned int i; 168 169 for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) { 170 if (rzg2l_du_format_infos[i].fourcc == fourcc) 171 return &rzg2l_du_format_infos[i]; 172 } 173 174 return NULL; 175 } 176 177 /* ----------------------------------------------------------------------------- 178 * Frame buffer 179 */ 180 181 int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev, 182 struct drm_mode_create_dumb *args) 183 { 184 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); 185 unsigned int align = 16 * args->bpp / 8; 186 187 args->pitch = roundup(min_pitch, align); 188 189 return drm_gem_dma_dumb_create_internal(file, dev, args); 190 } 191 192 static struct drm_framebuffer * 193 rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, 194 const struct drm_mode_fb_cmd2 *mode_cmd) 195 { 196 const struct rzg2l_du_format_info *format; 197 unsigned int max_pitch; 198 199 format = rzg2l_du_format_info(mode_cmd->pixel_format); 200 if (!format) { 201 dev_dbg(dev->dev, "unsupported pixel format %p4cc\n", 202 &mode_cmd->pixel_format); 203 return ERR_PTR(-EINVAL); 204 } 205 206 /* 207 * On RZ/G2L the memory interface is handled by the VSP that limits the 208 * pitch to 65535 bytes. 209 */ 210 max_pitch = 65535; 211 if (mode_cmd->pitches[0] > max_pitch) { 212 dev_dbg(dev->dev, "invalid pitch value %u\n", 213 mode_cmd->pitches[0]); 214 return ERR_PTR(-EINVAL); 215 } 216 217 return drm_gem_fb_create(dev, file_priv, mode_cmd); 218 } 219 220 /* ----------------------------------------------------------------------------- 221 * Initialization 222 */ 223 224 static const struct drm_mode_config_helper_funcs rzg2l_du_mode_config_helper = { 225 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 226 }; 227 228 static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs = { 229 .fb_create = rzg2l_du_fb_create, 230 .atomic_check = drm_atomic_helper_check, 231 .atomic_commit = drm_atomic_helper_commit, 232 }; 233 234 static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu, 235 enum rzg2l_du_output output, 236 struct of_endpoint *ep) 237 { 238 struct device_node *entity; 239 int ret; 240 241 /* Locate the connected entity and initialize the encoder. */ 242 entity = of_graph_get_remote_port_parent(ep->local_node); 243 if (!entity) { 244 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n", 245 ep->local_node); 246 return -ENODEV; 247 } 248 249 if (!of_device_is_available(entity)) { 250 dev_dbg(rcdu->dev, 251 "connected entity %pOF is disabled, skipping\n", 252 entity); 253 of_node_put(entity); 254 return -ENODEV; 255 } 256 257 ret = rzg2l_du_encoder_init(rcdu, output, entity); 258 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK) 259 dev_warn(rcdu->dev, 260 "failed to initialize encoder %pOF on output %s (%d), skipping\n", 261 entity, rzg2l_du_output_name(output), ret); 262 263 of_node_put(entity); 264 265 return ret; 266 } 267 268 static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu) 269 { 270 struct device_node *np = rcdu->dev->of_node; 271 struct device_node *ep_node; 272 unsigned int num_encoders = 0; 273 274 /* 275 * Iterate over the endpoints and create one encoder for each output 276 * pipeline. 277 */ 278 for_each_endpoint_of_node(np, ep_node) { 279 enum rzg2l_du_output output; 280 struct of_endpoint ep; 281 unsigned int i; 282 int ret; 283 284 ret = of_graph_parse_endpoint(ep_node, &ep); 285 if (ret < 0) { 286 of_node_put(ep_node); 287 return ret; 288 } 289 290 /* Find the output route corresponding to the port number. */ 291 for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) { 292 if (rcdu->info->routes[i].possible_outputs && 293 rcdu->info->routes[i].port == ep.port) { 294 output = i; 295 break; 296 } 297 } 298 299 if (i == RZG2L_DU_OUTPUT_MAX) { 300 dev_warn(rcdu->dev, 301 "port %u references unexisting output, skipping\n", 302 ep.port); 303 continue; 304 } 305 306 /* Process the output pipeline. */ 307 ret = rzg2l_du_encoders_init_one(rcdu, output, &ep); 308 if (ret < 0) { 309 if (ret == -EPROBE_DEFER) { 310 of_node_put(ep_node); 311 return ret; 312 } 313 314 continue; 315 } 316 317 num_encoders++; 318 } 319 320 return num_encoders; 321 } 322 323 static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu) 324 { 325 const struct device_node *np = rcdu->dev->of_node; 326 const char *vsps_prop_name = "renesas,vsps"; 327 struct of_phandle_args args; 328 struct { 329 struct device_node *np; 330 unsigned int crtcs_mask; 331 } vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, }; 332 unsigned int vsps_count = 0; 333 unsigned int cells; 334 unsigned int i; 335 int ret; 336 337 /* 338 * First parse the DT vsps property to populate the list of VSPs. Each 339 * entry contains a pointer to the VSP DT node and a bitmask of the 340 * connected DU CRTCs. 341 */ 342 ret = of_property_count_u32_elems(np, vsps_prop_name); 343 cells = ret / rcdu->num_crtcs - 1; 344 if (cells != 1) 345 return -EINVAL; 346 347 for (i = 0; i < rcdu->num_crtcs; ++i) { 348 unsigned int j; 349 350 ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name, 351 cells, i, &args); 352 if (ret < 0) 353 goto done; 354 355 /* 356 * Add the VSP to the list or update the corresponding existing 357 * entry if the VSP has already been added. 358 */ 359 for (j = 0; j < vsps_count; ++j) { 360 if (vsps[j].np == args.np) 361 break; 362 } 363 364 if (j < vsps_count) 365 of_node_put(args.np); 366 else 367 vsps[vsps_count++].np = args.np; 368 369 vsps[j].crtcs_mask |= BIT(i); 370 371 /* 372 * Store the VSP pointer and pipe index in the CRTC. If the 373 * second cell of the 'renesas,vsps' specifier isn't present, 374 * default to 0. 375 */ 376 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; 377 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; 378 } 379 380 /* 381 * Then initialize all the VSPs from the node pointers and CRTCs bitmask 382 * computed previously. 383 */ 384 for (i = 0; i < vsps_count; ++i) { 385 struct rzg2l_du_vsp *vsp = &rcdu->vsps[i]; 386 387 vsp->index = i; 388 vsp->dev = rcdu; 389 390 ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask); 391 if (ret) 392 goto done; 393 } 394 395 done: 396 for (i = 0; i < ARRAY_SIZE(vsps); ++i) 397 of_node_put(vsps[i].np); 398 399 return ret; 400 } 401 402 int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu) 403 { 404 struct drm_device *dev = &rcdu->ddev; 405 struct drm_encoder *encoder; 406 unsigned int num_encoders; 407 int ret; 408 409 ret = drmm_mode_config_init(dev); 410 if (ret) 411 return ret; 412 413 dev->mode_config.min_width = 0; 414 dev->mode_config.min_height = 0; 415 dev->mode_config.normalize_zpos = true; 416 dev->mode_config.funcs = &rzg2l_du_mode_config_funcs; 417 dev->mode_config.helper_private = &rzg2l_du_mode_config_helper; 418 419 /* 420 * The RZ DU was designed to support a frame size of 1920x1200 (landscape) 421 * or 1200x1920 (portrait). 422 */ 423 dev->mode_config.max_width = 1920; 424 dev->mode_config.max_height = 1920; 425 426 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask); 427 428 /* 429 * Initialize vertical blanking interrupts handling. Start with vblank 430 * disabled for all CRTCs. 431 */ 432 ret = drm_vblank_init(dev, rcdu->num_crtcs); 433 if (ret < 0) 434 return ret; 435 436 /* Initialize the compositors. */ 437 ret = rzg2l_du_vsps_init(rcdu); 438 if (ret < 0) 439 return ret; 440 441 /* Create the CRTCs. */ 442 ret = rzg2l_du_crtc_create(rcdu); 443 if (ret < 0) 444 return ret; 445 446 /* Initialize the encoders. */ 447 ret = rzg2l_du_encoders_init(rcdu); 448 if (ret < 0) 449 return dev_err_probe(rcdu->dev, ret, 450 "failed to initialize encoders\n"); 451 452 if (ret == 0) { 453 dev_err(rcdu->dev, "error: no encoder could be initialized\n"); 454 return -EINVAL; 455 } 456 457 num_encoders = ret; 458 459 /* 460 * Set the possible CRTCs and possible clones. There's always at least 461 * one way for all encoders to clone each other, set all bits in the 462 * possible clones field. 463 */ 464 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 465 struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder); 466 const struct rzg2l_du_output_routing *route = 467 &rcdu->info->routes[renc->output]; 468 469 encoder->possible_crtcs = route->possible_outputs; 470 encoder->possible_clones = (1 << num_encoders) - 1; 471 } 472 473 drm_mode_config_reset(dev); 474 475 drm_kms_helper_poll_init(dev); 476 477 return 0; 478 } 479