1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * R-Car MIPI DSI Interface Registers Definitions 4 * 5 * Copyright (C) 2020 Renesas Electronics Corporation 6 */ 7 8 #ifndef __RCAR_MIPI_DSI_REGS_H__ 9 #define __RCAR_MIPI_DSI_REGS_H__ 10 11 #define LINKSR 0x010 12 #define LINKSR_LPBUSY (1 << 1) 13 #define LINKSR_HSBUSY (1 << 0) 14 15 #define TXSETR 0x100 16 #define TXSETR_LANECNT_MASK (0x3 << 0) 17 18 /* 19 * DSI Command Transfer Registers 20 */ 21 #define TXCMSETR 0x110 22 #define TXCMSETR_SPDTYP (1 << 8) /* 0:HS 1:LP */ 23 #define TXCMSETR_LPPDACC (1 << 0) 24 #define TXCMCR 0x120 25 #define TXCMCR_BTATYP (1 << 2) 26 #define TXCMCR_BTAREQ (1 << 1) 27 #define TXCMCR_TXREQ (1 << 0) 28 #define TXCMSR 0x130 29 #define TXCMSR_CLSNERR (1 << 18) 30 #define TXCMSR_AXIERR (1 << 16) 31 #define TXCMSR_TXREQEND (1 << 0) 32 #define TXCMSCR 0x134 33 #define TXCMSCR_CLSNERR (1 << 18) 34 #define TXCMSCR_AXIERR (1 << 16) 35 #define TXCMSCR_TXREQEND (1 << 0) 36 #define TXCMIER 0x138 37 #define TXCMIER_CLSNERR (1 << 18) 38 #define TXCMIER_AXIERR (1 << 16) 39 #define TXCMIER_TXREQEND (1 << 0) 40 #define TXCMADDRSET0R 0x140 41 #define TXCMPHDR 0x150 42 #define TXCMPHDR_FMT (1 << 24) /* 0:SP 1:LP */ 43 #define TXCMPHDR_VC(n) (((n) & 0x3) << 22) 44 #define TXCMPHDR_DT(n) (((n) & 0x3f) << 16) 45 #define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8) 46 #define TXCMPHDR_DATA0(n) (((n) & 0xff) << 0) 47 #define TXCMPPD0R 0x160 48 #define TXCMPPD1R 0x164 49 #define TXCMPPD2R 0x168 50 #define TXCMPPD3R 0x16c 51 52 #define RXSETR 0x200 53 #define RXSETR_CRCEN (((n) & 0xf) << 24) 54 #define RXSETR_ECCEN (((n) & 0xf) << 16) 55 #define RXPSETR 0x210 56 #define RXPSETR_LPPDACC (1 << 0) 57 #define RXPSR 0x220 58 #define RXPSR_ECCERR1B (1 << 28) 59 #define RXPSR_UEXTRGERR (1 << 25) 60 #define RXPSR_RESPTOERR (1 << 24) 61 #define RXPSR_OVRERR (1 << 23) 62 #define RXPSR_AXIERR (1 << 22) 63 #define RXPSR_CRCERR (1 << 21) 64 #define RXPSR_WCERR (1 << 20) 65 #define RXPSR_UEXDTERR (1 << 19) 66 #define RXPSR_UEXPKTERR (1 << 18) 67 #define RXPSR_ECCERR (1 << 17) 68 #define RXPSR_MLFERR (1 << 16) 69 #define RXPSR_RCVACK (1 << 14) 70 #define RXPSR_RCVEOT (1 << 10) 71 #define RXPSR_RCVAKE (1 << 9) 72 #define RXPSR_RCVRESP (1 << 8) 73 #define RXPSR_BTAREQEND (1 << 0) 74 #define RXPSCR 0x224 75 #define RXPSCR_ECCERR1B (1 << 28) 76 #define RXPSCR_UEXTRGERR (1 << 25) 77 #define RXPSCR_RESPTOERR (1 << 24) 78 #define RXPSCR_OVRERR (1 << 23) 79 #define RXPSCR_AXIERR (1 << 22) 80 #define RXPSCR_CRCERR (1 << 21) 81 #define RXPSCR_WCERR (1 << 20) 82 #define RXPSCR_UEXDTERR (1 << 19) 83 #define RXPSCR_UEXPKTERR (1 << 18) 84 #define RXPSCR_ECCERR (1 << 17) 85 #define RXPSCR_MLFERR (1 << 16) 86 #define RXPSCR_RCVACK (1 << 14) 87 #define RXPSCR_RCVEOT (1 << 10) 88 #define RXPSCR_RCVAKE (1 << 9) 89 #define RXPSCR_RCVRESP (1 << 8) 90 #define RXPSCR_BTAREQEND (1 << 0) 91 #define RXPIER 0x228 92 #define RXPIER_ECCERR1B (1 << 28) 93 #define RXPIER_UEXTRGERR (1 << 25) 94 #define RXPIER_RESPTOERR (1 << 24) 95 #define RXPIER_OVRERR (1 << 23) 96 #define RXPIER_AXIERR (1 << 22) 97 #define RXPIER_CRCERR (1 << 21) 98 #define RXPIER_WCERR (1 << 20) 99 #define RXPIER_UEXDTERR (1 << 19) 100 #define RXPIER_UEXPKTERR (1 << 18) 101 #define RXPIER_ECCERR (1 << 17) 102 #define RXPIER_MLFERR (1 << 16) 103 #define RXPIER_RCVACK (1 << 14) 104 #define RXPIER_RCVEOT (1 << 10) 105 #define RXPIER_RCVAKE (1 << 9) 106 #define RXPIER_RCVRESP (1 << 8) 107 #define RXPIER_BTAREQEND (1 << 0) 108 #define RXPADDRSET0R 0x230 109 #define RXPSIZESETR 0x238 110 #define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3) 111 #define RXPHDR 0x240 112 #define RXPHDR_FMT (1 << 24) /* 0:SP 1:LP */ 113 #define RXPHDR_VC(n) (((n) & 0x3) << 22) 114 #define RXPHDR_DT(n) (((n) & 0x3f) << 16) 115 #define RXPHDR_DATA1(n) (((n) & 0xff) << 8) 116 #define RXPHDR_DATA0(n) (((n) & 0xff) << 0) 117 #define RXPPD0R 0x250 118 #define RXPPD1R 0x254 119 #define RXPPD2R 0x258 120 #define RXPPD3R 0x25c 121 #define AKEPR 0x300 122 #define AKEPR_VC(n) (((n) & 0x3) << 22) 123 #define AKEPR_DT(n) (((n) & 0x3f) << 16) 124 #define AKEPR_ERRRPT(n) (((n) & 0xffff) << 0) 125 #define RXRESPTOSETR 0x400 126 #define TACR 0x500 127 #define TASR 0x510 128 #define TASCR 0x514 129 #define TAIER 0x518 130 #define TOSR 0x610 131 #define TOSR_TATO (1 << 2) 132 #define TOSR_LRXHTO (1 << 1) 133 #define TOSR_HRXTO (1 << 0) 134 #define TOSCR 0x614 135 #define TOSCR_TATO (1 << 2) 136 #define TOSCR_LRXHTO (1 << 1) 137 #define TOSCR_HRXTO (1 << 0) 138 139 /* 140 * Video Mode Register 141 */ 142 #define TXVMSETR 0x180 143 #define TXVMSETR_SYNSEQ_PULSES (0 << 16) 144 #define TXVMSETR_SYNSEQ_EVENTS (1 << 16) 145 #define TXVMSETR_VSTPM (1 << 15) 146 #define TXVMSETR_PIXWDTH (1 << 8) 147 #define TXVMSETR_VSEN_EN (1 << 4) 148 #define TXVMSETR_VSEN_DIS (0 << 4) 149 #define TXVMSETR_HFPBPEN_EN (1 << 2) 150 #define TXVMSETR_HFPBPEN_DIS (0 << 2) 151 #define TXVMSETR_HBPBPEN_EN (1 << 1) 152 #define TXVMSETR_HBPBPEN_DIS (0 << 1) 153 #define TXVMSETR_HSABPEN_EN (1 << 0) 154 #define TXVMSETR_HSABPEN_DIS (0 << 0) 155 156 #define TXVMCR 0x190 157 #define TXVMCR_VFCLR (1 << 12) 158 #define TXVMCR_EN_VIDEO (1 << 0) 159 160 #define TXVMSR 0x1a0 161 #define TXVMSR_STR (1 << 16) 162 #define TXVMSR_VFRDY (1 << 12) 163 #define TXVMSR_ACT (1 << 8) 164 #define TXVMSR_RDY (1 << 0) 165 166 #define TXVMSCR 0x1a4 167 #define TXVMSCR_STR (1 << 16) 168 169 #define TXVMPSPHSETR 0x1c0 170 #define TXVMPSPHSETR_DT_RGB16 (0x0e << 16) 171 #define TXVMPSPHSETR_DT_RGB18 (0x1e << 16) 172 #define TXVMPSPHSETR_DT_RGB18_LS (0x2e << 16) 173 #define TXVMPSPHSETR_DT_RGB24 (0x3e << 16) 174 #define TXVMPSPHSETR_DT_YCBCR16 (0x2c << 16) 175 176 #define TXVMVPRMSET0R 0x1d0 177 #define TXVMVPRMSET0R_HSPOL_HIG (0 << 17) 178 #define TXVMVPRMSET0R_HSPOL_LOW (1 << 17) 179 #define TXVMVPRMSET0R_VSPOL_HIG (0 << 16) 180 #define TXVMVPRMSET0R_VSPOL_LOW (1 << 16) 181 #define TXVMVPRMSET0R_CSPC_RGB (0 << 4) 182 #define TXVMVPRMSET0R_CSPC_YCbCr (1 << 4) 183 #define TXVMVPRMSET0R_BPP_16 (0 << 0) 184 #define TXVMVPRMSET0R_BPP_18 (1 << 0) 185 #define TXVMVPRMSET0R_BPP_24 (2 << 0) 186 187 #define TXVMVPRMSET1R 0x1d4 188 #define TXVMVPRMSET1R_VACTIVE(x) (((x) & 0x7fff) << 16) 189 #define TXVMVPRMSET1R_VSA(x) (((x) & 0xfff) << 0) 190 191 #define TXVMVPRMSET2R 0x1d8 192 #define TXVMVPRMSET2R_VFP(x) (((x) & 0x1fff) << 16) 193 #define TXVMVPRMSET2R_VBP(x) (((x) & 0x1fff) << 0) 194 195 #define TXVMVPRMSET3R 0x1dc 196 #define TXVMVPRMSET3R_HACTIVE(x) (((x) & 0x7fff) << 16) 197 #define TXVMVPRMSET3R_HSA(x) (((x) & 0xfff) << 0) 198 199 #define TXVMVPRMSET4R 0x1e0 200 #define TXVMVPRMSET4R_HFP(x) (((x) & 0x1fff) << 16) 201 #define TXVMVPRMSET4R_HBP(x) (((x) & 0x1fff) << 0) 202 203 /* 204 * PHY-Protocol Interface (PPI) Registers 205 */ 206 #define PPISETR 0x700 207 #define PPISETR_DLEN_MASK (0xf << 0) 208 #define PPISETR_CLEN (1 << 8) 209 210 #define PPICLCR 0x710 211 #define PPICLCR_TXREQHS (1 << 8) 212 #define PPICLCR_TXULPSEXT (1 << 1) 213 #define PPICLCR_TXULPSCLK (1 << 0) 214 215 #define PPICLSR 0x720 216 #define PPICLSR_HSTOLP (1 << 27) 217 #define PPICLSR_TOHS (1 << 26) 218 #define PPICLSR_STPST (1 << 0) 219 220 #define PPICLSCR 0x724 221 #define PPICLSCR_HSTOLP (1 << 27) 222 #define PPICLSCR_TOHS (1 << 26) 223 224 #define PPIDL0SR 0x740 225 #define PPIDL0SR_DIR (1 << 10) 226 #define PPIDL0SR_STPST (1 << 6) 227 228 #define PPIDLSR 0x760 229 #define PPIDLSR_STPST (0xf << 0) 230 231 /* 232 * Clocks registers 233 */ 234 #define LPCLKSET 0x1000 235 #define LPCLKSET_CKEN (1 << 8) 236 #define LPCLKSET_LPCLKDIV(x) (((x) & 0x3f) << 0) 237 238 #define CFGCLKSET 0x1004 239 #define CFGCLKSET_CKEN (1 << 8) 240 #define CFGCLKSET_CFGCLKDIV(x) (((x) & 0x3f) << 0) 241 242 #define DOTCLKDIV 0x1008 243 #define DOTCLKDIV_CKEN (1 << 8) 244 #define DOTCLKDIV_DOTCLKDIV(x) (((x) & 0x3f) << 0) 245 246 #define VCLKSET 0x100c 247 #define VCLKSET_CKEN (1 << 16) 248 #define VCLKSET_COLOR_RGB (0 << 8) 249 #define VCLKSET_COLOR_YCC (1 << 8) 250 #define VCLKSET_DIV_V3U(x) (((x) & 0x3) << 4) 251 #define VCLKSET_DIV_V4H(x) (((x) & 0x7) << 4) 252 #define VCLKSET_BPP_16 (0 << 2) 253 #define VCLKSET_BPP_18 (1 << 2) 254 #define VCLKSET_BPP_18L (2 << 2) 255 #define VCLKSET_BPP_24 (3 << 2) 256 #define VCLKSET_LANE(x) (((x) & 0x3) << 0) 257 258 #define VCLKEN 0x1010 259 #define VCLKEN_CKEN (1 << 0) 260 261 #define PHYSETUP 0x1014 262 #define PHYSETUP_HSFREQRANGE(x) (((x) & 0x7f) << 16) 263 #define PHYSETUP_HSFREQRANGE_MASK (0x7f << 16) 264 #define PHYSETUP_CFGCLKFREQRANGE(x) (((x) & 0x3f) << 8) 265 #define PHYSETUP_SHUTDOWNZ (1 << 1) 266 #define PHYSETUP_RSTZ (1 << 0) 267 268 #define CLOCKSET1 0x101c 269 #define CLOCKSET1_LOCK_PHY (1 << 17) 270 #define CLOCKSET1_CLKSEL (1 << 8) 271 #define CLOCKSET1_CLKINSEL_EXTAL (0 << 2) 272 #define CLOCKSET1_CLKINSEL_DIG (1 << 2) 273 #define CLOCKSET1_CLKINSEL_DU (1 << 3) 274 #define CLOCKSET1_SHADOW_CLEAR (1 << 1) 275 #define CLOCKSET1_UPDATEPLL (1 << 0) 276 277 #define CLOCKSET2 0x1020 278 #define CLOCKSET2_M(x) (((x) & 0xfff) << 16) 279 #define CLOCKSET2_VCO_CNTRL(x) (((x) & 0x3f) << 8) 280 #define CLOCKSET2_N(x) (((x) & 0xf) << 0) 281 282 #define CLOCKSET3 0x1024 283 #define CLOCKSET3_PROP_CNTRL(x) (((x) & 0x3f) << 24) 284 #define CLOCKSET3_INT_CNTRL(x) (((x) & 0x3f) << 16) 285 #define CLOCKSET3_CPBIAS_CNTRL(x) (((x) & 0x7f) << 8) 286 #define CLOCKSET3_GMP_CNTRL(x) (((x) & 0x3) << 0) 287 288 #define PHTW 0x1034 289 #define PHTW_DWEN (1 << 24) 290 #define PHTW_TESTDIN_DATA(x) (((x) & 0xff) << 16) 291 #define PHTW_CWEN (1 << 8) 292 #define PHTW_TESTDIN_CODE(x) (((x) & 0xff) << 0) 293 294 #define PHTR 0x1038 295 #define PHTR_TEST (1 << 16) 296 297 #define PHTC 0x103c 298 #define PHTC_TESTCLR (1 << 0) 299 300 #endif /* __RCAR_MIPI_DSI_REGS_H__ */ 301