1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car MIPI DSI Encoder 4 * 5 * Copyright (C) 2020 Renesas Electronics Corporation 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/math64.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_graph.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_probe_helper.h> 27 28 #include "rcar_mipi_dsi.h" 29 #include "rcar_mipi_dsi_regs.h" 30 31 #define MHZ(v) ((u32)((v) * 1000000U)) 32 33 enum rcar_mipi_dsi_hw_model { 34 RCAR_DSI_V3U, 35 RCAR_DSI_V4H, 36 }; 37 38 struct rcar_mipi_dsi_device_info { 39 enum rcar_mipi_dsi_hw_model model; 40 41 const struct dsi_clk_config *clk_cfg; 42 43 u8 clockset2_m_offset; 44 45 u8 n_min; 46 u8 n_max; 47 u8 n_mul; 48 unsigned long fpfd_min; 49 unsigned long fpfd_max; 50 u16 m_min; 51 u16 m_max; 52 unsigned long fout_min; 53 unsigned long fout_max; 54 }; 55 56 struct rcar_mipi_dsi { 57 struct device *dev; 58 const struct rcar_mipi_dsi_device_info *info; 59 struct reset_control *rstc; 60 61 struct mipi_dsi_host host; 62 struct drm_bridge bridge; 63 struct drm_bridge *next_bridge; 64 struct drm_connector connector; 65 66 void __iomem *mmio; 67 struct { 68 struct clk *mod; 69 struct clk *pll; 70 struct clk *dsi; 71 } clocks; 72 73 enum mipi_dsi_pixel_format format; 74 unsigned int num_data_lanes; 75 unsigned int lanes; 76 }; 77 78 struct dsi_setup_info { 79 unsigned long hsfreq; 80 u16 hsfreqrange; 81 82 unsigned long fout; 83 u16 m; 84 u16 n; 85 u16 vclk_divider; 86 const struct dsi_clk_config *clkset; 87 }; 88 89 static inline struct rcar_mipi_dsi * 90 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge) 91 { 92 return container_of(bridge, struct rcar_mipi_dsi, bridge); 93 } 94 95 static inline struct rcar_mipi_dsi * 96 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host) 97 { 98 return container_of(host, struct rcar_mipi_dsi, host); 99 } 100 101 static const u32 hsfreqrange_table[][2] = { 102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 }, 103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 }, 104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 }, 105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 }, 106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 }, 107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 }, 108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 }, 109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 }, 110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 }, 111 { MHZ(750), 0x39 }, { MHZ(800), 0x09 }, { MHZ(850), 0x19 }, 112 { MHZ(900), 0x29 }, { MHZ(950), 0x3a }, { MHZ(1000), 0x0a }, 113 { MHZ(1050), 0x1a }, { MHZ(1100), 0x2a }, { MHZ(1150), 0x3b }, 114 { MHZ(1200), 0x0b }, { MHZ(1250), 0x1b }, { MHZ(1300), 0x2b }, 115 { MHZ(1350), 0x3c }, { MHZ(1400), 0x0c }, { MHZ(1450), 0x1c }, 116 { MHZ(1500), 0x2c }, { MHZ(1550), 0x3d }, { MHZ(1600), 0x0d }, 117 { MHZ(1650), 0x1d }, { MHZ(1700), 0x2e }, { MHZ(1750), 0x3e }, 118 { MHZ(1800), 0x0e }, { MHZ(1850), 0x1e }, { MHZ(1900), 0x2f }, 119 { MHZ(1950), 0x3f }, { MHZ(2000), 0x0f }, { MHZ(2050), 0x40 }, 120 { MHZ(2100), 0x41 }, { MHZ(2150), 0x42 }, { MHZ(2200), 0x43 }, 121 { MHZ(2250), 0x44 }, { MHZ(2300), 0x45 }, { MHZ(2350), 0x46 }, 122 { MHZ(2400), 0x47 }, { MHZ(2450), 0x48 }, { MHZ(2500), 0x49 }, 123 { /* sentinel */ }, 124 }; 125 126 struct dsi_clk_config { 127 u32 min_freq; 128 u32 max_freq; 129 u8 vco_cntrl; 130 u8 cpbias_cntrl; 131 u8 gmp_cntrl; 132 u8 int_cntrl; 133 u8 prop_cntrl; 134 }; 135 136 static const struct dsi_clk_config dsi_clk_cfg_v3u[] = { 137 { MHZ(40), MHZ(55), 0x3f, 0x10, 0x01, 0x00, 0x0b }, 138 { MHZ(52.5), MHZ(80), 0x39, 0x10, 0x01, 0x00, 0x0b }, 139 { MHZ(80), MHZ(110), 0x2f, 0x10, 0x01, 0x00, 0x0b }, 140 { MHZ(105), MHZ(160), 0x29, 0x10, 0x01, 0x00, 0x0b }, 141 { MHZ(160), MHZ(220), 0x1f, 0x10, 0x01, 0x00, 0x0b }, 142 { MHZ(210), MHZ(320), 0x19, 0x10, 0x01, 0x00, 0x0b }, 143 { MHZ(320), MHZ(440), 0x0f, 0x10, 0x01, 0x00, 0x0b }, 144 { MHZ(420), MHZ(660), 0x09, 0x10, 0x01, 0x00, 0x0b }, 145 { MHZ(630), MHZ(1149), 0x03, 0x10, 0x01, 0x00, 0x0b }, 146 { MHZ(1100), MHZ(1152), 0x01, 0x10, 0x01, 0x00, 0x0b }, 147 { MHZ(1150), MHZ(1250), 0x01, 0x10, 0x01, 0x00, 0x0c }, 148 { /* sentinel */ }, 149 }; 150 151 static const struct dsi_clk_config dsi_clk_cfg_v4h[] = { 152 { MHZ(40), MHZ(45.31), 0x2b, 0x00, 0x00, 0x08, 0x0a }, 153 { MHZ(45.31), MHZ(54.66), 0x28, 0x00, 0x00, 0x08, 0x0a }, 154 { MHZ(54.66), MHZ(62.5), 0x28, 0x00, 0x00, 0x08, 0x0a }, 155 { MHZ(62.5), MHZ(75), 0x27, 0x00, 0x00, 0x08, 0x0a }, 156 { MHZ(75), MHZ(90.63), 0x23, 0x00, 0x00, 0x08, 0x0a }, 157 { MHZ(90.63), MHZ(109.37), 0x20, 0x00, 0x00, 0x08, 0x0a }, 158 { MHZ(109.37), MHZ(125), 0x20, 0x00, 0x00, 0x08, 0x0a }, 159 { MHZ(125), MHZ(150), 0x1f, 0x00, 0x00, 0x08, 0x0a }, 160 { MHZ(150), MHZ(181.25), 0x1b, 0x00, 0x00, 0x08, 0x0a }, 161 { MHZ(181.25), MHZ(218.75), 0x18, 0x00, 0x00, 0x08, 0x0a }, 162 { MHZ(218.75), MHZ(250), 0x18, 0x00, 0x00, 0x08, 0x0a }, 163 { MHZ(250), MHZ(300), 0x17, 0x00, 0x00, 0x08, 0x0a }, 164 { MHZ(300), MHZ(362.5), 0x13, 0x00, 0x00, 0x08, 0x0a }, 165 { MHZ(362.5), MHZ(455.48), 0x10, 0x00, 0x00, 0x08, 0x0a }, 166 { MHZ(455.48), MHZ(500), 0x10, 0x00, 0x00, 0x08, 0x0a }, 167 { MHZ(500), MHZ(600), 0x0f, 0x00, 0x00, 0x08, 0x0a }, 168 { MHZ(600), MHZ(725), 0x0b, 0x00, 0x00, 0x08, 0x0a }, 169 { MHZ(725), MHZ(875), 0x08, 0x00, 0x00, 0x08, 0x0a }, 170 { MHZ(875), MHZ(1000), 0x08, 0x00, 0x00, 0x08, 0x0a }, 171 { MHZ(1000), MHZ(1200), 0x07, 0x00, 0x00, 0x08, 0x0a }, 172 { MHZ(1200), MHZ(1250), 0x03, 0x00, 0x00, 0x08, 0x0a }, 173 { /* sentinel */ }, 174 }; 175 176 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data) 177 { 178 iowrite32(data, dsi->mmio + reg); 179 } 180 181 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg) 182 { 183 return ioread32(dsi->mmio + reg); 184 } 185 186 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr) 187 { 188 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr); 189 } 190 191 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set) 192 { 193 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set); 194 } 195 196 static int rcar_mipi_dsi_write_phtw(struct rcar_mipi_dsi *dsi, u32 phtw) 197 { 198 u32 status; 199 int ret; 200 201 rcar_mipi_dsi_write(dsi, PHTW, phtw); 202 203 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 204 !(status & (PHTW_DWEN | PHTW_CWEN)), 205 2000, 10000, false, dsi, PHTW); 206 if (ret < 0) { 207 dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n", 208 phtw); 209 return ret; 210 } 211 212 return ret; 213 } 214 215 static int rcar_mipi_dsi_write_phtw_arr(struct rcar_mipi_dsi *dsi, 216 const u32 *phtw, unsigned int size) 217 { 218 for (unsigned int i = 0; i < size; i++) { 219 int ret = rcar_mipi_dsi_write_phtw(dsi, phtw[i]); 220 221 if (ret < 0) 222 return ret; 223 } 224 225 return 0; 226 } 227 228 #define WRITE_PHTW(...) \ 229 ({ \ 230 static const u32 phtw[] = { __VA_ARGS__ }; \ 231 int ret; \ 232 ret = rcar_mipi_dsi_write_phtw_arr(dsi, phtw, \ 233 ARRAY_SIZE(phtw)); \ 234 ret; \ 235 }) 236 237 static int rcar_mipi_dsi_init_phtw_v3u(struct rcar_mipi_dsi *dsi) 238 { 239 return WRITE_PHTW(0x01020114, 0x01600115, 0x01030116, 0x0102011d, 240 0x011101a4, 0x018601a4, 0x014201a0, 0x010001a3, 241 0x0101011f); 242 } 243 244 static int rcar_mipi_dsi_post_init_phtw_v3u(struct rcar_mipi_dsi *dsi) 245 { 246 return WRITE_PHTW(0x010c0130, 0x010c0140, 0x010c0150, 0x010c0180, 247 0x010c0190, 0x010a0160, 0x010a0170, 0x01800164, 248 0x01800174); 249 } 250 251 static int rcar_mipi_dsi_init_phtw_v4h(struct rcar_mipi_dsi *dsi, 252 const struct dsi_setup_info *setup_info) 253 { 254 int ret; 255 256 if (setup_info->hsfreq < MHZ(450)) { 257 ret = WRITE_PHTW(0x01010100, 0x011b01ac); 258 if (ret) 259 return ret; 260 } 261 262 ret = WRITE_PHTW(0x01010100, 0x01030173, 0x01000174, 0x01500175, 263 0x01030176, 0x01040166, 0x010201ad); 264 if (ret) 265 return ret; 266 267 if (setup_info->hsfreq <= MHZ(1000)) 268 ret = WRITE_PHTW(0x01020100, 0x01910170, 0x01020171, 269 0x01110172); 270 else if (setup_info->hsfreq <= MHZ(1500)) 271 ret = WRITE_PHTW(0x01020100, 0x01980170, 0x01030171, 272 0x01100172); 273 else if (setup_info->hsfreq <= MHZ(2500)) 274 ret = WRITE_PHTW(0x01020100, 0x0144016b, 0x01000172); 275 else 276 return -EINVAL; 277 278 if (ret) 279 return ret; 280 281 if (dsi->lanes <= 1) { 282 ret = WRITE_PHTW(0x01070100, 0x010e010b); 283 if (ret) 284 return ret; 285 } 286 287 if (dsi->lanes <= 2) { 288 ret = WRITE_PHTW(0x01090100, 0x010e010b); 289 if (ret) 290 return ret; 291 } 292 293 if (dsi->lanes <= 3) { 294 ret = WRITE_PHTW(0x010b0100, 0x010e010b); 295 if (ret) 296 return ret; 297 } 298 299 if (setup_info->hsfreq <= MHZ(1500)) { 300 ret = WRITE_PHTW(0x01010100, 0x01c0016e); 301 if (ret) 302 return ret; 303 } 304 305 return 0; 306 } 307 308 static int 309 rcar_mipi_dsi_post_init_phtw_v4h(struct rcar_mipi_dsi *dsi, 310 const struct dsi_setup_info *setup_info) 311 { 312 u32 status; 313 int ret; 314 315 if (setup_info->hsfreq <= MHZ(1500)) { 316 WRITE_PHTW(0x01020100, 0x00000180); 317 318 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 319 status & PHTR_TEST, 2000, 10000, false, 320 dsi, PHTR); 321 if (ret < 0) { 322 dev_err(dsi->dev, "failed to test PHTR\n"); 323 return ret; 324 } 325 326 WRITE_PHTW(0x01010100, 0x0100016e); 327 } 328 329 return 0; 330 } 331 332 /* ----------------------------------------------------------------------------- 333 * Hardware Setup 334 */ 335 336 static void rcar_mipi_dsi_pll_calc(struct rcar_mipi_dsi *dsi, 337 unsigned long fin_rate, 338 unsigned long fout_target, 339 struct dsi_setup_info *setup_info) 340 { 341 unsigned int best_err = -1; 342 const struct rcar_mipi_dsi_device_info *info = dsi->info; 343 344 for (unsigned int n = info->n_min; n <= info->n_max; n++) { 345 unsigned long fpfd; 346 347 fpfd = fin_rate / n; 348 349 if (fpfd < info->fpfd_min || fpfd > info->fpfd_max) 350 continue; 351 352 for (unsigned int m = info->m_min; m <= info->m_max; m++) { 353 unsigned int err; 354 u64 fout; 355 356 fout = div64_u64((u64)fpfd * m, dsi->info->n_mul); 357 358 if (fout < info->fout_min || fout > info->fout_max) 359 continue; 360 361 fout = div64_u64(fout, setup_info->vclk_divider); 362 363 if (fout < setup_info->clkset->min_freq || 364 fout > setup_info->clkset->max_freq) 365 continue; 366 367 err = abs((long)(fout - fout_target) * 10000 / 368 (long)fout_target); 369 if (err < best_err) { 370 setup_info->m = m; 371 setup_info->n = n; 372 setup_info->fout = (unsigned long)fout; 373 best_err = err; 374 375 if (err == 0) 376 return; 377 } 378 } 379 } 380 } 381 382 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi, 383 struct clk *clk, unsigned long target, 384 struct dsi_setup_info *setup_info) 385 { 386 387 const struct dsi_clk_config *clk_cfg; 388 unsigned long fout_target; 389 unsigned long fin_rate; 390 unsigned int i; 391 unsigned int err; 392 393 /* 394 * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count) 395 * The range out Fout is [40 - 1250] Mhz 396 */ 397 fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format) 398 / (2 * dsi->lanes); 399 if (fout_target < MHZ(40) || fout_target > MHZ(1250)) 400 return; 401 402 /* Find PLL settings */ 403 for (clk_cfg = dsi->info->clk_cfg; clk_cfg->min_freq != 0; clk_cfg++) { 404 if (fout_target > clk_cfg->min_freq && 405 fout_target <= clk_cfg->max_freq) { 406 setup_info->clkset = clk_cfg; 407 break; 408 } 409 } 410 411 fin_rate = clk_get_rate(clk); 412 413 switch (dsi->info->model) { 414 case RCAR_DSI_V3U: 415 default: 416 setup_info->vclk_divider = 1 << ((clk_cfg->vco_cntrl >> 4) & 0x3); 417 break; 418 419 case RCAR_DSI_V4H: 420 setup_info->vclk_divider = 1 << (((clk_cfg->vco_cntrl >> 3) & 0x7) + 1); 421 break; 422 } 423 424 rcar_mipi_dsi_pll_calc(dsi, fin_rate, fout_target, setup_info); 425 426 /* Find hsfreqrange */ 427 setup_info->hsfreq = setup_info->fout * 2; 428 for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) { 429 if (hsfreqrange_table[i][0] >= setup_info->hsfreq) { 430 setup_info->hsfreqrange = hsfreqrange_table[i][1]; 431 break; 432 } 433 } 434 435 err = abs((long)(setup_info->fout - fout_target) * 10000 / (long)fout_target); 436 437 dev_dbg(dsi->dev, 438 "Fout = %u * %lu / (%u * %u * %u) = %lu (target %lu Hz, error %d.%02u%%)\n", 439 setup_info->m, fin_rate, dsi->info->n_mul, setup_info->n, 440 setup_info->vclk_divider, setup_info->fout, fout_target, 441 err / 100, err % 100); 442 443 dev_dbg(dsi->dev, 444 "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n", 445 clk_cfg->vco_cntrl, clk_cfg->prop_cntrl, 446 setup_info->hsfreqrange); 447 } 448 449 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi, 450 const struct drm_display_mode *mode) 451 { 452 u32 setr; 453 u32 vprmset0r; 454 u32 vprmset1r; 455 u32 vprmset2r; 456 u32 vprmset3r; 457 u32 vprmset4r; 458 459 /* Configuration for Pixel Stream and Packet Header */ 460 if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 24) 461 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24); 462 else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 18) 463 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18); 464 else if (mipi_dsi_pixel_format_to_bpp(dsi->format) == 16) 465 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16); 466 else { 467 dev_warn(dsi->dev, "unsupported format"); 468 return; 469 } 470 471 /* Configuration for Blanking sequence and Input Pixel */ 472 setr = TXVMSETR_HSABPEN_EN | TXVMSETR_HBPBPEN_EN 473 | TXVMSETR_HFPBPEN_EN | TXVMSETR_SYNSEQ_PULSES 474 | TXVMSETR_PIXWDTH | TXVMSETR_VSTPM; 475 rcar_mipi_dsi_write(dsi, TXVMSETR, setr); 476 477 /* Configuration for Video Parameters */ 478 vprmset0r = (mode->flags & DRM_MODE_FLAG_PVSYNC ? 479 TXVMVPRMSET0R_VSPOL_HIG : TXVMVPRMSET0R_VSPOL_LOW) 480 | (mode->flags & DRM_MODE_FLAG_PHSYNC ? 481 TXVMVPRMSET0R_HSPOL_HIG : TXVMVPRMSET0R_HSPOL_LOW) 482 | TXVMVPRMSET0R_CSPC_RGB | TXVMVPRMSET0R_BPP_24; 483 484 vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay) 485 | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start); 486 487 vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay) 488 | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end); 489 490 vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay) 491 | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start); 492 493 vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay) 494 | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end); 495 496 rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r); 497 rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r); 498 rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r); 499 rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r); 500 rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r); 501 } 502 503 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi, 504 const struct drm_display_mode *mode) 505 { 506 struct dsi_setup_info setup_info = {}; 507 unsigned int timeout; 508 int ret; 509 int dsi_format; 510 u32 phy_setup; 511 u32 clockset2, clockset3; 512 u32 ppisetr; 513 u32 vclkset; 514 515 /* Checking valid format */ 516 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format); 517 if (dsi_format < 0) { 518 dev_warn(dsi->dev, "invalid format"); 519 return -EINVAL; 520 } 521 522 /* Parameters Calculation */ 523 rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll, 524 mode->clock * 1000, &setup_info); 525 526 /* LPCLK enable */ 527 rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN); 528 529 /* CFGCLK enabled */ 530 rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN); 531 532 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ); 533 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ); 534 535 rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR); 536 rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR); 537 538 /* PHY setting */ 539 phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP); 540 phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK; 541 phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange); 542 rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup); 543 544 switch (dsi->info->model) { 545 case RCAR_DSI_V3U: 546 default: 547 ret = rcar_mipi_dsi_init_phtw_v3u(dsi); 548 if (ret < 0) 549 return ret; 550 break; 551 552 case RCAR_DSI_V4H: 553 ret = rcar_mipi_dsi_init_phtw_v4h(dsi, &setup_info); 554 if (ret < 0) 555 return ret; 556 break; 557 } 558 559 /* PLL Clock Setting */ 560 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR); 561 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR); 562 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR); 563 564 clockset2 = CLOCKSET2_M(setup_info.m - dsi->info->clockset2_m_offset) 565 | CLOCKSET2_N(setup_info.n - 1) 566 | CLOCKSET2_VCO_CNTRL(setup_info.clkset->vco_cntrl); 567 clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.clkset->prop_cntrl) 568 | CLOCKSET3_INT_CNTRL(setup_info.clkset->int_cntrl) 569 | CLOCKSET3_CPBIAS_CNTRL(setup_info.clkset->cpbias_cntrl) 570 | CLOCKSET3_GMP_CNTRL(setup_info.clkset->gmp_cntrl); 571 rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2); 572 rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3); 573 574 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL); 575 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL); 576 udelay(10); 577 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL); 578 579 rcar_mipi_dsi_clr(dsi, TXSETR, TXSETR_LANECNT_MASK); 580 rcar_mipi_dsi_set(dsi, TXSETR, dsi->lanes - 1); 581 582 ppisetr = ((BIT(dsi->lanes) - 1) & PPISETR_DLEN_MASK) | PPISETR_CLEN; 583 rcar_mipi_dsi_write(dsi, PPISETR, ppisetr); 584 585 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ); 586 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ); 587 usleep_range(400, 500); 588 589 /* Checking PPI clock status register */ 590 for (timeout = 10; timeout > 0; --timeout) { 591 if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) && 592 (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) && 593 (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK_PHY)) 594 break; 595 596 usleep_range(1000, 2000); 597 } 598 599 if (!timeout) { 600 dev_err(dsi->dev, "failed to enable PPI clock\n"); 601 return -ETIMEDOUT; 602 } 603 604 switch (dsi->info->model) { 605 case RCAR_DSI_V3U: 606 default: 607 ret = rcar_mipi_dsi_post_init_phtw_v3u(dsi); 608 if (ret < 0) 609 return ret; 610 break; 611 612 case RCAR_DSI_V4H: 613 ret = rcar_mipi_dsi_post_init_phtw_v4h(dsi, &setup_info); 614 if (ret < 0) 615 return ret; 616 break; 617 } 618 619 /* Enable DOT clock */ 620 vclkset = VCLKSET_CKEN; 621 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset); 622 623 if (dsi_format == 24) 624 vclkset |= VCLKSET_BPP_24; 625 else if (dsi_format == 18) 626 vclkset |= VCLKSET_BPP_18; 627 else if (dsi_format == 16) 628 vclkset |= VCLKSET_BPP_16; 629 else { 630 dev_warn(dsi->dev, "unsupported format"); 631 return -EINVAL; 632 } 633 634 vclkset |= VCLKSET_COLOR_RGB | VCLKSET_LANE(dsi->lanes - 1); 635 636 switch (dsi->info->model) { 637 case RCAR_DSI_V3U: 638 default: 639 vclkset |= VCLKSET_DIV_V3U(__ffs(setup_info.vclk_divider)); 640 break; 641 642 case RCAR_DSI_V4H: 643 vclkset |= VCLKSET_DIV_V4H(__ffs(setup_info.vclk_divider) - 1); 644 break; 645 } 646 647 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset); 648 649 /* After setting VCLKSET register, enable VCLKEN */ 650 rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN); 651 652 dev_dbg(dsi->dev, "DSI device is started\n"); 653 654 return 0; 655 } 656 657 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi) 658 { 659 /* Disable VCLKEN */ 660 rcar_mipi_dsi_write(dsi, VCLKSET, 0); 661 662 /* Disable DOT clock */ 663 rcar_mipi_dsi_write(dsi, VCLKSET, 0); 664 665 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ); 666 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ); 667 668 /* CFGCLK disable */ 669 rcar_mipi_dsi_clr(dsi, CFGCLKSET, CFGCLKSET_CKEN); 670 671 /* LPCLK disable */ 672 rcar_mipi_dsi_clr(dsi, LPCLKSET, LPCLKSET_CKEN); 673 674 dev_dbg(dsi->dev, "DSI device is shutdown\n"); 675 } 676 677 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi) 678 { 679 int ret; 680 681 reset_control_deassert(dsi->rstc); 682 683 ret = clk_prepare_enable(dsi->clocks.mod); 684 if (ret < 0) 685 goto err_reset; 686 687 ret = clk_prepare_enable(dsi->clocks.dsi); 688 if (ret < 0) 689 goto err_clock; 690 691 return 0; 692 693 err_clock: 694 clk_disable_unprepare(dsi->clocks.mod); 695 err_reset: 696 reset_control_assert(dsi->rstc); 697 return ret; 698 } 699 700 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi) 701 { 702 clk_disable_unprepare(dsi->clocks.dsi); 703 clk_disable_unprepare(dsi->clocks.mod); 704 705 reset_control_assert(dsi->rstc); 706 } 707 708 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi) 709 { 710 /* 711 * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont 712 * write how to check. So we skip this check in this patch 713 */ 714 u32 status; 715 int ret; 716 717 /* Start HS clock. */ 718 rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS); 719 720 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 721 status & PPICLSR_TOHS, 722 2000, 10000, false, dsi, PPICLSR); 723 if (ret < 0) { 724 dev_err(dsi->dev, "failed to enable HS clock\n"); 725 return ret; 726 } 727 728 rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS); 729 730 return 0; 731 } 732 733 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi) 734 { 735 u32 status; 736 int ret; 737 738 /* Wait for the link to be ready. */ 739 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 740 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)), 741 2000, 10000, false, dsi, LINKSR); 742 if (ret < 0) { 743 dev_err(dsi->dev, "Link failed to become ready\n"); 744 return ret; 745 } 746 747 /* De-assert video FIFO clear. */ 748 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR); 749 750 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 751 status & TXVMSR_VFRDY, 752 2000, 10000, false, dsi, TXVMSR); 753 if (ret < 0) { 754 dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n"); 755 return ret; 756 } 757 758 /* Enable transmission in video mode. */ 759 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO); 760 761 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 762 status & TXVMSR_RDY, 763 2000, 10000, false, dsi, TXVMSR); 764 if (ret < 0) { 765 dev_err(dsi->dev, "Failed to enable video transmission\n"); 766 return ret; 767 } 768 769 return 0; 770 } 771 772 static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi) 773 { 774 u32 status; 775 int ret; 776 777 /* Disable transmission in video mode. */ 778 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO); 779 780 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 781 !(status & TXVMSR_ACT), 782 2000, 100000, false, dsi, TXVMSR); 783 if (ret < 0) { 784 dev_err(dsi->dev, "Failed to disable video transmission\n"); 785 return; 786 } 787 788 /* Assert video FIFO clear. */ 789 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR); 790 791 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 792 !(status & TXVMSR_VFRDY), 793 2000, 100000, false, dsi, TXVMSR); 794 if (ret < 0) { 795 dev_err(dsi->dev, "Failed to assert video FIFO clear\n"); 796 return; 797 } 798 } 799 800 /* ----------------------------------------------------------------------------- 801 * Bridge 802 */ 803 804 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge, 805 struct drm_encoder *encoder, 806 enum drm_bridge_attach_flags flags) 807 { 808 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); 809 810 return drm_bridge_attach(encoder, dsi->next_bridge, bridge, 811 flags); 812 } 813 814 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge, 815 struct drm_atomic_state *state) 816 { 817 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); 818 819 rcar_mipi_dsi_start_video(dsi); 820 } 821 822 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge, 823 struct drm_atomic_state *state) 824 { 825 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); 826 827 rcar_mipi_dsi_stop_video(dsi); 828 } 829 830 void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge, 831 struct drm_atomic_state *state) 832 { 833 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); 834 const struct drm_display_mode *mode; 835 struct drm_connector *connector; 836 struct drm_crtc *crtc; 837 int ret; 838 839 connector = drm_atomic_get_new_connector_for_encoder(state, 840 bridge->encoder); 841 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 842 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode; 843 844 ret = rcar_mipi_dsi_clk_enable(dsi); 845 if (ret < 0) { 846 dev_err(dsi->dev, "failed to enable DSI clocks\n"); 847 return; 848 } 849 850 ret = rcar_mipi_dsi_startup(dsi, mode); 851 if (ret < 0) 852 goto err_dsi_startup; 853 854 rcar_mipi_dsi_set_display_timing(dsi, mode); 855 856 ret = rcar_mipi_dsi_start_hs_clock(dsi); 857 if (ret < 0) 858 goto err_dsi_start_hs; 859 860 return; 861 862 err_dsi_start_hs: 863 rcar_mipi_dsi_shutdown(dsi); 864 err_dsi_startup: 865 rcar_mipi_dsi_clk_disable(dsi); 866 } 867 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_enable); 868 869 void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge) 870 { 871 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge); 872 873 rcar_mipi_dsi_shutdown(dsi); 874 rcar_mipi_dsi_clk_disable(dsi); 875 } 876 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_disable); 877 878 static enum drm_mode_status 879 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 880 const struct drm_display_info *info, 881 const struct drm_display_mode *mode) 882 { 883 if (mode->clock > 297000) 884 return MODE_CLOCK_HIGH; 885 886 return MODE_OK; 887 } 888 889 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = { 890 .attach = rcar_mipi_dsi_attach, 891 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 892 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 893 .atomic_reset = drm_atomic_helper_bridge_reset, 894 .atomic_enable = rcar_mipi_dsi_atomic_enable, 895 .atomic_disable = rcar_mipi_dsi_atomic_disable, 896 .mode_valid = rcar_mipi_dsi_bridge_mode_valid, 897 }; 898 899 /* ----------------------------------------------------------------------------- 900 * Host setting 901 */ 902 903 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host, 904 struct mipi_dsi_device *device) 905 { 906 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host); 907 int ret; 908 909 if (device->lanes > dsi->num_data_lanes) 910 return -EINVAL; 911 912 dsi->lanes = device->lanes; 913 dsi->format = device->format; 914 915 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 916 1, 0); 917 if (IS_ERR(dsi->next_bridge)) { 918 ret = PTR_ERR(dsi->next_bridge); 919 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret); 920 return ret; 921 } 922 923 /* Initialize the DRM bridge. */ 924 dsi->bridge.of_node = dsi->dev->of_node; 925 drm_bridge_add(&dsi->bridge); 926 927 return 0; 928 } 929 930 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host, 931 struct mipi_dsi_device *device) 932 { 933 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host); 934 935 drm_bridge_remove(&dsi->bridge); 936 937 return 0; 938 } 939 940 static ssize_t rcar_mipi_dsi_host_tx_transfer(struct mipi_dsi_host *host, 941 const struct mipi_dsi_msg *msg, 942 bool is_rx_xfer) 943 { 944 const bool is_tx_long = mipi_dsi_packet_format_is_long(msg->type); 945 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host); 946 struct mipi_dsi_packet packet; 947 u8 payload[16] = { 0 }; 948 u32 status; 949 int ret; 950 951 ret = mipi_dsi_create_packet(&packet, msg); 952 if (ret) 953 return ret; 954 955 /* Configure LP or HS command transfer. */ 956 rcar_mipi_dsi_write(dsi, TXCMSETR, (msg->flags & MIPI_DSI_MSG_USE_LPM) ? 957 TXCMSETR_SPDTYP : 0); 958 959 /* Register access mode for RX transfer. */ 960 if (is_rx_xfer) 961 rcar_mipi_dsi_write(dsi, RXPSETR, 0); 962 963 /* Do not use IRQ, poll for completion, the completion is quick. */ 964 rcar_mipi_dsi_write(dsi, TXCMIER, 0); 965 966 /* 967 * Send the header: 968 * header[0] = Virtual Channel + Data Type 969 * header[1] = Word Count LSB (LP) or first param (SP) 970 * header[2] = Word Count MSB (LP) or second param (SP) 971 */ 972 rcar_mipi_dsi_write(dsi, TXCMPHDR, 973 (is_tx_long ? TXCMPHDR_FMT : 0) | 974 TXCMPHDR_VC(msg->channel) | 975 TXCMPHDR_DT(msg->type) | 976 TXCMPHDR_DATA1(packet.header[2]) | 977 TXCMPHDR_DATA0(packet.header[1])); 978 979 if (is_tx_long) { 980 memcpy(payload, packet.payload, 981 min(msg->tx_len, sizeof(payload))); 982 983 rcar_mipi_dsi_write(dsi, TXCMPPD0R, 984 (payload[3] << 24) | (payload[2] << 16) | 985 (payload[1] << 8) | payload[0]); 986 rcar_mipi_dsi_write(dsi, TXCMPPD1R, 987 (payload[7] << 24) | (payload[6] << 16) | 988 (payload[5] << 8) | payload[4]); 989 rcar_mipi_dsi_write(dsi, TXCMPPD2R, 990 (payload[11] << 24) | (payload[10] << 16) | 991 (payload[9] << 8) | payload[8]); 992 rcar_mipi_dsi_write(dsi, TXCMPPD3R, 993 (payload[15] << 24) | (payload[14] << 16) | 994 (payload[13] << 8) | payload[12]); 995 } 996 997 /* Start the transfer, RX with BTA, TX without BTA. */ 998 if (is_rx_xfer) { 999 rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_BTAREQ); 1000 1001 /* Wait until the transmission, BTA, reception completed. */ 1002 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 1003 (status & RXPSR_BTAREQEND), 1004 2000, 50000, false, dsi, RXPSR); 1005 } else { 1006 rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_TXREQ); 1007 1008 /* Wait until the transmission completed. */ 1009 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 1010 (status & TXCMSR_TXREQEND), 1011 2000, 50000, false, dsi, TXCMSR); 1012 } 1013 1014 if (ret < 0) { 1015 dev_err(dsi->dev, "Command transfer timeout (0x%08x)\n", 1016 status); 1017 return ret; 1018 } 1019 1020 return packet.size; 1021 } 1022 1023 static ssize_t rcar_mipi_dsi_host_rx_transfer(struct mipi_dsi_host *host, 1024 const struct mipi_dsi_msg *msg) 1025 { 1026 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host); 1027 u8 *rx_buf = (u8 *)(msg->rx_buf); 1028 u32 reg, data, status, wc; 1029 int i, ret; 1030 1031 /* RX transfer received data validation and parsing starts here. */ 1032 reg = rcar_mipi_dsi_read(dsi, TOSR); 1033 if (reg & TOSR_TATO) { /* Turn-Around TimeOut. */ 1034 /* Clear TATO Turn-Around TimeOut bit. */ 1035 rcar_mipi_dsi_write(dsi, TOSR, TOSR_TATO); 1036 return -ETIMEDOUT; 1037 } 1038 1039 reg = rcar_mipi_dsi_read(dsi, RXPSR); 1040 1041 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) { 1042 /* Transfer with zero-length RX. */ 1043 if (!(reg & RXPSR_RCVACK)) { 1044 /* No ACK on RX response received. */ 1045 return -EINVAL; 1046 } 1047 } else { 1048 /* Transfer with non-zero-length RX. */ 1049 if (!(reg & RXPSR_RCVRESP)) { 1050 /* No packet header of RX response received. */ 1051 return -EINVAL; 1052 } 1053 1054 if (reg & (RXPSR_CRCERR | RXPSR_WCERR | RXPSR_AXIERR | RXPSR_OVRERR)) { 1055 /* Incorrect response payload. */ 1056 return -ENODATA; 1057 } 1058 1059 data = rcar_mipi_dsi_read(dsi, RXPHDR); 1060 if (data & RXPHDR_FMT) { /* Long Packet Response. */ 1061 /* Read Long Packet Response length from packet header. */ 1062 wc = data & 0xffff; 1063 if (wc > msg->rx_len) { 1064 dev_warn(dsi->dev, 1065 "Long Packet Response longer than RX buffer (%d), limited to %zu Bytes\n", 1066 wc, msg->rx_len); 1067 wc = msg->rx_len; 1068 } 1069 1070 if (wc > 16) { 1071 dev_warn(dsi->dev, 1072 "Long Packet Response too long (%d), limited to 16 Bytes\n", 1073 wc); 1074 wc = 16; 1075 } 1076 1077 for (i = 0; i < msg->rx_len; i++) { 1078 if (!(i % 4)) 1079 data = rcar_mipi_dsi_read(dsi, RXPPD0R + i); 1080 1081 rx_buf[i] = data & 0xff; 1082 data >>= 8; 1083 } 1084 } else { /* Short Packet Response. */ 1085 if (msg->rx_len >= 1) 1086 rx_buf[0] = data & 0xff; 1087 if (msg->rx_len >= 2) 1088 rx_buf[1] = (data >> 8) & 0xff; 1089 if (msg->rx_len >= 3) { 1090 dev_warn(dsi->dev, 1091 "Expected Short Packet Response too long (%zu), limited to 2 Bytes\n", 1092 msg->rx_len); 1093 } 1094 } 1095 } 1096 1097 if (reg & RXPSR_RCVAKE) { 1098 /* Acknowledge and Error report received. */ 1099 return -EFAULT; 1100 } 1101 1102 /* Wait until the bus handover to host processor completed. */ 1103 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 1104 !(status & PPIDL0SR_DIR), 1105 2000, 50000, false, dsi, PPIDL0SR); 1106 if (ret < 0) { 1107 dev_err(dsi->dev, "Command RX DIR timeout (0x%08x)\n", status); 1108 return ret; 1109 } 1110 1111 /* Wait until the data lane is in LP11 stop state. */ 1112 ret = read_poll_timeout(rcar_mipi_dsi_read, status, 1113 status & PPIDL0SR_STPST, 1114 2000, 50000, false, dsi, PPIDL0SR); 1115 if (ret < 0) { 1116 dev_err(dsi->dev, "Command RX STPST timeout (0x%08x)\n", status); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static ssize_t rcar_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 1124 const struct mipi_dsi_msg *msg) 1125 { 1126 const bool is_rx_xfer = (msg->flags & MIPI_DSI_MSG_REQ_ACK) || msg->rx_len; 1127 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host); 1128 int ret; 1129 1130 if (msg->tx_len > 16 || msg->rx_len > 16) { 1131 /* ToDo: Implement Memory on AXI bus command mode. */ 1132 dev_warn(dsi->dev, 1133 "Register-based command mode supports only up to 16 Bytes long payload\n"); 1134 return -EOPNOTSUPP; 1135 } 1136 1137 ret = rcar_mipi_dsi_host_tx_transfer(host, msg, is_rx_xfer); 1138 1139 /* If TX transfer succeeded and this transfer has RX part. */ 1140 if (ret >= 0 && is_rx_xfer) { 1141 ret = rcar_mipi_dsi_host_rx_transfer(host, msg); 1142 if (ret) 1143 return ret; 1144 1145 ret = msg->rx_len; 1146 } 1147 1148 /* 1149 * Wait a bit between commands, otherwise panels based on ILI9881C 1150 * TCON may fail to correctly receive all commands sent to them. 1151 * Until we can actually test with another DSI device, keep the 1152 * delay here, but eventually this delay might have to be moved 1153 * into the ILI9881C panel driver. 1154 */ 1155 usleep_range(1000, 2000); 1156 1157 /* Clear the completion interrupt. */ 1158 if (!msg->rx_len) 1159 rcar_mipi_dsi_write(dsi, TXCMSR, TXCMSR_TXREQEND); 1160 1161 return ret; 1162 } 1163 1164 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = { 1165 .attach = rcar_mipi_dsi_host_attach, 1166 .detach = rcar_mipi_dsi_host_detach, 1167 .transfer = rcar_mipi_dsi_host_transfer 1168 }; 1169 1170 /* ----------------------------------------------------------------------------- 1171 * Probe & Remove 1172 */ 1173 1174 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi) 1175 { 1176 int ret; 1177 1178 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); 1179 if (ret < 0) { 1180 dev_err(dsi->dev, "missing or invalid data-lanes property\n"); 1181 return ret; 1182 } 1183 1184 dsi->num_data_lanes = ret; 1185 return 0; 1186 } 1187 1188 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi, 1189 const char *name, 1190 bool optional) 1191 { 1192 struct clk *clk; 1193 1194 clk = devm_clk_get(dsi->dev, name); 1195 if (!IS_ERR(clk)) 1196 return clk; 1197 1198 if (PTR_ERR(clk) == -ENOENT && optional) 1199 return NULL; 1200 1201 dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n", 1202 name ? name : "module"); 1203 1204 return clk; 1205 } 1206 1207 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi) 1208 { 1209 dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false); 1210 if (IS_ERR(dsi->clocks.mod)) 1211 return PTR_ERR(dsi->clocks.mod); 1212 1213 dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true); 1214 if (IS_ERR(dsi->clocks.pll)) 1215 return PTR_ERR(dsi->clocks.pll); 1216 1217 dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true); 1218 if (IS_ERR(dsi->clocks.dsi)) 1219 return PTR_ERR(dsi->clocks.dsi); 1220 1221 if (!dsi->clocks.pll && !dsi->clocks.dsi) { 1222 dev_err(dsi->dev, "no input clock (pll, dsi)\n"); 1223 return -EINVAL; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int rcar_mipi_dsi_probe(struct platform_device *pdev) 1230 { 1231 struct rcar_mipi_dsi *dsi; 1232 int ret; 1233 1234 dsi = devm_drm_bridge_alloc(&pdev->dev, struct rcar_mipi_dsi, bridge, 1235 &rcar_mipi_dsi_bridge_ops); 1236 if (IS_ERR(dsi)) 1237 return PTR_ERR(dsi); 1238 1239 platform_set_drvdata(pdev, dsi); 1240 1241 dsi->dev = &pdev->dev; 1242 dsi->info = of_device_get_match_data(&pdev->dev); 1243 1244 ret = rcar_mipi_dsi_parse_dt(dsi); 1245 if (ret < 0) 1246 return ret; 1247 1248 /* Acquire resources. */ 1249 dsi->mmio = devm_platform_ioremap_resource(pdev, 0); 1250 if (IS_ERR(dsi->mmio)) 1251 return PTR_ERR(dsi->mmio); 1252 1253 ret = rcar_mipi_dsi_get_clocks(dsi); 1254 if (ret < 0) 1255 return ret; 1256 1257 dsi->rstc = devm_reset_control_get(dsi->dev, NULL); 1258 if (IS_ERR(dsi->rstc)) { 1259 dev_err(dsi->dev, "failed to get cpg reset\n"); 1260 return PTR_ERR(dsi->rstc); 1261 } 1262 1263 /* Initialize the DSI host. */ 1264 dsi->host.dev = dsi->dev; 1265 dsi->host.ops = &rcar_mipi_dsi_host_ops; 1266 ret = mipi_dsi_host_register(&dsi->host); 1267 if (ret < 0) 1268 return ret; 1269 1270 return 0; 1271 } 1272 1273 static void rcar_mipi_dsi_remove(struct platform_device *pdev) 1274 { 1275 struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev); 1276 1277 mipi_dsi_host_unregister(&dsi->host); 1278 } 1279 1280 static const struct rcar_mipi_dsi_device_info v3u_data = { 1281 .model = RCAR_DSI_V3U, 1282 .clk_cfg = dsi_clk_cfg_v3u, 1283 .clockset2_m_offset = 2, 1284 .n_min = 3, 1285 .n_max = 8, 1286 .n_mul = 1, 1287 .fpfd_min = MHZ(2), 1288 .fpfd_max = MHZ(8), 1289 .m_min = 64, 1290 .m_max = 625, 1291 .fout_min = MHZ(320), 1292 .fout_max = MHZ(1250), 1293 }; 1294 1295 static const struct rcar_mipi_dsi_device_info v4h_data = { 1296 .model = RCAR_DSI_V4H, 1297 .clk_cfg = dsi_clk_cfg_v4h, 1298 .clockset2_m_offset = 0, 1299 .n_min = 1, 1300 .n_max = 8, 1301 .n_mul = 2, 1302 .fpfd_min = MHZ(8), 1303 .fpfd_max = MHZ(24), 1304 .m_min = 167, 1305 .m_max = 1000, 1306 .fout_min = MHZ(2000), 1307 .fout_max = MHZ(4000), 1308 }; 1309 1310 static const struct of_device_id rcar_mipi_dsi_of_table[] = { 1311 { .compatible = "renesas,r8a779a0-dsi-csi2-tx", .data = &v3u_data }, 1312 { .compatible = "renesas,r8a779g0-dsi-csi2-tx", .data = &v4h_data }, 1313 /* DSI in r8a779h0 is identical to r8a779g0 */ 1314 { .compatible = "renesas,r8a779h0-dsi-csi2-tx", .data = &v4h_data }, 1315 { } 1316 }; 1317 1318 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table); 1319 1320 static struct platform_driver rcar_mipi_dsi_platform_driver = { 1321 .probe = rcar_mipi_dsi_probe, 1322 .remove = rcar_mipi_dsi_remove, 1323 .driver = { 1324 .name = "rcar-mipi-dsi", 1325 .of_match_table = rcar_mipi_dsi_of_table, 1326 }, 1327 }; 1328 1329 module_platform_driver(rcar_mipi_dsi_platform_driver); 1330 1331 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver"); 1332 MODULE_LICENSE("GPL"); 1333