1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU7_DISCRETE_H 25 #define SMU7_DISCRETE_H 26 27 #include "smu7.h" 28 29 #pragma pack(push, 1) 30 31 #define SMU7_DTE_ITERATIONS 5 32 #define SMU7_DTE_SOURCES 3 33 #define SMU7_DTE_SINKS 1 34 #define SMU7_NUM_CPU_TES 0 35 #define SMU7_NUM_GPU_TES 1 36 #define SMU7_NUM_NON_TES 2 37 38 struct SMU7_SoftRegisters { 39 uint32_t RefClockFrequency; 40 uint32_t PmTimerP; 41 uint32_t FeatureEnables; 42 uint32_t PreVBlankGap; 43 uint32_t VBlankTimeout; 44 uint32_t TrainTimeGap; 45 46 uint32_t MvddSwitchTime; 47 uint32_t LongestAcpiTrainTime; 48 uint32_t AcpiDelay; 49 uint32_t G5TrainTime; 50 uint32_t DelayMpllPwron; 51 uint32_t VoltageChangeTimeout; 52 uint32_t HandshakeDisables; 53 54 uint8_t DisplayPhy1Config; 55 uint8_t DisplayPhy2Config; 56 uint8_t DisplayPhy3Config; 57 uint8_t DisplayPhy4Config; 58 59 uint8_t DisplayPhy5Config; 60 uint8_t DisplayPhy6Config; 61 uint8_t DisplayPhy7Config; 62 uint8_t DisplayPhy8Config; 63 64 uint32_t AverageGraphicsA; 65 uint32_t AverageMemoryA; 66 uint32_t AverageGioA; 67 68 uint8_t SClkDpmEnabledLevels; 69 uint8_t MClkDpmEnabledLevels; 70 uint8_t LClkDpmEnabledLevels; 71 uint8_t PCIeDpmEnabledLevels; 72 73 uint8_t UVDDpmEnabledLevels; 74 uint8_t SAMUDpmEnabledLevels; 75 uint8_t ACPDpmEnabledLevels; 76 uint8_t VCEDpmEnabledLevels; 77 78 uint32_t DRAM_LOG_ADDR_H; 79 uint32_t DRAM_LOG_ADDR_L; 80 uint32_t DRAM_LOG_PHY_ADDR_H; 81 uint32_t DRAM_LOG_PHY_ADDR_L; 82 uint32_t DRAM_LOG_BUFF_SIZE; 83 uint32_t UlvEnterC; 84 uint32_t UlvTime; 85 uint32_t Reserved[3]; 86 87 }; 88 89 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 90 91 struct SMU7_Discrete_VoltageLevel { 92 uint16_t Voltage; 93 uint16_t StdVoltageHiSidd; 94 uint16_t StdVoltageLoSidd; 95 uint8_t Smio; 96 uint8_t padding; 97 }; 98 99 typedef struct SMU7_Discrete_VoltageLevel SMU7_Discrete_VoltageLevel; 100 101 struct SMU7_Discrete_GraphicsLevel { 102 uint32_t Flags; 103 uint32_t MinVddc; 104 uint32_t MinVddcPhases; 105 106 uint32_t SclkFrequency; 107 108 uint8_t padding1[2]; 109 uint16_t ActivityLevel; 110 111 uint32_t CgSpllFuncCntl3; 112 uint32_t CgSpllFuncCntl4; 113 uint32_t SpllSpreadSpectrum; 114 uint32_t SpllSpreadSpectrum2; 115 uint32_t CcPwrDynRm; 116 uint32_t CcPwrDynRm1; 117 uint8_t SclkDid; 118 uint8_t DisplayWatermark; 119 uint8_t EnabledForActivity; 120 uint8_t EnabledForThrottle; 121 uint8_t UpH; 122 uint8_t DownH; 123 uint8_t VoltageDownH; 124 uint8_t PowerThrottle; 125 uint8_t DeepSleepDivId; 126 uint8_t padding[3]; 127 }; 128 129 typedef struct SMU7_Discrete_GraphicsLevel SMU7_Discrete_GraphicsLevel; 130 131 struct SMU7_Discrete_ACPILevel { 132 uint32_t Flags; 133 uint32_t MinVddc; 134 uint32_t MinVddcPhases; 135 uint32_t SclkFrequency; 136 uint8_t SclkDid; 137 uint8_t DisplayWatermark; 138 uint8_t DeepSleepDivId; 139 uint8_t padding; 140 uint32_t CgSpllFuncCntl; 141 uint32_t CgSpllFuncCntl2; 142 uint32_t CgSpllFuncCntl3; 143 uint32_t CgSpllFuncCntl4; 144 uint32_t SpllSpreadSpectrum; 145 uint32_t SpllSpreadSpectrum2; 146 uint32_t CcPwrDynRm; 147 uint32_t CcPwrDynRm1; 148 }; 149 150 typedef struct SMU7_Discrete_ACPILevel SMU7_Discrete_ACPILevel; 151 152 struct SMU7_Discrete_Ulv { 153 uint32_t CcPwrDynRm; 154 uint32_t CcPwrDynRm1; 155 uint16_t VddcOffset; 156 uint8_t VddcOffsetVid; 157 uint8_t VddcPhase; 158 uint32_t Reserved; 159 }; 160 161 typedef struct SMU7_Discrete_Ulv SMU7_Discrete_Ulv; 162 163 struct SMU7_Discrete_MemoryLevel { 164 uint32_t MinVddc; 165 uint32_t MinVddcPhases; 166 uint32_t MinVddci; 167 uint32_t MinMvdd; 168 169 uint32_t MclkFrequency; 170 171 uint8_t EdcReadEnable; 172 uint8_t EdcWriteEnable; 173 uint8_t RttEnable; 174 uint8_t StutterEnable; 175 176 uint8_t StrobeEnable; 177 uint8_t StrobeRatio; 178 uint8_t EnabledForThrottle; 179 uint8_t EnabledForActivity; 180 181 uint8_t UpH; 182 uint8_t DownH; 183 uint8_t VoltageDownH; 184 uint8_t padding; 185 186 uint16_t ActivityLevel; 187 uint8_t DisplayWatermark; 188 uint8_t padding1; 189 190 uint32_t MpllFuncCntl; 191 uint32_t MpllFuncCntl_1; 192 uint32_t MpllFuncCntl_2; 193 uint32_t MpllAdFuncCntl; 194 uint32_t MpllDqFuncCntl; 195 uint32_t MclkPwrmgtCntl; 196 uint32_t DllCntl; 197 uint32_t MpllSs1; 198 uint32_t MpllSs2; 199 }; 200 201 typedef struct SMU7_Discrete_MemoryLevel SMU7_Discrete_MemoryLevel; 202 203 struct SMU7_Discrete_LinkLevel { 204 uint8_t PcieGenSpeed; 205 uint8_t PcieLaneCount; 206 uint8_t EnabledForActivity; 207 uint8_t Padding; 208 uint32_t DownT; 209 uint32_t UpT; 210 uint32_t Reserved; 211 }; 212 213 typedef struct SMU7_Discrete_LinkLevel SMU7_Discrete_LinkLevel; 214 215 216 struct SMU7_Discrete_MCArbDramTimingTableEntry { 217 uint32_t McArbDramTiming; 218 uint32_t McArbDramTiming2; 219 uint8_t McArbBurstTime; 220 uint8_t padding[3]; 221 }; 222 223 typedef struct SMU7_Discrete_MCArbDramTimingTableEntry SMU7_Discrete_MCArbDramTimingTableEntry; 224 225 struct SMU7_Discrete_MCArbDramTimingTable { 226 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 227 }; 228 229 typedef struct SMU7_Discrete_MCArbDramTimingTable SMU7_Discrete_MCArbDramTimingTable; 230 231 struct SMU7_Discrete_UvdLevel { 232 uint32_t VclkFrequency; 233 uint32_t DclkFrequency; 234 uint16_t MinVddc; 235 uint8_t MinVddcPhases; 236 uint8_t VclkDivider; 237 uint8_t DclkDivider; 238 uint8_t padding[3]; 239 }; 240 241 typedef struct SMU7_Discrete_UvdLevel SMU7_Discrete_UvdLevel; 242 243 struct SMU7_Discrete_ExtClkLevel { 244 uint32_t Frequency; 245 uint16_t MinVoltage; 246 uint8_t MinPhases; 247 uint8_t Divider; 248 }; 249 250 typedef struct SMU7_Discrete_ExtClkLevel SMU7_Discrete_ExtClkLevel; 251 252 struct SMU7_Discrete_StateInfo { 253 uint32_t SclkFrequency; 254 uint32_t MclkFrequency; 255 uint32_t VclkFrequency; 256 uint32_t DclkFrequency; 257 uint32_t SamclkFrequency; 258 uint32_t AclkFrequency; 259 uint32_t EclkFrequency; 260 uint16_t MvddVoltage; 261 uint16_t padding16; 262 uint8_t DisplayWatermark; 263 uint8_t McArbIndex; 264 uint8_t McRegIndex; 265 uint8_t SeqIndex; 266 uint8_t SclkDid; 267 int8_t SclkIndex; 268 int8_t MclkIndex; 269 uint8_t PCIeGen; 270 271 }; 272 273 typedef struct SMU7_Discrete_StateInfo SMU7_Discrete_StateInfo; 274 275 276 struct SMU7_Discrete_DpmTable { 277 SMU7_PIDController GraphicsPIDController; 278 SMU7_PIDController MemoryPIDController; 279 SMU7_PIDController LinkPIDController; 280 281 uint32_t SystemFlags; 282 283 284 uint32_t SmioMaskVddcVid; 285 uint32_t SmioMaskVddcPhase; 286 uint32_t SmioMaskVddciVid; 287 uint32_t SmioMaskMvddVid; 288 289 uint32_t VddcLevelCount; 290 uint32_t VddciLevelCount; 291 uint32_t MvddLevelCount; 292 293 SMU7_Discrete_VoltageLevel VddcLevel [SMU7_MAX_LEVELS_VDDC]; 294 // SMU7_Discrete_VoltageLevel VddcStandardReference [SMU7_MAX_LEVELS_VDDC]; 295 SMU7_Discrete_VoltageLevel VddciLevel [SMU7_MAX_LEVELS_VDDCI]; 296 SMU7_Discrete_VoltageLevel MvddLevel [SMU7_MAX_LEVELS_MVDD]; 297 298 uint8_t GraphicsDpmLevelCount; 299 uint8_t MemoryDpmLevelCount; 300 uint8_t LinkLevelCount; 301 uint8_t UvdLevelCount; 302 uint8_t VceLevelCount; 303 uint8_t AcpLevelCount; 304 uint8_t SamuLevelCount; 305 uint8_t MasterDeepSleepControl; 306 uint32_t Reserved[5]; 307 // uint32_t SamuDefaultLevel; 308 309 SMU7_Discrete_GraphicsLevel GraphicsLevel [SMU7_MAX_LEVELS_GRAPHICS]; 310 SMU7_Discrete_MemoryLevel MemoryACPILevel; 311 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; 312 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; 313 SMU7_Discrete_ACPILevel ACPILevel; 314 SMU7_Discrete_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 315 SMU7_Discrete_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 316 SMU7_Discrete_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 317 SMU7_Discrete_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 318 SMU7_Discrete_Ulv Ulv; 319 320 uint32_t SclkStepSize; 321 uint32_t Smio [SMU7_MAX_ENTRIES_SMIO]; 322 323 uint8_t UvdBootLevel; 324 uint8_t VceBootLevel; 325 uint8_t AcpBootLevel; 326 uint8_t SamuBootLevel; 327 328 uint8_t UVDInterval; 329 uint8_t VCEInterval; 330 uint8_t ACPInterval; 331 uint8_t SAMUInterval; 332 333 uint8_t GraphicsBootLevel; 334 uint8_t GraphicsVoltageChangeEnable; 335 uint8_t GraphicsThermThrottleEnable; 336 uint8_t GraphicsInterval; 337 338 uint8_t VoltageInterval; 339 uint8_t ThermalInterval; 340 uint16_t TemperatureLimitHigh; 341 342 uint16_t TemperatureLimitLow; 343 uint8_t MemoryBootLevel; 344 uint8_t MemoryVoltageChangeEnable; 345 346 uint8_t MemoryInterval; 347 uint8_t MemoryThermThrottleEnable; 348 uint16_t VddcVddciDelta; 349 350 uint16_t VoltageResponseTime; 351 uint16_t PhaseResponseTime; 352 353 uint8_t PCIeBootLinkLevel; 354 uint8_t PCIeGenInterval; 355 uint8_t DTEInterval; 356 uint8_t DTEMode; 357 358 uint8_t SVI2Enable; 359 uint8_t VRHotGpio; 360 uint8_t AcDcGpio; 361 uint8_t ThermGpio; 362 363 uint16_t PPM_PkgPwrLimit; 364 uint16_t PPM_TemperatureLimit; 365 366 uint16_t DefaultTdp; 367 uint16_t TargetTdp; 368 369 uint16_t FpsHighT; 370 uint16_t FpsLowT; 371 372 uint16_t BAPMTI_R [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 373 uint16_t BAPMTI_RC [SMU7_DTE_ITERATIONS][SMU7_DTE_SOURCES][SMU7_DTE_SINKS]; 374 375 uint8_t DTEAmbientTempBase; 376 uint8_t DTETjOffset; 377 uint8_t GpuTjMax; 378 uint8_t GpuTjHyst; 379 380 uint16_t BootVddc; 381 uint16_t BootVddci; 382 383 uint16_t BootMVdd; 384 uint16_t padding; 385 386 uint32_t BAPM_TEMP_GRADIENT; 387 388 uint32_t LowSclkInterruptT; 389 }; 390 391 typedef struct SMU7_Discrete_DpmTable SMU7_Discrete_DpmTable; 392 393 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 394 #define SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU7_MAX_LEVELS_MEMORY 395 396 struct SMU7_Discrete_MCRegisterAddress { 397 uint16_t s0; 398 uint16_t s1; 399 }; 400 401 typedef struct SMU7_Discrete_MCRegisterAddress SMU7_Discrete_MCRegisterAddress; 402 403 struct SMU7_Discrete_MCRegisterSet { 404 uint32_t value[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 405 }; 406 407 typedef struct SMU7_Discrete_MCRegisterSet SMU7_Discrete_MCRegisterSet; 408 409 struct SMU7_Discrete_MCRegisters { 410 uint8_t last; 411 uint8_t reserved[3]; 412 SMU7_Discrete_MCRegisterAddress address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 413 SMU7_Discrete_MCRegisterSet data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 414 }; 415 416 typedef struct SMU7_Discrete_MCRegisters SMU7_Discrete_MCRegisters; 417 418 struct SMU7_Discrete_FanTable { 419 uint16_t FdoMode; 420 int16_t TempMin; 421 int16_t TempMed; 422 int16_t TempMax; 423 int16_t Slope1; 424 int16_t Slope2; 425 int16_t FdoMin; 426 int16_t HystUp; 427 int16_t HystDown; 428 int16_t HystSlope; 429 int16_t TempRespLim; 430 int16_t TempCurr; 431 int16_t SlopeCurr; 432 int16_t PwmCurr; 433 uint32_t RefreshPeriod; 434 int16_t FdoMax; 435 uint8_t TempSrc; 436 int8_t Padding; 437 }; 438 439 typedef struct SMU7_Discrete_FanTable SMU7_Discrete_FanTable; 440 441 442 struct SMU7_Discrete_PmFuses { 443 // dw0-dw1 444 uint8_t BapmVddCVidHiSidd[8]; 445 446 // dw2-dw3 447 uint8_t BapmVddCVidLoSidd[8]; 448 449 // dw4-dw5 450 uint8_t VddCVid[8]; 451 452 // dw6 453 uint8_t SviLoadLineEn; 454 uint8_t SviLoadLineVddC; 455 uint8_t SviLoadLineTrimVddC; 456 uint8_t SviLoadLineOffsetVddC; 457 458 // dw7 459 uint16_t TDC_VDDC_PkgLimit; 460 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 461 uint8_t TDC_MAWt; 462 463 // dw8 464 uint8_t TdcWaterfallCtl; 465 uint8_t LPMLTemperatureMin; 466 uint8_t LPMLTemperatureMax; 467 uint8_t Reserved; 468 469 // dw9-dw10 470 uint8_t BapmVddCVidHiSidd2[8]; 471 472 // dw11-dw12 473 int16_t FuzzyFan_ErrorSetDelta; 474 int16_t FuzzyFan_ErrorRateSetDelta; 475 int16_t FuzzyFan_PwmSetDelta; 476 uint16_t CalcMeasPowerBlend; 477 478 // dw13-dw16 479 uint8_t GnbLPML[16]; 480 481 // dw17 482 uint8_t GnbLPMLMaxVid; 483 uint8_t GnbLPMLMinVid; 484 uint8_t Reserved1[2]; 485 486 // dw18 487 uint16_t BapmVddCBaseLeakageHiSidd; 488 uint16_t BapmVddCBaseLeakageLoSidd; 489 }; 490 491 typedef struct SMU7_Discrete_PmFuses SMU7_Discrete_PmFuses; 492 493 494 #pragma pack(pop) 495 496 #endif 497 498