1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define CG_MULT_THERMAL_STATUS 0x714 28 #define ASIC_MAX_TEMP(x) ((x) << 0) 29 #define ASIC_MAX_TEMP_MASK 0x000001ff 30 #define ASIC_MAX_TEMP_SHIFT 0 31 #define CTF_TEMP(x) ((x) << 9) 32 #define CTF_TEMP_MASK 0x0003fe00 33 #define CTF_TEMP_SHIFT 9 34 35 #define SI_MAX_SH_GPRS 256 36 #define SI_MAX_TEMP_GPRS 16 37 #define SI_MAX_SH_THREADS 256 38 #define SI_MAX_SH_STACK_ENTRIES 4096 39 #define SI_MAX_FRC_EOV_CNT 16384 40 #define SI_MAX_BACKENDS 8 41 #define SI_MAX_BACKENDS_MASK 0xFF 42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 43 #define SI_MAX_SIMDS 12 44 #define SI_MAX_SIMDS_MASK 0x0FFF 45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 46 #define SI_MAX_PIPES 8 47 #define SI_MAX_PIPES_MASK 0xFF 48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 49 #define SI_MAX_LDS_NUM 0xFFFF 50 #define SI_MAX_TCC 16 51 #define SI_MAX_TCC_MASK 0xFFFF 52 53 #define VGA_HDP_CONTROL 0x328 54 #define VGA_MEMORY_DISABLE (1 << 4) 55 56 #define DMIF_ADDR_CONFIG 0xBD4 57 58 #define SRBM_STATUS 0xE50 59 60 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 61 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 62 63 #define VM_L2_CNTL 0x1400 64 #define ENABLE_L2_CACHE (1 << 0) 65 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 66 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 67 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 68 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 69 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 70 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 71 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 72 #define VM_L2_CNTL2 0x1404 73 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 74 #define INVALIDATE_L2_CACHE (1 << 1) 75 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 76 #define INVALIDATE_PTE_AND_PDE_CACHES 0 77 #define INVALIDATE_ONLY_PTE_CACHES 1 78 #define INVALIDATE_ONLY_PDE_CACHES 2 79 #define VM_L2_CNTL3 0x1408 80 #define BANK_SELECT(x) ((x) << 0) 81 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 82 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 83 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 84 #define VM_L2_STATUS 0x140C 85 #define L2_BUSY (1 << 0) 86 #define VM_CONTEXT0_CNTL 0x1410 87 #define ENABLE_CONTEXT (1 << 0) 88 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 89 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 90 #define VM_CONTEXT1_CNTL 0x1414 91 #define VM_CONTEXT0_CNTL2 0x1430 92 #define VM_CONTEXT1_CNTL2 0x1434 93 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 94 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 95 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 96 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 97 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 98 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 99 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 100 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 101 102 #define VM_INVALIDATE_REQUEST 0x1478 103 #define VM_INVALIDATE_RESPONSE 0x147c 104 105 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 106 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 107 108 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 109 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 110 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 111 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 112 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 113 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 114 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 115 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 116 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 117 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 118 119 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 120 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 121 122 #define MC_SHARED_CHMAP 0x2004 123 #define NOOFCHAN_SHIFT 12 124 #define NOOFCHAN_MASK 0x0000f000 125 #define MC_SHARED_CHREMAP 0x2008 126 127 #define MC_VM_FB_LOCATION 0x2024 128 #define MC_VM_AGP_TOP 0x2028 129 #define MC_VM_AGP_BOT 0x202C 130 #define MC_VM_AGP_BASE 0x2030 131 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 132 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 133 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 134 135 #define MC_VM_MX_L1_TLB_CNTL 0x2064 136 #define ENABLE_L1_TLB (1 << 0) 137 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 138 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 139 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 140 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 141 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 142 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 143 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 144 145 #define MC_ARB_RAMCFG 0x2760 146 #define NOOFBANK_SHIFT 0 147 #define NOOFBANK_MASK 0x00000003 148 #define NOOFRANK_SHIFT 2 149 #define NOOFRANK_MASK 0x00000004 150 #define NOOFROWS_SHIFT 3 151 #define NOOFROWS_MASK 0x00000038 152 #define NOOFCOLS_SHIFT 6 153 #define NOOFCOLS_MASK 0x000000C0 154 #define CHANSIZE_SHIFT 8 155 #define CHANSIZE_MASK 0x00000100 156 #define CHANSIZE_OVERRIDE (1 << 11) 157 #define NOOFGROUPS_SHIFT 12 158 #define NOOFGROUPS_MASK 0x00001000 159 160 #define HDP_HOST_PATH_CNTL 0x2C00 161 #define HDP_NONSURFACE_BASE 0x2C04 162 #define HDP_NONSURFACE_INFO 0x2C08 163 #define HDP_NONSURFACE_SIZE 0x2C0C 164 165 #define HDP_ADDR_CONFIG 0x2F48 166 #define HDP_MISC_CNTL 0x2F4C 167 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 168 169 #define CONFIG_MEMSIZE 0x5428 170 171 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 172 173 #define BIF_FB_EN 0x5490 174 #define FB_READ_EN (1 << 0) 175 #define FB_WRITE_EN (1 << 1) 176 177 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 178 179 #define DC_LB_MEMORY_SPLIT 0x6b0c 180 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 181 182 #define PRIORITY_A_CNT 0x6b18 183 #define PRIORITY_MARK_MASK 0x7fff 184 #define PRIORITY_OFF (1 << 16) 185 #define PRIORITY_ALWAYS_ON (1 << 20) 186 #define PRIORITY_B_CNT 0x6b1c 187 188 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 189 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 190 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 191 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 192 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 193 194 #define GRBM_CNTL 0x8000 195 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 196 197 #define GRBM_STATUS2 0x8008 198 #define RLC_RQ_PENDING (1 << 0) 199 #define RLC_BUSY (1 << 8) 200 #define TC_BUSY (1 << 9) 201 202 #define GRBM_STATUS 0x8010 203 #define CMDFIFO_AVAIL_MASK 0x0000000F 204 #define RING2_RQ_PENDING (1 << 4) 205 #define SRBM_RQ_PENDING (1 << 5) 206 #define RING1_RQ_PENDING (1 << 6) 207 #define CF_RQ_PENDING (1 << 7) 208 #define PF_RQ_PENDING (1 << 8) 209 #define GDS_DMA_RQ_PENDING (1 << 9) 210 #define GRBM_EE_BUSY (1 << 10) 211 #define DB_CLEAN (1 << 12) 212 #define CB_CLEAN (1 << 13) 213 #define TA_BUSY (1 << 14) 214 #define GDS_BUSY (1 << 15) 215 #define VGT_BUSY (1 << 17) 216 #define IA_BUSY_NO_DMA (1 << 18) 217 #define IA_BUSY (1 << 19) 218 #define SX_BUSY (1 << 20) 219 #define SPI_BUSY (1 << 22) 220 #define BCI_BUSY (1 << 23) 221 #define SC_BUSY (1 << 24) 222 #define PA_BUSY (1 << 25) 223 #define DB_BUSY (1 << 26) 224 #define CP_COHERENCY_BUSY (1 << 28) 225 #define CP_BUSY (1 << 29) 226 #define CB_BUSY (1 << 30) 227 #define GUI_ACTIVE (1 << 31) 228 #define GRBM_STATUS_SE0 0x8014 229 #define GRBM_STATUS_SE1 0x8018 230 #define SE_DB_CLEAN (1 << 1) 231 #define SE_CB_CLEAN (1 << 2) 232 #define SE_BCI_BUSY (1 << 22) 233 #define SE_VGT_BUSY (1 << 23) 234 #define SE_PA_BUSY (1 << 24) 235 #define SE_TA_BUSY (1 << 25) 236 #define SE_SX_BUSY (1 << 26) 237 #define SE_SPI_BUSY (1 << 27) 238 #define SE_SC_BUSY (1 << 29) 239 #define SE_DB_BUSY (1 << 30) 240 #define SE_CB_BUSY (1 << 31) 241 242 #define GRBM_SOFT_RESET 0x8020 243 #define SOFT_RESET_CP (1 << 0) 244 #define SOFT_RESET_CB (1 << 1) 245 #define SOFT_RESET_RLC (1 << 2) 246 #define SOFT_RESET_DB (1 << 3) 247 #define SOFT_RESET_GDS (1 << 4) 248 #define SOFT_RESET_PA (1 << 5) 249 #define SOFT_RESET_SC (1 << 6) 250 #define SOFT_RESET_BCI (1 << 7) 251 #define SOFT_RESET_SPI (1 << 8) 252 #define SOFT_RESET_SX (1 << 10) 253 #define SOFT_RESET_TC (1 << 11) 254 #define SOFT_RESET_TA (1 << 12) 255 #define SOFT_RESET_VGT (1 << 14) 256 #define SOFT_RESET_IA (1 << 15) 257 258 #define CP_ME_CNTL 0x86D8 259 #define CP_CE_HALT (1 << 24) 260 #define CP_PFP_HALT (1 << 26) 261 #define CP_ME_HALT (1 << 28) 262 263 #define CP_RB0_RPTR 0x8700 264 265 #define CP_QUEUE_THRESHOLDS 0x8760 266 #define ROQ_IB1_START(x) ((x) << 0) 267 #define ROQ_IB2_START(x) ((x) << 8) 268 #define CP_MEQ_THRESHOLDS 0x8764 269 #define MEQ1_START(x) ((x) << 0) 270 #define MEQ2_START(x) ((x) << 8) 271 272 #define CP_PERFMON_CNTL 0x87FC 273 274 #define VGT_CACHE_INVALIDATION 0x88C4 275 #define CACHE_INVALIDATION(x) ((x) << 0) 276 #define VC_ONLY 0 277 #define TC_ONLY 1 278 #define VC_AND_TC 2 279 #define AUTO_INVLD_EN(x) ((x) << 6) 280 #define NO_AUTO 0 281 #define ES_AUTO 1 282 #define GS_AUTO 2 283 #define ES_AND_GS_AUTO 3 284 285 #define VGT_GS_VERTEX_REUSE 0x88D4 286 287 #define VGT_NUM_INSTANCES 0x8974 288 289 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 290 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 291 292 #define PA_CL_ENHANCE 0x8A14 293 #define CLIP_VTX_REORDER_ENA (1 << 0) 294 #define NUM_CLIP_SEQ(x) ((x) << 1) 295 296 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 297 298 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 299 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 300 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 301 302 #define PA_SC_FIFO_SIZE 0x8BCC 303 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 304 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 305 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 306 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 307 308 #define SQ_CONFIG 0x8C00 309 310 #define SX_DEBUG_1 0x9060 311 312 #define SPI_CONFIG_CNTL_1 0x913C 313 #define VTX_DONE_DELAY(x) ((x) << 0) 314 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 315 316 #define CGTS_TCC_DISABLE 0x9148 317 #define CGTS_USER_TCC_DISABLE 0x914C 318 #define TCC_DISABLE_MASK 0xFFFF0000 319 #define TCC_DISABLE_SHIFT 16 320 321 #define CC_RB_BACKEND_DISABLE 0x98F4 322 #define BACKEND_DISABLE(x) ((x) << 16) 323 #define GB_ADDR_CONFIG 0x98F8 324 #define NUM_PIPES(x) ((x) << 0) 325 #define NUM_PIPES_MASK 0x00000007 326 #define NUM_PIPES_SHIFT 0 327 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 328 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 329 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 330 #define NUM_SHADER_ENGINES(x) ((x) << 12) 331 #define NUM_SHADER_ENGINES_MASK 0x00003000 332 #define NUM_SHADER_ENGINES_SHIFT 12 333 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 334 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 335 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 336 #define NUM_GPUS(x) ((x) << 20) 337 #define NUM_GPUS_MASK 0x00700000 338 #define NUM_GPUS_SHIFT 20 339 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 340 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 341 #define MULTI_GPU_TILE_SIZE_SHIFT 24 342 #define ROW_SIZE(x) ((x) << 28) 343 #define ROW_SIZE_MASK 0x30000000 344 #define ROW_SIZE_SHIFT 28 345 346 #define GB_TILE_MODE0 0x9910 347 # define MICRO_TILE_MODE(x) ((x) << 0) 348 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 349 # define ADDR_SURF_THIN_MICRO_TILING 1 350 # define ADDR_SURF_DEPTH_MICRO_TILING 2 351 # define ARRAY_MODE(x) ((x) << 2) 352 # define ARRAY_LINEAR_GENERAL 0 353 # define ARRAY_LINEAR_ALIGNED 1 354 # define ARRAY_1D_TILED_THIN1 2 355 # define ARRAY_2D_TILED_THIN1 4 356 # define PIPE_CONFIG(x) ((x) << 6) 357 # define ADDR_SURF_P2 0 358 # define ADDR_SURF_P4_8x16 4 359 # define ADDR_SURF_P4_16x16 5 360 # define ADDR_SURF_P4_16x32 6 361 # define ADDR_SURF_P4_32x32 7 362 # define ADDR_SURF_P8_16x16_8x16 8 363 # define ADDR_SURF_P8_16x32_8x16 9 364 # define ADDR_SURF_P8_32x32_8x16 10 365 # define ADDR_SURF_P8_16x32_16x16 11 366 # define ADDR_SURF_P8_32x32_16x16 12 367 # define ADDR_SURF_P8_32x32_16x32 13 368 # define ADDR_SURF_P8_32x64_32x32 14 369 # define TILE_SPLIT(x) ((x) << 11) 370 # define ADDR_SURF_TILE_SPLIT_64B 0 371 # define ADDR_SURF_TILE_SPLIT_128B 1 372 # define ADDR_SURF_TILE_SPLIT_256B 2 373 # define ADDR_SURF_TILE_SPLIT_512B 3 374 # define ADDR_SURF_TILE_SPLIT_1KB 4 375 # define ADDR_SURF_TILE_SPLIT_2KB 5 376 # define ADDR_SURF_TILE_SPLIT_4KB 6 377 # define BANK_WIDTH(x) ((x) << 14) 378 # define ADDR_SURF_BANK_WIDTH_1 0 379 # define ADDR_SURF_BANK_WIDTH_2 1 380 # define ADDR_SURF_BANK_WIDTH_4 2 381 # define ADDR_SURF_BANK_WIDTH_8 3 382 # define BANK_HEIGHT(x) ((x) << 16) 383 # define ADDR_SURF_BANK_HEIGHT_1 0 384 # define ADDR_SURF_BANK_HEIGHT_2 1 385 # define ADDR_SURF_BANK_HEIGHT_4 2 386 # define ADDR_SURF_BANK_HEIGHT_8 3 387 # define MACRO_TILE_ASPECT(x) ((x) << 18) 388 # define ADDR_SURF_MACRO_ASPECT_1 0 389 # define ADDR_SURF_MACRO_ASPECT_2 1 390 # define ADDR_SURF_MACRO_ASPECT_4 2 391 # define ADDR_SURF_MACRO_ASPECT_8 3 392 # define NUM_BANKS(x) ((x) << 20) 393 # define ADDR_SURF_2_BANK 0 394 # define ADDR_SURF_4_BANK 1 395 # define ADDR_SURF_8_BANK 2 396 # define ADDR_SURF_16_BANK 3 397 398 #define CB_PERFCOUNTER0_SELECT0 0x9a20 399 #define CB_PERFCOUNTER0_SELECT1 0x9a24 400 #define CB_PERFCOUNTER1_SELECT0 0x9a28 401 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 402 #define CB_PERFCOUNTER2_SELECT0 0x9a30 403 #define CB_PERFCOUNTER2_SELECT1 0x9a34 404 #define CB_PERFCOUNTER3_SELECT0 0x9a38 405 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 406 407 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 408 #define BACKEND_DISABLE_MASK 0x00FF0000 409 #define BACKEND_DISABLE_SHIFT 16 410 411 #define TCP_CHAN_STEER_LO 0xac0c 412 #define TCP_CHAN_STEER_HI 0xac10 413 414 /* 415 * PM4 416 */ 417 #define PACKET_TYPE0 0 418 #define PACKET_TYPE1 1 419 #define PACKET_TYPE2 2 420 #define PACKET_TYPE3 3 421 422 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 423 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 424 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 425 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 426 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 427 (((reg) >> 2) & 0xFFFF) | \ 428 ((n) & 0x3FFF) << 16) 429 #define CP_PACKET2 0x80000000 430 #define PACKET2_PAD_SHIFT 0 431 #define PACKET2_PAD_MASK (0x3fffffff << 0) 432 433 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 434 435 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 436 (((op) & 0xFF) << 8) | \ 437 ((n) & 0x3FFF) << 16) 438 439 /* Packet 3 types */ 440 #define PACKET3_NOP 0x10 441 #define PACKET3_SET_BASE 0x11 442 #define PACKET3_BASE_INDEX(x) ((x) << 0) 443 #define GDS_PARTITION_BASE 2 444 #define CE_PARTITION_BASE 3 445 #define PACKET3_CLEAR_STATE 0x12 446 #define PACKET3_INDEX_BUFFER_SIZE 0x13 447 #define PACKET3_DISPATCH_DIRECT 0x15 448 #define PACKET3_DISPATCH_INDIRECT 0x16 449 #define PACKET3_ALLOC_GDS 0x1B 450 #define PACKET3_WRITE_GDS_RAM 0x1C 451 #define PACKET3_ATOMIC_GDS 0x1D 452 #define PACKET3_ATOMIC 0x1E 453 #define PACKET3_OCCLUSION_QUERY 0x1F 454 #define PACKET3_SET_PREDICATION 0x20 455 #define PACKET3_REG_RMW 0x21 456 #define PACKET3_COND_EXEC 0x22 457 #define PACKET3_PRED_EXEC 0x23 458 #define PACKET3_DRAW_INDIRECT 0x24 459 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 460 #define PACKET3_INDEX_BASE 0x26 461 #define PACKET3_DRAW_INDEX_2 0x27 462 #define PACKET3_CONTEXT_CONTROL 0x28 463 #define PACKET3_INDEX_TYPE 0x2A 464 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 465 #define PACKET3_DRAW_INDEX_AUTO 0x2D 466 #define PACKET3_DRAW_INDEX_IMMD 0x2E 467 #define PACKET3_NUM_INSTANCES 0x2F 468 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 469 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 470 #define PACKET3_INDIRECT_BUFFER 0x32 471 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 472 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 473 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 474 #define PACKET3_WRITE_DATA 0x37 475 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 476 #define PACKET3_MEM_SEMAPHORE 0x39 477 #define PACKET3_MPEG_INDEX 0x3A 478 #define PACKET3_COPY_DW 0x3B 479 #define PACKET3_WAIT_REG_MEM 0x3C 480 #define PACKET3_MEM_WRITE 0x3D 481 #define PACKET3_COPY_DATA 0x40 482 #define PACKET3_PFP_SYNC_ME 0x42 483 #define PACKET3_SURFACE_SYNC 0x43 484 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 485 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 486 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 487 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 488 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 489 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 490 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 491 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 492 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 493 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 494 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 495 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 496 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 497 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 498 # define PACKET3_TC_ACTION_ENA (1 << 23) 499 # define PACKET3_CB_ACTION_ENA (1 << 25) 500 # define PACKET3_DB_ACTION_ENA (1 << 26) 501 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 502 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 503 #define PACKET3_ME_INITIALIZE 0x44 504 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 505 #define PACKET3_COND_WRITE 0x45 506 #define PACKET3_EVENT_WRITE 0x46 507 #define PACKET3_EVENT_WRITE_EOP 0x47 508 #define PACKET3_EVENT_WRITE_EOS 0x48 509 #define PACKET3_PREAMBLE_CNTL 0x4A 510 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 511 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 512 #define PACKET3_ONE_REG_WRITE 0x57 513 #define PACKET3_LOAD_CONFIG_REG 0x5F 514 #define PACKET3_LOAD_CONTEXT_REG 0x60 515 #define PACKET3_LOAD_SH_REG 0x61 516 #define PACKET3_SET_CONFIG_REG 0x68 517 #define PACKET3_SET_CONFIG_REG_START 0x00008000 518 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 519 #define PACKET3_SET_CONTEXT_REG 0x69 520 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 521 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 522 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 523 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 524 #define PACKET3_SET_SH_REG 0x76 525 #define PACKET3_SET_SH_REG_START 0x0000b000 526 #define PACKET3_SET_SH_REG_END 0x0000c000 527 #define PACKET3_SET_SH_REG_OFFSET 0x77 528 #define PACKET3_ME_WRITE 0x7A 529 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 530 #define PACKET3_SCRATCH_RAM_READ 0x7E 531 #define PACKET3_CE_WRITE 0x7F 532 #define PACKET3_LOAD_CONST_RAM 0x80 533 #define PACKET3_WRITE_CONST_RAM 0x81 534 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 535 #define PACKET3_DUMP_CONST_RAM 0x83 536 #define PACKET3_INCREMENT_CE_COUNTER 0x84 537 #define PACKET3_INCREMENT_DE_COUNTER 0x85 538 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 539 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 540 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 541 #define PACKET3_SET_CE_DE_COUNTERS 0x89 542 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 543 544 #endif 545