1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 28 29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 31 32 #define CG_MULT_THERMAL_STATUS 0x714 33 #define ASIC_MAX_TEMP(x) ((x) << 0) 34 #define ASIC_MAX_TEMP_MASK 0x000001ff 35 #define ASIC_MAX_TEMP_SHIFT 0 36 #define CTF_TEMP(x) ((x) << 9) 37 #define CTF_TEMP_MASK 0x0003fe00 38 #define CTF_TEMP_SHIFT 9 39 40 #define SI_MAX_SH_GPRS 256 41 #define SI_MAX_TEMP_GPRS 16 42 #define SI_MAX_SH_THREADS 256 43 #define SI_MAX_SH_STACK_ENTRIES 4096 44 #define SI_MAX_FRC_EOV_CNT 16384 45 #define SI_MAX_BACKENDS 8 46 #define SI_MAX_BACKENDS_MASK 0xFF 47 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 48 #define SI_MAX_SIMDS 12 49 #define SI_MAX_SIMDS_MASK 0x0FFF 50 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 51 #define SI_MAX_PIPES 8 52 #define SI_MAX_PIPES_MASK 0xFF 53 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 54 #define SI_MAX_LDS_NUM 0xFFFF 55 #define SI_MAX_TCC 16 56 #define SI_MAX_TCC_MASK 0xFFFF 57 58 #define VGA_HDP_CONTROL 0x328 59 #define VGA_MEMORY_DISABLE (1 << 4) 60 61 #define DMIF_ADDR_CONFIG 0xBD4 62 63 #define SRBM_STATUS 0xE50 64 65 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 66 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 67 68 #define VM_L2_CNTL 0x1400 69 #define ENABLE_L2_CACHE (1 << 0) 70 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 71 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 72 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 73 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 74 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 75 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 76 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 77 #define VM_L2_CNTL2 0x1404 78 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 79 #define INVALIDATE_L2_CACHE (1 << 1) 80 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 81 #define INVALIDATE_PTE_AND_PDE_CACHES 0 82 #define INVALIDATE_ONLY_PTE_CACHES 1 83 #define INVALIDATE_ONLY_PDE_CACHES 2 84 #define VM_L2_CNTL3 0x1408 85 #define BANK_SELECT(x) ((x) << 0) 86 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 87 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 88 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 89 #define VM_L2_STATUS 0x140C 90 #define L2_BUSY (1 << 0) 91 #define VM_CONTEXT0_CNTL 0x1410 92 #define ENABLE_CONTEXT (1 << 0) 93 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 94 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 95 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 96 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 97 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 98 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 99 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 100 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 101 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 102 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 103 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 104 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 105 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 106 #define VM_CONTEXT1_CNTL 0x1414 107 #define VM_CONTEXT0_CNTL2 0x1430 108 #define VM_CONTEXT1_CNTL2 0x1434 109 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 110 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 111 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 112 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 113 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 114 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 115 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 116 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 117 118 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 119 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 120 121 #define VM_INVALIDATE_REQUEST 0x1478 122 #define VM_INVALIDATE_RESPONSE 0x147c 123 124 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 125 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 126 127 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 128 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 129 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 130 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 131 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 132 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 133 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 134 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 135 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 136 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 137 138 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 139 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 140 141 #define MC_SHARED_CHMAP 0x2004 142 #define NOOFCHAN_SHIFT 12 143 #define NOOFCHAN_MASK 0x0000f000 144 #define MC_SHARED_CHREMAP 0x2008 145 146 #define MC_VM_FB_LOCATION 0x2024 147 #define MC_VM_AGP_TOP 0x2028 148 #define MC_VM_AGP_BOT 0x202C 149 #define MC_VM_AGP_BASE 0x2030 150 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 151 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 152 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 153 154 #define MC_VM_MX_L1_TLB_CNTL 0x2064 155 #define ENABLE_L1_TLB (1 << 0) 156 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 157 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 158 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 159 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 160 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 161 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 162 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 163 164 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 165 166 #define MC_ARB_RAMCFG 0x2760 167 #define NOOFBANK_SHIFT 0 168 #define NOOFBANK_MASK 0x00000003 169 #define NOOFRANK_SHIFT 2 170 #define NOOFRANK_MASK 0x00000004 171 #define NOOFROWS_SHIFT 3 172 #define NOOFROWS_MASK 0x00000038 173 #define NOOFCOLS_SHIFT 6 174 #define NOOFCOLS_MASK 0x000000C0 175 #define CHANSIZE_SHIFT 8 176 #define CHANSIZE_MASK 0x00000100 177 #define CHANSIZE_OVERRIDE (1 << 11) 178 #define NOOFGROUPS_SHIFT 12 179 #define NOOFGROUPS_MASK 0x00001000 180 181 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 182 #define TRAIN_DONE_D0 (1 << 30) 183 #define TRAIN_DONE_D1 (1 << 31) 184 185 #define MC_SEQ_SUP_CNTL 0x28c8 186 #define RUN_MASK (1 << 0) 187 #define MC_SEQ_SUP_PGM 0x28cc 188 189 #define MC_IO_PAD_CNTL_D0 0x29d0 190 #define MEM_FALL_OUT_CMD (1 << 8) 191 192 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 193 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 194 195 #define HDP_HOST_PATH_CNTL 0x2C00 196 #define HDP_NONSURFACE_BASE 0x2C04 197 #define HDP_NONSURFACE_INFO 0x2C08 198 #define HDP_NONSURFACE_SIZE 0x2C0C 199 200 #define HDP_ADDR_CONFIG 0x2F48 201 #define HDP_MISC_CNTL 0x2F4C 202 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 203 204 #define IH_RB_CNTL 0x3e00 205 # define IH_RB_ENABLE (1 << 0) 206 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 207 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 208 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 209 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 210 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 211 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 212 #define IH_RB_BASE 0x3e04 213 #define IH_RB_RPTR 0x3e08 214 #define IH_RB_WPTR 0x3e0c 215 # define RB_OVERFLOW (1 << 0) 216 # define WPTR_OFFSET_MASK 0x3fffc 217 #define IH_RB_WPTR_ADDR_HI 0x3e10 218 #define IH_RB_WPTR_ADDR_LO 0x3e14 219 #define IH_CNTL 0x3e18 220 # define ENABLE_INTR (1 << 0) 221 # define IH_MC_SWAP(x) ((x) << 1) 222 # define IH_MC_SWAP_NONE 0 223 # define IH_MC_SWAP_16BIT 1 224 # define IH_MC_SWAP_32BIT 2 225 # define IH_MC_SWAP_64BIT 3 226 # define RPTR_REARM (1 << 4) 227 # define MC_WRREQ_CREDIT(x) ((x) << 15) 228 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 229 # define MC_VMID(x) ((x) << 25) 230 231 #define CONFIG_MEMSIZE 0x5428 232 233 #define INTERRUPT_CNTL 0x5468 234 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 235 # define IH_DUMMY_RD_EN (1 << 1) 236 # define IH_REQ_NONSNOOP_EN (1 << 3) 237 # define GEN_IH_INT_EN (1 << 8) 238 #define INTERRUPT_CNTL2 0x546c 239 240 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 241 242 #define BIF_FB_EN 0x5490 243 #define FB_READ_EN (1 << 0) 244 #define FB_WRITE_EN (1 << 1) 245 246 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 247 248 #define DC_LB_MEMORY_SPLIT 0x6b0c 249 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 250 251 #define PRIORITY_A_CNT 0x6b18 252 #define PRIORITY_MARK_MASK 0x7fff 253 #define PRIORITY_OFF (1 << 16) 254 #define PRIORITY_ALWAYS_ON (1 << 20) 255 #define PRIORITY_B_CNT 0x6b1c 256 257 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 258 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 259 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 260 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 261 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 262 263 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 264 #define VLINE_STATUS 0x6bb8 265 # define VLINE_OCCURRED (1 << 0) 266 # define VLINE_ACK (1 << 4) 267 # define VLINE_STAT (1 << 12) 268 # define VLINE_INTERRUPT (1 << 16) 269 # define VLINE_INTERRUPT_TYPE (1 << 17) 270 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 271 #define VBLANK_STATUS 0x6bbc 272 # define VBLANK_OCCURRED (1 << 0) 273 # define VBLANK_ACK (1 << 4) 274 # define VBLANK_STAT (1 << 12) 275 # define VBLANK_INTERRUPT (1 << 16) 276 # define VBLANK_INTERRUPT_TYPE (1 << 17) 277 278 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 279 #define INT_MASK 0x6b40 280 # define VBLANK_INT_MASK (1 << 0) 281 # define VLINE_INT_MASK (1 << 4) 282 283 #define DISP_INTERRUPT_STATUS 0x60f4 284 # define LB_D1_VLINE_INTERRUPT (1 << 2) 285 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 286 # define DC_HPD1_INTERRUPT (1 << 17) 287 # define DC_HPD1_RX_INTERRUPT (1 << 18) 288 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 289 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 290 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 291 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 292 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 293 # define LB_D2_VLINE_INTERRUPT (1 << 2) 294 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 295 # define DC_HPD2_INTERRUPT (1 << 17) 296 # define DC_HPD2_RX_INTERRUPT (1 << 18) 297 # define DISP_TIMER_INTERRUPT (1 << 24) 298 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 299 # define LB_D3_VLINE_INTERRUPT (1 << 2) 300 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 301 # define DC_HPD3_INTERRUPT (1 << 17) 302 # define DC_HPD3_RX_INTERRUPT (1 << 18) 303 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 304 # define LB_D4_VLINE_INTERRUPT (1 << 2) 305 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 306 # define DC_HPD4_INTERRUPT (1 << 17) 307 # define DC_HPD4_RX_INTERRUPT (1 << 18) 308 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 309 # define LB_D5_VLINE_INTERRUPT (1 << 2) 310 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 311 # define DC_HPD5_INTERRUPT (1 << 17) 312 # define DC_HPD5_RX_INTERRUPT (1 << 18) 313 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 314 # define LB_D6_VLINE_INTERRUPT (1 << 2) 315 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 316 # define DC_HPD6_INTERRUPT (1 << 17) 317 # define DC_HPD6_RX_INTERRUPT (1 << 18) 318 319 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 320 #define GRPH_INT_STATUS 0x6858 321 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 322 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 323 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 324 #define GRPH_INT_CONTROL 0x685c 325 # define GRPH_PFLIP_INT_MASK (1 << 0) 326 # define GRPH_PFLIP_INT_TYPE (1 << 8) 327 328 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 329 330 #define DC_HPD1_INT_STATUS 0x601c 331 #define DC_HPD2_INT_STATUS 0x6028 332 #define DC_HPD3_INT_STATUS 0x6034 333 #define DC_HPD4_INT_STATUS 0x6040 334 #define DC_HPD5_INT_STATUS 0x604c 335 #define DC_HPD6_INT_STATUS 0x6058 336 # define DC_HPDx_INT_STATUS (1 << 0) 337 # define DC_HPDx_SENSE (1 << 1) 338 # define DC_HPDx_RX_INT_STATUS (1 << 8) 339 340 #define DC_HPD1_INT_CONTROL 0x6020 341 #define DC_HPD2_INT_CONTROL 0x602c 342 #define DC_HPD3_INT_CONTROL 0x6038 343 #define DC_HPD4_INT_CONTROL 0x6044 344 #define DC_HPD5_INT_CONTROL 0x6050 345 #define DC_HPD6_INT_CONTROL 0x605c 346 # define DC_HPDx_INT_ACK (1 << 0) 347 # define DC_HPDx_INT_POLARITY (1 << 8) 348 # define DC_HPDx_INT_EN (1 << 16) 349 # define DC_HPDx_RX_INT_ACK (1 << 20) 350 # define DC_HPDx_RX_INT_EN (1 << 24) 351 352 #define DC_HPD1_CONTROL 0x6024 353 #define DC_HPD2_CONTROL 0x6030 354 #define DC_HPD3_CONTROL 0x603c 355 #define DC_HPD4_CONTROL 0x6048 356 #define DC_HPD5_CONTROL 0x6054 357 #define DC_HPD6_CONTROL 0x6060 358 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 359 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 360 # define DC_HPDx_EN (1 << 28) 361 362 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 363 #define CRTC_STATUS_FRAME_COUNT 0x6e98 364 365 #define GRBM_CNTL 0x8000 366 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 367 368 #define GRBM_STATUS2 0x8008 369 #define RLC_RQ_PENDING (1 << 0) 370 #define RLC_BUSY (1 << 8) 371 #define TC_BUSY (1 << 9) 372 373 #define GRBM_STATUS 0x8010 374 #define CMDFIFO_AVAIL_MASK 0x0000000F 375 #define RING2_RQ_PENDING (1 << 4) 376 #define SRBM_RQ_PENDING (1 << 5) 377 #define RING1_RQ_PENDING (1 << 6) 378 #define CF_RQ_PENDING (1 << 7) 379 #define PF_RQ_PENDING (1 << 8) 380 #define GDS_DMA_RQ_PENDING (1 << 9) 381 #define GRBM_EE_BUSY (1 << 10) 382 #define DB_CLEAN (1 << 12) 383 #define CB_CLEAN (1 << 13) 384 #define TA_BUSY (1 << 14) 385 #define GDS_BUSY (1 << 15) 386 #define VGT_BUSY (1 << 17) 387 #define IA_BUSY_NO_DMA (1 << 18) 388 #define IA_BUSY (1 << 19) 389 #define SX_BUSY (1 << 20) 390 #define SPI_BUSY (1 << 22) 391 #define BCI_BUSY (1 << 23) 392 #define SC_BUSY (1 << 24) 393 #define PA_BUSY (1 << 25) 394 #define DB_BUSY (1 << 26) 395 #define CP_COHERENCY_BUSY (1 << 28) 396 #define CP_BUSY (1 << 29) 397 #define CB_BUSY (1 << 30) 398 #define GUI_ACTIVE (1 << 31) 399 #define GRBM_STATUS_SE0 0x8014 400 #define GRBM_STATUS_SE1 0x8018 401 #define SE_DB_CLEAN (1 << 1) 402 #define SE_CB_CLEAN (1 << 2) 403 #define SE_BCI_BUSY (1 << 22) 404 #define SE_VGT_BUSY (1 << 23) 405 #define SE_PA_BUSY (1 << 24) 406 #define SE_TA_BUSY (1 << 25) 407 #define SE_SX_BUSY (1 << 26) 408 #define SE_SPI_BUSY (1 << 27) 409 #define SE_SC_BUSY (1 << 29) 410 #define SE_DB_BUSY (1 << 30) 411 #define SE_CB_BUSY (1 << 31) 412 413 #define GRBM_SOFT_RESET 0x8020 414 #define SOFT_RESET_CP (1 << 0) 415 #define SOFT_RESET_CB (1 << 1) 416 #define SOFT_RESET_RLC (1 << 2) 417 #define SOFT_RESET_DB (1 << 3) 418 #define SOFT_RESET_GDS (1 << 4) 419 #define SOFT_RESET_PA (1 << 5) 420 #define SOFT_RESET_SC (1 << 6) 421 #define SOFT_RESET_BCI (1 << 7) 422 #define SOFT_RESET_SPI (1 << 8) 423 #define SOFT_RESET_SX (1 << 10) 424 #define SOFT_RESET_TC (1 << 11) 425 #define SOFT_RESET_TA (1 << 12) 426 #define SOFT_RESET_VGT (1 << 14) 427 #define SOFT_RESET_IA (1 << 15) 428 429 #define GRBM_GFX_INDEX 0x802C 430 #define INSTANCE_INDEX(x) ((x) << 0) 431 #define SH_INDEX(x) ((x) << 8) 432 #define SE_INDEX(x) ((x) << 16) 433 #define SH_BROADCAST_WRITES (1 << 29) 434 #define INSTANCE_BROADCAST_WRITES (1 << 30) 435 #define SE_BROADCAST_WRITES (1 << 31) 436 437 #define GRBM_INT_CNTL 0x8060 438 # define RDERR_INT_ENABLE (1 << 0) 439 # define GUI_IDLE_INT_ENABLE (1 << 19) 440 441 #define CP_STRMOUT_CNTL 0x84FC 442 #define SCRATCH_REG0 0x8500 443 #define SCRATCH_REG1 0x8504 444 #define SCRATCH_REG2 0x8508 445 #define SCRATCH_REG3 0x850C 446 #define SCRATCH_REG4 0x8510 447 #define SCRATCH_REG5 0x8514 448 #define SCRATCH_REG6 0x8518 449 #define SCRATCH_REG7 0x851C 450 451 #define SCRATCH_UMSK 0x8540 452 #define SCRATCH_ADDR 0x8544 453 454 #define CP_SEM_WAIT_TIMER 0x85BC 455 456 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 457 458 #define CP_ME_CNTL 0x86D8 459 #define CP_CE_HALT (1 << 24) 460 #define CP_PFP_HALT (1 << 26) 461 #define CP_ME_HALT (1 << 28) 462 463 #define CP_COHER_CNTL2 0x85E8 464 465 #define CP_RB2_RPTR 0x86f8 466 #define CP_RB1_RPTR 0x86fc 467 #define CP_RB0_RPTR 0x8700 468 #define CP_RB_WPTR_DELAY 0x8704 469 470 #define CP_QUEUE_THRESHOLDS 0x8760 471 #define ROQ_IB1_START(x) ((x) << 0) 472 #define ROQ_IB2_START(x) ((x) << 8) 473 #define CP_MEQ_THRESHOLDS 0x8764 474 #define MEQ1_START(x) ((x) << 0) 475 #define MEQ2_START(x) ((x) << 8) 476 477 #define CP_PERFMON_CNTL 0x87FC 478 479 #define VGT_VTX_VECT_EJECT_REG 0x88B0 480 481 #define VGT_CACHE_INVALIDATION 0x88C4 482 #define CACHE_INVALIDATION(x) ((x) << 0) 483 #define VC_ONLY 0 484 #define TC_ONLY 1 485 #define VC_AND_TC 2 486 #define AUTO_INVLD_EN(x) ((x) << 6) 487 #define NO_AUTO 0 488 #define ES_AUTO 1 489 #define GS_AUTO 2 490 #define ES_AND_GS_AUTO 3 491 #define VGT_ESGS_RING_SIZE 0x88C8 492 #define VGT_GSVS_RING_SIZE 0x88CC 493 494 #define VGT_GS_VERTEX_REUSE 0x88D4 495 496 #define VGT_PRIMITIVE_TYPE 0x8958 497 #define VGT_INDEX_TYPE 0x895C 498 499 #define VGT_NUM_INDICES 0x8970 500 #define VGT_NUM_INSTANCES 0x8974 501 502 #define VGT_TF_RING_SIZE 0x8988 503 504 #define VGT_HS_OFFCHIP_PARAM 0x89B0 505 506 #define VGT_TF_MEMORY_BASE 0x89B8 507 508 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 509 #define INACTIVE_CUS_MASK 0xFFFF0000 510 #define INACTIVE_CUS_SHIFT 16 511 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 512 513 #define PA_CL_ENHANCE 0x8A14 514 #define CLIP_VTX_REORDER_ENA (1 << 0) 515 #define NUM_CLIP_SEQ(x) ((x) << 1) 516 517 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 518 519 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 520 521 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 522 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 523 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 524 525 #define PA_SC_FIFO_SIZE 0x8BCC 526 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 527 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 528 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 529 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 530 531 #define PA_SC_ENHANCE 0x8BF0 532 533 #define SQ_CONFIG 0x8C00 534 535 #define SQC_CACHES 0x8C08 536 537 #define SX_DEBUG_1 0x9060 538 539 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 540 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 541 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 542 #define SPI_PS_MAX_WAVE_ID 0x90EC 543 544 #define SPI_CONFIG_CNTL 0x9100 545 546 #define SPI_CONFIG_CNTL_1 0x913C 547 #define VTX_DONE_DELAY(x) ((x) << 0) 548 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 549 550 #define CGTS_TCC_DISABLE 0x9148 551 #define CGTS_USER_TCC_DISABLE 0x914C 552 #define TCC_DISABLE_MASK 0xFFFF0000 553 #define TCC_DISABLE_SHIFT 16 554 555 #define TA_CNTL_AUX 0x9508 556 557 #define CC_RB_BACKEND_DISABLE 0x98F4 558 #define BACKEND_DISABLE(x) ((x) << 16) 559 #define GB_ADDR_CONFIG 0x98F8 560 #define NUM_PIPES(x) ((x) << 0) 561 #define NUM_PIPES_MASK 0x00000007 562 #define NUM_PIPES_SHIFT 0 563 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 564 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 565 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 566 #define NUM_SHADER_ENGINES(x) ((x) << 12) 567 #define NUM_SHADER_ENGINES_MASK 0x00003000 568 #define NUM_SHADER_ENGINES_SHIFT 12 569 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 570 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 571 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 572 #define NUM_GPUS(x) ((x) << 20) 573 #define NUM_GPUS_MASK 0x00700000 574 #define NUM_GPUS_SHIFT 20 575 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 576 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 577 #define MULTI_GPU_TILE_SIZE_SHIFT 24 578 #define ROW_SIZE(x) ((x) << 28) 579 #define ROW_SIZE_MASK 0x30000000 580 #define ROW_SIZE_SHIFT 28 581 582 #define GB_TILE_MODE0 0x9910 583 # define MICRO_TILE_MODE(x) ((x) << 0) 584 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 585 # define ADDR_SURF_THIN_MICRO_TILING 1 586 # define ADDR_SURF_DEPTH_MICRO_TILING 2 587 # define ARRAY_MODE(x) ((x) << 2) 588 # define ARRAY_LINEAR_GENERAL 0 589 # define ARRAY_LINEAR_ALIGNED 1 590 # define ARRAY_1D_TILED_THIN1 2 591 # define ARRAY_2D_TILED_THIN1 4 592 # define PIPE_CONFIG(x) ((x) << 6) 593 # define ADDR_SURF_P2 0 594 # define ADDR_SURF_P4_8x16 4 595 # define ADDR_SURF_P4_16x16 5 596 # define ADDR_SURF_P4_16x32 6 597 # define ADDR_SURF_P4_32x32 7 598 # define ADDR_SURF_P8_16x16_8x16 8 599 # define ADDR_SURF_P8_16x32_8x16 9 600 # define ADDR_SURF_P8_32x32_8x16 10 601 # define ADDR_SURF_P8_16x32_16x16 11 602 # define ADDR_SURF_P8_32x32_16x16 12 603 # define ADDR_SURF_P8_32x32_16x32 13 604 # define ADDR_SURF_P8_32x64_32x32 14 605 # define TILE_SPLIT(x) ((x) << 11) 606 # define ADDR_SURF_TILE_SPLIT_64B 0 607 # define ADDR_SURF_TILE_SPLIT_128B 1 608 # define ADDR_SURF_TILE_SPLIT_256B 2 609 # define ADDR_SURF_TILE_SPLIT_512B 3 610 # define ADDR_SURF_TILE_SPLIT_1KB 4 611 # define ADDR_SURF_TILE_SPLIT_2KB 5 612 # define ADDR_SURF_TILE_SPLIT_4KB 6 613 # define BANK_WIDTH(x) ((x) << 14) 614 # define ADDR_SURF_BANK_WIDTH_1 0 615 # define ADDR_SURF_BANK_WIDTH_2 1 616 # define ADDR_SURF_BANK_WIDTH_4 2 617 # define ADDR_SURF_BANK_WIDTH_8 3 618 # define BANK_HEIGHT(x) ((x) << 16) 619 # define ADDR_SURF_BANK_HEIGHT_1 0 620 # define ADDR_SURF_BANK_HEIGHT_2 1 621 # define ADDR_SURF_BANK_HEIGHT_4 2 622 # define ADDR_SURF_BANK_HEIGHT_8 3 623 # define MACRO_TILE_ASPECT(x) ((x) << 18) 624 # define ADDR_SURF_MACRO_ASPECT_1 0 625 # define ADDR_SURF_MACRO_ASPECT_2 1 626 # define ADDR_SURF_MACRO_ASPECT_4 2 627 # define ADDR_SURF_MACRO_ASPECT_8 3 628 # define NUM_BANKS(x) ((x) << 20) 629 # define ADDR_SURF_2_BANK 0 630 # define ADDR_SURF_4_BANK 1 631 # define ADDR_SURF_8_BANK 2 632 # define ADDR_SURF_16_BANK 3 633 634 #define CB_PERFCOUNTER0_SELECT0 0x9a20 635 #define CB_PERFCOUNTER0_SELECT1 0x9a24 636 #define CB_PERFCOUNTER1_SELECT0 0x9a28 637 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 638 #define CB_PERFCOUNTER2_SELECT0 0x9a30 639 #define CB_PERFCOUNTER2_SELECT1 0x9a34 640 #define CB_PERFCOUNTER3_SELECT0 0x9a38 641 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 642 643 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 644 #define BACKEND_DISABLE_MASK 0x00FF0000 645 #define BACKEND_DISABLE_SHIFT 16 646 647 #define TCP_CHAN_STEER_LO 0xac0c 648 #define TCP_CHAN_STEER_HI 0xac10 649 650 #define CP_RB0_BASE 0xC100 651 #define CP_RB0_CNTL 0xC104 652 #define RB_BUFSZ(x) ((x) << 0) 653 #define RB_BLKSZ(x) ((x) << 8) 654 #define BUF_SWAP_32BIT (2 << 16) 655 #define RB_NO_UPDATE (1 << 27) 656 #define RB_RPTR_WR_ENA (1 << 31) 657 658 #define CP_RB0_RPTR_ADDR 0xC10C 659 #define CP_RB0_RPTR_ADDR_HI 0xC110 660 #define CP_RB0_WPTR 0xC114 661 662 #define CP_PFP_UCODE_ADDR 0xC150 663 #define CP_PFP_UCODE_DATA 0xC154 664 #define CP_ME_RAM_RADDR 0xC158 665 #define CP_ME_RAM_WADDR 0xC15C 666 #define CP_ME_RAM_DATA 0xC160 667 668 #define CP_CE_UCODE_ADDR 0xC168 669 #define CP_CE_UCODE_DATA 0xC16C 670 671 #define CP_RB1_BASE 0xC180 672 #define CP_RB1_CNTL 0xC184 673 #define CP_RB1_RPTR_ADDR 0xC188 674 #define CP_RB1_RPTR_ADDR_HI 0xC18C 675 #define CP_RB1_WPTR 0xC190 676 #define CP_RB2_BASE 0xC194 677 #define CP_RB2_CNTL 0xC198 678 #define CP_RB2_RPTR_ADDR 0xC19C 679 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 680 #define CP_RB2_WPTR 0xC1A4 681 #define CP_INT_CNTL_RING0 0xC1A8 682 #define CP_INT_CNTL_RING1 0xC1AC 683 #define CP_INT_CNTL_RING2 0xC1B0 684 # define CNTX_BUSY_INT_ENABLE (1 << 19) 685 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 686 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 687 # define TIME_STAMP_INT_ENABLE (1 << 26) 688 # define CP_RINGID2_INT_ENABLE (1 << 29) 689 # define CP_RINGID1_INT_ENABLE (1 << 30) 690 # define CP_RINGID0_INT_ENABLE (1 << 31) 691 #define CP_INT_STATUS_RING0 0xC1B4 692 #define CP_INT_STATUS_RING1 0xC1B8 693 #define CP_INT_STATUS_RING2 0xC1BC 694 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 695 # define TIME_STAMP_INT_STAT (1 << 26) 696 # define CP_RINGID2_INT_STAT (1 << 29) 697 # define CP_RINGID1_INT_STAT (1 << 30) 698 # define CP_RINGID0_INT_STAT (1 << 31) 699 700 #define CP_DEBUG 0xC1FC 701 702 #define RLC_CNTL 0xC300 703 # define RLC_ENABLE (1 << 0) 704 #define RLC_RL_BASE 0xC304 705 #define RLC_RL_SIZE 0xC308 706 #define RLC_LB_CNTL 0xC30C 707 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 708 #define RLC_LB_CNTR_MAX 0xC314 709 #define RLC_LB_CNTR_INIT 0xC318 710 711 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 712 713 #define RLC_UCODE_ADDR 0xC32C 714 #define RLC_UCODE_DATA 0xC330 715 716 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 717 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 718 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 719 #define RLC_MC_CNTL 0xC344 720 #define RLC_UCODE_CNTL 0xC348 721 722 #define PA_SC_RASTER_CONFIG 0x28350 723 # define RASTER_CONFIG_RB_MAP_0 0 724 # define RASTER_CONFIG_RB_MAP_1 1 725 # define RASTER_CONFIG_RB_MAP_2 2 726 # define RASTER_CONFIG_RB_MAP_3 3 727 728 #define VGT_EVENT_INITIATOR 0x28a90 729 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 730 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 731 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 732 # define CACHE_FLUSH_TS (4 << 0) 733 # define CACHE_FLUSH (6 << 0) 734 # define CS_PARTIAL_FLUSH (7 << 0) 735 # define VGT_STREAMOUT_RESET (10 << 0) 736 # define END_OF_PIPE_INCR_DE (11 << 0) 737 # define END_OF_PIPE_IB_END (12 << 0) 738 # define RST_PIX_CNT (13 << 0) 739 # define VS_PARTIAL_FLUSH (15 << 0) 740 # define PS_PARTIAL_FLUSH (16 << 0) 741 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 742 # define ZPASS_DONE (21 << 0) 743 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 744 # define PERFCOUNTER_START (23 << 0) 745 # define PERFCOUNTER_STOP (24 << 0) 746 # define PIPELINESTAT_START (25 << 0) 747 # define PIPELINESTAT_STOP (26 << 0) 748 # define PERFCOUNTER_SAMPLE (27 << 0) 749 # define SAMPLE_PIPELINESTAT (30 << 0) 750 # define SAMPLE_STREAMOUTSTATS (32 << 0) 751 # define RESET_VTX_CNT (33 << 0) 752 # define VGT_FLUSH (36 << 0) 753 # define BOTTOM_OF_PIPE_TS (40 << 0) 754 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 755 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 756 # define FLUSH_AND_INV_DB_META (44 << 0) 757 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 758 # define FLUSH_AND_INV_CB_META (46 << 0) 759 # define CS_DONE (47 << 0) 760 # define PS_DONE (48 << 0) 761 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 762 # define THREAD_TRACE_START (51 << 0) 763 # define THREAD_TRACE_STOP (52 << 0) 764 # define THREAD_TRACE_FLUSH (54 << 0) 765 # define THREAD_TRACE_FINISH (55 << 0) 766 767 /* 768 * PM4 769 */ 770 #define PACKET_TYPE0 0 771 #define PACKET_TYPE1 1 772 #define PACKET_TYPE2 2 773 #define PACKET_TYPE3 3 774 775 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 776 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 777 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 778 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 779 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 780 (((reg) >> 2) & 0xFFFF) | \ 781 ((n) & 0x3FFF) << 16) 782 #define CP_PACKET2 0x80000000 783 #define PACKET2_PAD_SHIFT 0 784 #define PACKET2_PAD_MASK (0x3fffffff << 0) 785 786 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 787 788 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 789 (((op) & 0xFF) << 8) | \ 790 ((n) & 0x3FFF) << 16) 791 792 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 793 794 /* Packet 3 types */ 795 #define PACKET3_NOP 0x10 796 #define PACKET3_SET_BASE 0x11 797 #define PACKET3_BASE_INDEX(x) ((x) << 0) 798 #define GDS_PARTITION_BASE 2 799 #define CE_PARTITION_BASE 3 800 #define PACKET3_CLEAR_STATE 0x12 801 #define PACKET3_INDEX_BUFFER_SIZE 0x13 802 #define PACKET3_DISPATCH_DIRECT 0x15 803 #define PACKET3_DISPATCH_INDIRECT 0x16 804 #define PACKET3_ALLOC_GDS 0x1B 805 #define PACKET3_WRITE_GDS_RAM 0x1C 806 #define PACKET3_ATOMIC_GDS 0x1D 807 #define PACKET3_ATOMIC 0x1E 808 #define PACKET3_OCCLUSION_QUERY 0x1F 809 #define PACKET3_SET_PREDICATION 0x20 810 #define PACKET3_REG_RMW 0x21 811 #define PACKET3_COND_EXEC 0x22 812 #define PACKET3_PRED_EXEC 0x23 813 #define PACKET3_DRAW_INDIRECT 0x24 814 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 815 #define PACKET3_INDEX_BASE 0x26 816 #define PACKET3_DRAW_INDEX_2 0x27 817 #define PACKET3_CONTEXT_CONTROL 0x28 818 #define PACKET3_INDEX_TYPE 0x2A 819 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 820 #define PACKET3_DRAW_INDEX_AUTO 0x2D 821 #define PACKET3_DRAW_INDEX_IMMD 0x2E 822 #define PACKET3_NUM_INSTANCES 0x2F 823 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 824 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 825 #define PACKET3_INDIRECT_BUFFER 0x32 826 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 827 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 828 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 829 #define PACKET3_WRITE_DATA 0x37 830 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 831 /* 0 - register 832 * 1 - memory (sync - via GRBM) 833 * 2 - tc/l2 834 * 3 - gds 835 * 4 - reserved 836 * 5 - memory (async - direct) 837 */ 838 #define WR_ONE_ADDR (1 << 16) 839 #define WR_CONFIRM (1 << 20) 840 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 841 /* 0 - me 842 * 1 - pfp 843 * 2 - ce 844 */ 845 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 846 #define PACKET3_MEM_SEMAPHORE 0x39 847 #define PACKET3_MPEG_INDEX 0x3A 848 #define PACKET3_COPY_DW 0x3B 849 #define PACKET3_WAIT_REG_MEM 0x3C 850 #define PACKET3_MEM_WRITE 0x3D 851 #define PACKET3_COPY_DATA 0x40 852 #define PACKET3_CP_DMA 0x41 853 /* 1. header 854 * 2. SRC_ADDR_LO or DATA [31:0] 855 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 856 * SRC_ADDR_HI [7:0] 857 * 4. DST_ADDR_LO [31:0] 858 * 5. DST_ADDR_HI [7:0] 859 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 860 */ 861 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 862 /* 0 - SRC_ADDR 863 * 1 - GDS 864 */ 865 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 866 /* 0 - ME 867 * 1 - PFP 868 */ 869 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 870 /* 0 - SRC_ADDR 871 * 1 - GDS 872 * 2 - DATA 873 */ 874 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 875 /* COMMAND */ 876 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 877 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 878 /* 0 - none 879 * 1 - 8 in 16 880 * 2 - 8 in 32 881 * 3 - 8 in 64 882 */ 883 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 884 /* 0 - none 885 * 1 - 8 in 16 886 * 2 - 8 in 32 887 * 3 - 8 in 64 888 */ 889 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 890 /* 0 - memory 891 * 1 - register 892 */ 893 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 894 /* 0 - memory 895 * 1 - register 896 */ 897 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 898 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 899 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 900 #define PACKET3_PFP_SYNC_ME 0x42 901 #define PACKET3_SURFACE_SYNC 0x43 902 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 903 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 904 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 905 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 906 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 907 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 908 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 909 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 910 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 911 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 912 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 913 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 914 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 915 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 916 # define PACKET3_TC_ACTION_ENA (1 << 23) 917 # define PACKET3_CB_ACTION_ENA (1 << 25) 918 # define PACKET3_DB_ACTION_ENA (1 << 26) 919 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 920 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 921 #define PACKET3_ME_INITIALIZE 0x44 922 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 923 #define PACKET3_COND_WRITE 0x45 924 #define PACKET3_EVENT_WRITE 0x46 925 #define EVENT_TYPE(x) ((x) << 0) 926 #define EVENT_INDEX(x) ((x) << 8) 927 /* 0 - any non-TS event 928 * 1 - ZPASS_DONE 929 * 2 - SAMPLE_PIPELINESTAT 930 * 3 - SAMPLE_STREAMOUTSTAT* 931 * 4 - *S_PARTIAL_FLUSH 932 * 5 - EOP events 933 * 6 - EOS events 934 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 935 */ 936 #define INV_L2 (1 << 20) 937 /* INV TC L2 cache when EVENT_INDEX = 7 */ 938 #define PACKET3_EVENT_WRITE_EOP 0x47 939 #define DATA_SEL(x) ((x) << 29) 940 /* 0 - discard 941 * 1 - send low 32bit data 942 * 2 - send 64bit data 943 * 3 - send 64bit counter value 944 */ 945 #define INT_SEL(x) ((x) << 24) 946 /* 0 - none 947 * 1 - interrupt only (DATA_SEL = 0) 948 * 2 - interrupt when data write is confirmed 949 */ 950 #define PACKET3_EVENT_WRITE_EOS 0x48 951 #define PACKET3_PREAMBLE_CNTL 0x4A 952 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 953 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 954 #define PACKET3_ONE_REG_WRITE 0x57 955 #define PACKET3_LOAD_CONFIG_REG 0x5F 956 #define PACKET3_LOAD_CONTEXT_REG 0x60 957 #define PACKET3_LOAD_SH_REG 0x61 958 #define PACKET3_SET_CONFIG_REG 0x68 959 #define PACKET3_SET_CONFIG_REG_START 0x00008000 960 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 961 #define PACKET3_SET_CONTEXT_REG 0x69 962 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 963 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 964 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 965 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 966 #define PACKET3_SET_SH_REG 0x76 967 #define PACKET3_SET_SH_REG_START 0x0000b000 968 #define PACKET3_SET_SH_REG_END 0x0000c000 969 #define PACKET3_SET_SH_REG_OFFSET 0x77 970 #define PACKET3_ME_WRITE 0x7A 971 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 972 #define PACKET3_SCRATCH_RAM_READ 0x7E 973 #define PACKET3_CE_WRITE 0x7F 974 #define PACKET3_LOAD_CONST_RAM 0x80 975 #define PACKET3_WRITE_CONST_RAM 0x81 976 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 977 #define PACKET3_DUMP_CONST_RAM 0x83 978 #define PACKET3_INCREMENT_CE_COUNTER 0x84 979 #define PACKET3_INCREMENT_DE_COUNTER 0x85 980 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 981 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 982 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 983 #define PACKET3_SET_CE_DE_COUNTERS 0x89 984 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 985 #define PACKET3_SWITCH_BUFFER 0x8B 986 987 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 988 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 989 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 990 991 #define DMA_RB_CNTL 0xd000 992 # define DMA_RB_ENABLE (1 << 0) 993 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 994 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 995 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 996 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 997 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 998 #define DMA_RB_BASE 0xd004 999 #define DMA_RB_RPTR 0xd008 1000 #define DMA_RB_WPTR 0xd00c 1001 1002 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1003 #define DMA_RB_RPTR_ADDR_LO 0xd020 1004 1005 #define DMA_IB_CNTL 0xd024 1006 # define DMA_IB_ENABLE (1 << 0) 1007 # define DMA_IB_SWAP_ENABLE (1 << 4) 1008 #define DMA_IB_RPTR 0xd028 1009 #define DMA_CNTL 0xd02c 1010 # define TRAP_ENABLE (1 << 0) 1011 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1012 # define SEM_WAIT_INT_ENABLE (1 << 2) 1013 # define DATA_SWAP_ENABLE (1 << 3) 1014 # define FENCE_SWAP_ENABLE (1 << 4) 1015 # define CTXEMPTY_INT_ENABLE (1 << 28) 1016 #define DMA_TILING_CONFIG 0xd0b8 1017 1018 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1019 (((b) & 0x1) << 26) | \ 1020 (((t) & 0x1) << 23) | \ 1021 (((s) & 0x1) << 22) | \ 1022 (((n) & 0xFFFFF) << 0)) 1023 1024 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1025 (((vmid) & 0xF) << 20) | \ 1026 (((n) & 0xFFFFF) << 0)) 1027 1028 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1029 (1 << 26) | \ 1030 (1 << 21) | \ 1031 (((n) & 0xFFFFF) << 0)) 1032 1033 /* async DMA Packet types */ 1034 #define DMA_PACKET_WRITE 0x2 1035 #define DMA_PACKET_COPY 0x3 1036 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1037 #define DMA_PACKET_SEMAPHORE 0x5 1038 #define DMA_PACKET_FENCE 0x6 1039 #define DMA_PACKET_TRAP 0x7 1040 #define DMA_PACKET_SRBM_WRITE 0x9 1041 #define DMA_PACKET_CONSTANT_FILL 0xd 1042 #define DMA_PACKET_NOP 0xf 1043 1044 #endif 1045