1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define CG_MULT_THERMAL_STATUS 0x714 28 #define ASIC_MAX_TEMP(x) ((x) << 0) 29 #define ASIC_MAX_TEMP_MASK 0x000001ff 30 #define ASIC_MAX_TEMP_SHIFT 0 31 #define CTF_TEMP(x) ((x) << 9) 32 #define CTF_TEMP_MASK 0x0003fe00 33 #define CTF_TEMP_SHIFT 9 34 35 #define SI_MAX_SH_GPRS 256 36 #define SI_MAX_TEMP_GPRS 16 37 #define SI_MAX_SH_THREADS 256 38 #define SI_MAX_SH_STACK_ENTRIES 4096 39 #define SI_MAX_FRC_EOV_CNT 16384 40 #define SI_MAX_BACKENDS 8 41 #define SI_MAX_BACKENDS_MASK 0xFF 42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 43 #define SI_MAX_SIMDS 12 44 #define SI_MAX_SIMDS_MASK 0x0FFF 45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 46 #define SI_MAX_PIPES 8 47 #define SI_MAX_PIPES_MASK 0xFF 48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 49 #define SI_MAX_LDS_NUM 0xFFFF 50 #define SI_MAX_TCC 16 51 #define SI_MAX_TCC_MASK 0xFFFF 52 53 #define DMIF_ADDR_CONFIG 0xBD4 54 55 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 56 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 57 58 #define MC_SHARED_CHMAP 0x2004 59 #define NOOFCHAN_SHIFT 12 60 #define NOOFCHAN_MASK 0x0000f000 61 #define MC_SHARED_CHREMAP 0x2008 62 63 #define MC_ARB_RAMCFG 0x2760 64 #define NOOFBANK_SHIFT 0 65 #define NOOFBANK_MASK 0x00000003 66 #define NOOFRANK_SHIFT 2 67 #define NOOFRANK_MASK 0x00000004 68 #define NOOFROWS_SHIFT 3 69 #define NOOFROWS_MASK 0x00000038 70 #define NOOFCOLS_SHIFT 6 71 #define NOOFCOLS_MASK 0x000000C0 72 #define CHANSIZE_SHIFT 8 73 #define CHANSIZE_MASK 0x00000100 74 #define NOOFGROUPS_SHIFT 12 75 #define NOOFGROUPS_MASK 0x00001000 76 77 #define HDP_HOST_PATH_CNTL 0x2C00 78 79 #define HDP_ADDR_CONFIG 0x2F48 80 #define HDP_MISC_CNTL 0x2F4C 81 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 82 83 #define BIF_FB_EN 0x5490 84 #define FB_READ_EN (1 << 0) 85 #define FB_WRITE_EN (1 << 1) 86 87 #define DC_LB_MEMORY_SPLIT 0x6b0c 88 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 89 90 #define PRIORITY_A_CNT 0x6b18 91 #define PRIORITY_MARK_MASK 0x7fff 92 #define PRIORITY_OFF (1 << 16) 93 #define PRIORITY_ALWAYS_ON (1 << 20) 94 #define PRIORITY_B_CNT 0x6b1c 95 96 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 97 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 98 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 99 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 100 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 101 102 #define GRBM_CNTL 0x8000 103 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 104 105 #define CP_QUEUE_THRESHOLDS 0x8760 106 #define ROQ_IB1_START(x) ((x) << 0) 107 #define ROQ_IB2_START(x) ((x) << 8) 108 #define CP_MEQ_THRESHOLDS 0x8764 109 #define MEQ1_START(x) ((x) << 0) 110 #define MEQ2_START(x) ((x) << 8) 111 112 #define CP_PERFMON_CNTL 0x87FC 113 114 #define VGT_CACHE_INVALIDATION 0x88C4 115 #define CACHE_INVALIDATION(x) ((x) << 0) 116 #define VC_ONLY 0 117 #define TC_ONLY 1 118 #define VC_AND_TC 2 119 #define AUTO_INVLD_EN(x) ((x) << 6) 120 #define NO_AUTO 0 121 #define ES_AUTO 1 122 #define GS_AUTO 2 123 #define ES_AND_GS_AUTO 3 124 125 #define VGT_GS_VERTEX_REUSE 0x88D4 126 127 #define VGT_NUM_INSTANCES 0x8974 128 129 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 130 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 131 132 #define PA_CL_ENHANCE 0x8A14 133 #define CLIP_VTX_REORDER_ENA (1 << 0) 134 #define NUM_CLIP_SEQ(x) ((x) << 1) 135 136 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 137 138 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 139 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 140 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 141 142 #define PA_SC_FIFO_SIZE 0x8BCC 143 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 144 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 145 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 146 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 147 148 #define SQ_CONFIG 0x8C00 149 150 #define SX_DEBUG_1 0x9060 151 152 #define SPI_CONFIG_CNTL_1 0x913C 153 #define VTX_DONE_DELAY(x) ((x) << 0) 154 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 155 156 #define CGTS_TCC_DISABLE 0x9148 157 #define CGTS_USER_TCC_DISABLE 0x914C 158 #define TCC_DISABLE_MASK 0xFFFF0000 159 #define TCC_DISABLE_SHIFT 16 160 161 #define CC_RB_BACKEND_DISABLE 0x98F4 162 #define BACKEND_DISABLE(x) ((x) << 16) 163 #define GB_ADDR_CONFIG 0x98F8 164 #define NUM_PIPES(x) ((x) << 0) 165 #define NUM_PIPES_MASK 0x00000007 166 #define NUM_PIPES_SHIFT 0 167 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 168 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 169 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 170 #define NUM_SHADER_ENGINES(x) ((x) << 12) 171 #define NUM_SHADER_ENGINES_MASK 0x00003000 172 #define NUM_SHADER_ENGINES_SHIFT 12 173 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 174 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 175 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 176 #define NUM_GPUS(x) ((x) << 20) 177 #define NUM_GPUS_MASK 0x00700000 178 #define NUM_GPUS_SHIFT 20 179 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 180 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 181 #define MULTI_GPU_TILE_SIZE_SHIFT 24 182 #define ROW_SIZE(x) ((x) << 28) 183 #define ROW_SIZE_MASK 0x30000000 184 #define ROW_SIZE_SHIFT 28 185 186 #define GB_TILE_MODE0 0x9910 187 # define MICRO_TILE_MODE(x) ((x) << 0) 188 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 189 # define ADDR_SURF_THIN_MICRO_TILING 1 190 # define ADDR_SURF_DEPTH_MICRO_TILING 2 191 # define ARRAY_MODE(x) ((x) << 2) 192 # define ARRAY_LINEAR_GENERAL 0 193 # define ARRAY_LINEAR_ALIGNED 1 194 # define ARRAY_1D_TILED_THIN1 2 195 # define ARRAY_2D_TILED_THIN1 4 196 # define PIPE_CONFIG(x) ((x) << 6) 197 # define ADDR_SURF_P2 0 198 # define ADDR_SURF_P4_8x16 4 199 # define ADDR_SURF_P4_16x16 5 200 # define ADDR_SURF_P4_16x32 6 201 # define ADDR_SURF_P4_32x32 7 202 # define ADDR_SURF_P8_16x16_8x16 8 203 # define ADDR_SURF_P8_16x32_8x16 9 204 # define ADDR_SURF_P8_32x32_8x16 10 205 # define ADDR_SURF_P8_16x32_16x16 11 206 # define ADDR_SURF_P8_32x32_16x16 12 207 # define ADDR_SURF_P8_32x32_16x32 13 208 # define ADDR_SURF_P8_32x64_32x32 14 209 # define TILE_SPLIT(x) ((x) << 11) 210 # define ADDR_SURF_TILE_SPLIT_64B 0 211 # define ADDR_SURF_TILE_SPLIT_128B 1 212 # define ADDR_SURF_TILE_SPLIT_256B 2 213 # define ADDR_SURF_TILE_SPLIT_512B 3 214 # define ADDR_SURF_TILE_SPLIT_1KB 4 215 # define ADDR_SURF_TILE_SPLIT_2KB 5 216 # define ADDR_SURF_TILE_SPLIT_4KB 6 217 # define BANK_WIDTH(x) ((x) << 14) 218 # define ADDR_SURF_BANK_WIDTH_1 0 219 # define ADDR_SURF_BANK_WIDTH_2 1 220 # define ADDR_SURF_BANK_WIDTH_4 2 221 # define ADDR_SURF_BANK_WIDTH_8 3 222 # define BANK_HEIGHT(x) ((x) << 16) 223 # define ADDR_SURF_BANK_HEIGHT_1 0 224 # define ADDR_SURF_BANK_HEIGHT_2 1 225 # define ADDR_SURF_BANK_HEIGHT_4 2 226 # define ADDR_SURF_BANK_HEIGHT_8 3 227 # define MACRO_TILE_ASPECT(x) ((x) << 18) 228 # define ADDR_SURF_MACRO_ASPECT_1 0 229 # define ADDR_SURF_MACRO_ASPECT_2 1 230 # define ADDR_SURF_MACRO_ASPECT_4 2 231 # define ADDR_SURF_MACRO_ASPECT_8 3 232 # define NUM_BANKS(x) ((x) << 20) 233 # define ADDR_SURF_2_BANK 0 234 # define ADDR_SURF_4_BANK 1 235 # define ADDR_SURF_8_BANK 2 236 # define ADDR_SURF_16_BANK 3 237 238 #define CB_PERFCOUNTER0_SELECT0 0x9a20 239 #define CB_PERFCOUNTER0_SELECT1 0x9a24 240 #define CB_PERFCOUNTER1_SELECT0 0x9a28 241 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 242 #define CB_PERFCOUNTER2_SELECT0 0x9a30 243 #define CB_PERFCOUNTER2_SELECT1 0x9a34 244 #define CB_PERFCOUNTER3_SELECT0 0x9a38 245 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 246 247 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 248 #define BACKEND_DISABLE_MASK 0x00FF0000 249 #define BACKEND_DISABLE_SHIFT 16 250 251 #define TCP_CHAN_STEER_LO 0xac0c 252 #define TCP_CHAN_STEER_HI 0xac10 253 254 255 #endif 256