1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/math64.h> 25 #include <linux/seq_file.h> 26 27 #include <drm/drm_pci.h> 28 29 #include "atom.h" 30 #include "r600_dpm.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "si_dpm.h" 34 #include "sid.h" 35 36 #define MC_CG_ARB_FREQ_F0 0x0a 37 #define MC_CG_ARB_FREQ_F1 0x0b 38 #define MC_CG_ARB_FREQ_F2 0x0c 39 #define MC_CG_ARB_FREQ_F3 0x0d 40 41 #define SMC_RAM_END 0x20000 42 43 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 44 45 static const struct si_cac_config_reg cac_weights_tahiti[] = 46 { 47 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 50 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 51 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 57 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 59 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 60 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 62 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 65 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 66 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 68 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 69 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 78 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 82 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 85 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 87 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 107 { 0xFFFFFFFF } 108 }; 109 110 static const struct si_cac_config_reg lcac_tahiti[] = 111 { 112 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 185 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0xFFFFFFFF } 199 200 }; 201 202 static const struct si_cac_config_reg cac_override_tahiti[] = 203 { 204 { 0xFFFFFFFF } 205 }; 206 207 static const struct si_powertune_data powertune_data_tahiti = 208 { 209 ((1 << 16) | 27027), 210 6, 211 0, 212 4, 213 95, 214 { 215 0UL, 216 0UL, 217 4521550UL, 218 309631529UL, 219 -1270850L, 220 4513710L, 221 40 222 }, 223 595000000UL, 224 12, 225 { 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0, 233 0 234 }, 235 true 236 }; 237 238 static const struct si_dte_data dte_data_tahiti = 239 { 240 { 1159409, 0, 0, 0, 0 }, 241 { 777, 0, 0, 0, 0 }, 242 2, 243 54000, 244 127000, 245 25, 246 2, 247 10, 248 13, 249 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 250 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 251 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 252 85, 253 false 254 }; 255 256 static const struct si_dte_data dte_data_tahiti_le = 257 { 258 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 259 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 260 0x5, 261 0xAFC8, 262 0x64, 263 0x32, 264 1, 265 0, 266 0x10, 267 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 268 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 269 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 270 85, 271 true 272 }; 273 274 static const struct si_dte_data dte_data_tahiti_pro = 275 { 276 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 277 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 278 5, 279 45000, 280 100, 281 0xA, 282 1, 283 0, 284 0x10, 285 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 286 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 287 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 288 90, 289 true 290 }; 291 292 static const struct si_dte_data dte_data_new_zealand = 293 { 294 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 295 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 296 0x5, 297 0xAFC8, 298 0x69, 299 0x32, 300 1, 301 0, 302 0x10, 303 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 304 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 305 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 306 85, 307 true 308 }; 309 310 static const struct si_dte_data dte_data_aruba_pro = 311 { 312 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 313 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 314 5, 315 45000, 316 100, 317 0xA, 318 1, 319 0, 320 0x10, 321 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 322 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 323 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 324 90, 325 true 326 }; 327 328 static const struct si_dte_data dte_data_malta = 329 { 330 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 331 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 332 5, 333 45000, 334 100, 335 0xA, 336 1, 337 0, 338 0x10, 339 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 340 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 341 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 342 90, 343 true 344 }; 345 346 struct si_cac_config_reg cac_weights_pitcairn[] = 347 { 348 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 349 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 354 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 356 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 358 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 360 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 361 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 365 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 366 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 367 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 369 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 370 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 375 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 379 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 383 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 385 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 408 { 0xFFFFFFFF } 409 }; 410 411 static const struct si_cac_config_reg lcac_pitcairn[] = 412 { 413 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 416 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0xFFFFFFFF } 500 }; 501 502 static const struct si_cac_config_reg cac_override_pitcairn[] = 503 { 504 { 0xFFFFFFFF } 505 }; 506 507 static const struct si_powertune_data powertune_data_pitcairn = 508 { 509 ((1 << 16) | 27027), 510 5, 511 0, 512 6, 513 100, 514 { 515 51600000UL, 516 1800000UL, 517 7194395UL, 518 309631529UL, 519 -1270850L, 520 4513710L, 521 100 522 }, 523 117830498UL, 524 12, 525 { 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0 534 }, 535 true 536 }; 537 538 static const struct si_dte_data dte_data_pitcairn = 539 { 540 { 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0 }, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 0, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 552 0, 553 false 554 }; 555 556 static const struct si_dte_data dte_data_curacao_xt = 557 { 558 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 559 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 560 5, 561 45000, 562 100, 563 0xA, 564 1, 565 0, 566 0x10, 567 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 568 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 569 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 570 90, 571 true 572 }; 573 574 static const struct si_dte_data dte_data_curacao_pro = 575 { 576 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 577 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 578 5, 579 45000, 580 100, 581 0xA, 582 1, 583 0, 584 0x10, 585 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 586 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 587 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 588 90, 589 true 590 }; 591 592 static const struct si_dte_data dte_data_neptune_xt = 593 { 594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 596 5, 597 45000, 598 100, 599 0xA, 600 1, 601 0, 602 0x10, 603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 605 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 606 90, 607 true 608 }; 609 610 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 611 { 612 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 613 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 615 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 616 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 620 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 622 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 624 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 625 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 627 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 629 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 630 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 631 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 633 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 634 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 637 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 639 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 643 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 644 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 647 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 650 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 652 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 653 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 672 { 0xFFFFFFFF } 673 }; 674 675 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 676 { 677 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 678 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 680 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 681 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 685 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 687 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 689 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 690 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 692 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 694 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 695 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 696 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 698 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 699 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 702 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 704 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 708 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 709 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 712 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 715 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 717 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 718 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 737 { 0xFFFFFFFF } 738 }; 739 740 static const struct si_cac_config_reg cac_weights_heathrow[] = 741 { 742 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 743 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 745 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 746 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 750 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 752 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 754 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 755 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 757 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 759 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 760 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 761 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 763 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 764 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 767 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 769 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 773 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 774 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 777 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 780 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 782 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 783 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 802 { 0xFFFFFFFF } 803 }; 804 805 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 806 { 807 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 808 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 810 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 811 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 815 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 817 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 819 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 820 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 822 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 824 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 825 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 826 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 828 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 829 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 832 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 834 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 838 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 839 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 842 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 845 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 847 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 848 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 867 { 0xFFFFFFFF } 868 }; 869 870 static const struct si_cac_config_reg cac_weights_cape_verde[] = 871 { 872 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 873 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 875 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 876 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 880 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 882 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 884 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 885 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 887 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 889 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 890 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 891 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 893 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 894 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 897 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 899 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 903 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 904 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 907 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 910 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 912 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 913 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 932 { 0xFFFFFFFF } 933 }; 934 935 static const struct si_cac_config_reg lcac_cape_verde[] = 936 { 937 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 940 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 956 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0xFFFFFFFF } 992 }; 993 994 static const struct si_cac_config_reg cac_override_cape_verde[] = 995 { 996 { 0xFFFFFFFF } 997 }; 998 999 static const struct si_powertune_data powertune_data_cape_verde = 1000 { 1001 ((1 << 16) | 0x6993), 1002 5, 1003 0, 1004 7, 1005 105, 1006 { 1007 0UL, 1008 0UL, 1009 7194395UL, 1010 309631529UL, 1011 -1270850L, 1012 4513710L, 1013 100 1014 }, 1015 117830498UL, 1016 12, 1017 { 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0 1026 }, 1027 true 1028 }; 1029 1030 static const struct si_dte_data dte_data_cape_verde = 1031 { 1032 { 0, 0, 0, 0, 0 }, 1033 { 0, 0, 0, 0, 0 }, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 0, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1044 0, 1045 false 1046 }; 1047 1048 static const struct si_dte_data dte_data_venus_xtx = 1049 { 1050 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1051 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1052 5, 1053 55000, 1054 0x69, 1055 0xA, 1056 1, 1057 0, 1058 0x3, 1059 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1062 90, 1063 true 1064 }; 1065 1066 static const struct si_dte_data dte_data_venus_xt = 1067 { 1068 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1069 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1070 5, 1071 55000, 1072 0x69, 1073 0xA, 1074 1, 1075 0, 1076 0x3, 1077 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1080 90, 1081 true 1082 }; 1083 1084 static const struct si_dte_data dte_data_venus_pro = 1085 { 1086 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1087 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1088 5, 1089 55000, 1090 0x69, 1091 0xA, 1092 1, 1093 0, 1094 0x3, 1095 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1098 90, 1099 true 1100 }; 1101 1102 struct si_cac_config_reg cac_weights_oland[] = 1103 { 1104 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1164 { 0xFFFFFFFF } 1165 }; 1166 1167 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1168 { 1169 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xFFFFFFFF } 1230 }; 1231 1232 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1233 { 1234 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xFFFFFFFF } 1295 }; 1296 1297 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1298 { 1299 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xFFFFFFFF } 1360 }; 1361 1362 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1363 { 1364 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xFFFFFFFF } 1425 }; 1426 1427 static const struct si_cac_config_reg lcac_oland[] = 1428 { 1429 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xFFFFFFFF } 1472 }; 1473 1474 static const struct si_cac_config_reg lcac_mars_pro[] = 1475 { 1476 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0xFFFFFFFF } 1519 }; 1520 1521 static const struct si_cac_config_reg cac_override_oland[] = 1522 { 1523 { 0xFFFFFFFF } 1524 }; 1525 1526 static const struct si_powertune_data powertune_data_oland = 1527 { 1528 ((1 << 16) | 0x6993), 1529 5, 1530 0, 1531 7, 1532 105, 1533 { 1534 0UL, 1535 0UL, 1536 7194395UL, 1537 309631529UL, 1538 -1270850L, 1539 4513710L, 1540 100 1541 }, 1542 117830498UL, 1543 12, 1544 { 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0, 1552 0 1553 }, 1554 true 1555 }; 1556 1557 static const struct si_powertune_data powertune_data_mars_pro = 1558 { 1559 ((1 << 16) | 0x6993), 1560 5, 1561 0, 1562 7, 1563 105, 1564 { 1565 0UL, 1566 0UL, 1567 7194395UL, 1568 309631529UL, 1569 -1270850L, 1570 4513710L, 1571 100 1572 }, 1573 117830498UL, 1574 12, 1575 { 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0 1584 }, 1585 true 1586 }; 1587 1588 static const struct si_dte_data dte_data_oland = 1589 { 1590 { 0, 0, 0, 0, 0 }, 1591 { 0, 0, 0, 0, 0 }, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 0, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1602 0, 1603 false 1604 }; 1605 1606 static const struct si_dte_data dte_data_mars_pro = 1607 { 1608 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1609 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1610 5, 1611 55000, 1612 105, 1613 0xA, 1614 1, 1615 0, 1616 0x10, 1617 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1618 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1619 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1620 90, 1621 true 1622 }; 1623 1624 static const struct si_dte_data dte_data_sun_xt = 1625 { 1626 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1627 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1628 5, 1629 55000, 1630 105, 1631 0xA, 1632 1, 1633 0, 1634 0x10, 1635 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1636 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1637 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1638 90, 1639 true 1640 }; 1641 1642 1643 static const struct si_cac_config_reg cac_weights_hainan[] = 1644 { 1645 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1705 { 0xFFFFFFFF } 1706 }; 1707 1708 static const struct si_powertune_data powertune_data_hainan = 1709 { 1710 ((1 << 16) | 0x6993), 1711 5, 1712 0, 1713 9, 1714 105, 1715 { 1716 0UL, 1717 0UL, 1718 7194395UL, 1719 309631529UL, 1720 -1270850L, 1721 4513710L, 1722 100 1723 }, 1724 117830498UL, 1725 12, 1726 { 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0, 1734 0 1735 }, 1736 true 1737 }; 1738 1739 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1740 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1741 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1742 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1743 1744 extern int si_mc_load_microcode(struct radeon_device *rdev); 1745 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1746 1747 static int si_populate_voltage_value(struct radeon_device *rdev, 1748 const struct atom_voltage_table *table, 1749 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1750 static int si_get_std_voltage_value(struct radeon_device *rdev, 1751 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1752 u16 *std_voltage); 1753 static int si_write_smc_soft_register(struct radeon_device *rdev, 1754 u16 reg_offset, u32 value); 1755 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1756 struct rv7xx_pl *pl, 1757 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1758 static int si_calculate_sclk_params(struct radeon_device *rdev, 1759 u32 engine_clock, 1760 SISLANDS_SMC_SCLK_VALUE *sclk); 1761 1762 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1763 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1764 1765 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1766 { 1767 struct si_power_info *pi = rdev->pm.dpm.priv; 1768 1769 return pi; 1770 } 1771 1772 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1773 u16 v, s32 t, u32 ileakage, u32 *leakage) 1774 { 1775 s64 kt, kv, leakage_w, i_leakage, vddc; 1776 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1777 s64 tmp; 1778 1779 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1780 vddc = div64_s64(drm_int2fixp(v), 1000); 1781 temperature = div64_s64(drm_int2fixp(t), 1000); 1782 1783 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1784 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1785 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1786 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1787 t_ref = drm_int2fixp(coeff->t_ref); 1788 1789 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1790 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1791 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1792 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1793 1794 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1795 1796 *leakage = drm_fixp2int(leakage_w * 1000); 1797 } 1798 1799 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1800 const struct ni_leakage_coeffients *coeff, 1801 u16 v, 1802 s32 t, 1803 u32 i_leakage, 1804 u32 *leakage) 1805 { 1806 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1807 } 1808 1809 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1810 const u32 fixed_kt, u16 v, 1811 u32 ileakage, u32 *leakage) 1812 { 1813 s64 kt, kv, leakage_w, i_leakage, vddc; 1814 1815 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1816 vddc = div64_s64(drm_int2fixp(v), 1000); 1817 1818 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1819 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1820 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1821 1822 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1823 1824 *leakage = drm_fixp2int(leakage_w * 1000); 1825 } 1826 1827 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1828 const struct ni_leakage_coeffients *coeff, 1829 const u32 fixed_kt, 1830 u16 v, 1831 u32 i_leakage, 1832 u32 *leakage) 1833 { 1834 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1835 } 1836 1837 1838 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1839 struct si_dte_data *dte_data) 1840 { 1841 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1842 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1843 u32 k = dte_data->k; 1844 u32 t_max = dte_data->max_t; 1845 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1846 u32 t_0 = dte_data->t0; 1847 u32 i; 1848 1849 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1850 dte_data->tdep_count = 3; 1851 1852 for (i = 0; i < k; i++) { 1853 dte_data->r[i] = 1854 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1855 (p_limit2 * (u32)100); 1856 } 1857 1858 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1859 1860 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1861 dte_data->tdep_r[i] = dte_data->r[4]; 1862 } 1863 } else { 1864 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1865 } 1866 } 1867 1868 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1869 { 1870 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1871 struct si_power_info *si_pi = si_get_pi(rdev); 1872 bool update_dte_from_pl2 = false; 1873 1874 if (rdev->family == CHIP_TAHITI) { 1875 si_pi->cac_weights = cac_weights_tahiti; 1876 si_pi->lcac_config = lcac_tahiti; 1877 si_pi->cac_override = cac_override_tahiti; 1878 si_pi->powertune_data = &powertune_data_tahiti; 1879 si_pi->dte_data = dte_data_tahiti; 1880 1881 switch (rdev->pdev->device) { 1882 case 0x6798: 1883 si_pi->dte_data.enable_dte_by_default = true; 1884 break; 1885 case 0x6799: 1886 si_pi->dte_data = dte_data_new_zealand; 1887 break; 1888 case 0x6790: 1889 case 0x6791: 1890 case 0x6792: 1891 case 0x679E: 1892 si_pi->dte_data = dte_data_aruba_pro; 1893 update_dte_from_pl2 = true; 1894 break; 1895 case 0x679B: 1896 si_pi->dte_data = dte_data_malta; 1897 update_dte_from_pl2 = true; 1898 break; 1899 case 0x679A: 1900 si_pi->dte_data = dte_data_tahiti_pro; 1901 update_dte_from_pl2 = true; 1902 break; 1903 default: 1904 if (si_pi->dte_data.enable_dte_by_default == true) 1905 DRM_ERROR("DTE is not enabled!\n"); 1906 break; 1907 } 1908 } else if (rdev->family == CHIP_PITCAIRN) { 1909 switch (rdev->pdev->device) { 1910 case 0x6810: 1911 case 0x6818: 1912 si_pi->cac_weights = cac_weights_pitcairn; 1913 si_pi->lcac_config = lcac_pitcairn; 1914 si_pi->cac_override = cac_override_pitcairn; 1915 si_pi->powertune_data = &powertune_data_pitcairn; 1916 si_pi->dte_data = dte_data_curacao_xt; 1917 update_dte_from_pl2 = true; 1918 break; 1919 case 0x6819: 1920 case 0x6811: 1921 si_pi->cac_weights = cac_weights_pitcairn; 1922 si_pi->lcac_config = lcac_pitcairn; 1923 si_pi->cac_override = cac_override_pitcairn; 1924 si_pi->powertune_data = &powertune_data_pitcairn; 1925 si_pi->dte_data = dte_data_curacao_pro; 1926 update_dte_from_pl2 = true; 1927 break; 1928 case 0x6800: 1929 case 0x6806: 1930 si_pi->cac_weights = cac_weights_pitcairn; 1931 si_pi->lcac_config = lcac_pitcairn; 1932 si_pi->cac_override = cac_override_pitcairn; 1933 si_pi->powertune_data = &powertune_data_pitcairn; 1934 si_pi->dte_data = dte_data_neptune_xt; 1935 update_dte_from_pl2 = true; 1936 break; 1937 default: 1938 si_pi->cac_weights = cac_weights_pitcairn; 1939 si_pi->lcac_config = lcac_pitcairn; 1940 si_pi->cac_override = cac_override_pitcairn; 1941 si_pi->powertune_data = &powertune_data_pitcairn; 1942 si_pi->dte_data = dte_data_pitcairn; 1943 break; 1944 } 1945 } else if (rdev->family == CHIP_VERDE) { 1946 si_pi->lcac_config = lcac_cape_verde; 1947 si_pi->cac_override = cac_override_cape_verde; 1948 si_pi->powertune_data = &powertune_data_cape_verde; 1949 1950 switch (rdev->pdev->device) { 1951 case 0x683B: 1952 case 0x683F: 1953 case 0x6829: 1954 case 0x6835: 1955 si_pi->cac_weights = cac_weights_cape_verde_pro; 1956 si_pi->dte_data = dte_data_cape_verde; 1957 break; 1958 case 0x682C: 1959 si_pi->cac_weights = cac_weights_cape_verde_pro; 1960 si_pi->dte_data = dte_data_sun_xt; 1961 break; 1962 case 0x6825: 1963 case 0x6827: 1964 si_pi->cac_weights = cac_weights_heathrow; 1965 si_pi->dte_data = dte_data_cape_verde; 1966 break; 1967 case 0x6824: 1968 case 0x682D: 1969 si_pi->cac_weights = cac_weights_chelsea_xt; 1970 si_pi->dte_data = dte_data_cape_verde; 1971 break; 1972 case 0x682F: 1973 si_pi->cac_weights = cac_weights_chelsea_pro; 1974 si_pi->dte_data = dte_data_cape_verde; 1975 break; 1976 case 0x6820: 1977 si_pi->cac_weights = cac_weights_heathrow; 1978 si_pi->dte_data = dte_data_venus_xtx; 1979 break; 1980 case 0x6821: 1981 si_pi->cac_weights = cac_weights_heathrow; 1982 si_pi->dte_data = dte_data_venus_xt; 1983 break; 1984 case 0x6823: 1985 case 0x682B: 1986 case 0x6822: 1987 case 0x682A: 1988 si_pi->cac_weights = cac_weights_chelsea_pro; 1989 si_pi->dte_data = dte_data_venus_pro; 1990 break; 1991 default: 1992 si_pi->cac_weights = cac_weights_cape_verde; 1993 si_pi->dte_data = dte_data_cape_verde; 1994 break; 1995 } 1996 } else if (rdev->family == CHIP_OLAND) { 1997 switch (rdev->pdev->device) { 1998 case 0x6601: 1999 case 0x6621: 2000 case 0x6603: 2001 case 0x6605: 2002 si_pi->cac_weights = cac_weights_mars_pro; 2003 si_pi->lcac_config = lcac_mars_pro; 2004 si_pi->cac_override = cac_override_oland; 2005 si_pi->powertune_data = &powertune_data_mars_pro; 2006 si_pi->dte_data = dte_data_mars_pro; 2007 update_dte_from_pl2 = true; 2008 break; 2009 case 0x6600: 2010 case 0x6606: 2011 case 0x6620: 2012 case 0x6604: 2013 si_pi->cac_weights = cac_weights_mars_xt; 2014 si_pi->lcac_config = lcac_mars_pro; 2015 si_pi->cac_override = cac_override_oland; 2016 si_pi->powertune_data = &powertune_data_mars_pro; 2017 si_pi->dte_data = dte_data_mars_pro; 2018 update_dte_from_pl2 = true; 2019 break; 2020 case 0x6611: 2021 case 0x6613: 2022 case 0x6608: 2023 si_pi->cac_weights = cac_weights_oland_pro; 2024 si_pi->lcac_config = lcac_mars_pro; 2025 si_pi->cac_override = cac_override_oland; 2026 si_pi->powertune_data = &powertune_data_mars_pro; 2027 si_pi->dte_data = dte_data_mars_pro; 2028 update_dte_from_pl2 = true; 2029 break; 2030 case 0x6610: 2031 si_pi->cac_weights = cac_weights_oland_xt; 2032 si_pi->lcac_config = lcac_mars_pro; 2033 si_pi->cac_override = cac_override_oland; 2034 si_pi->powertune_data = &powertune_data_mars_pro; 2035 si_pi->dte_data = dte_data_mars_pro; 2036 update_dte_from_pl2 = true; 2037 break; 2038 default: 2039 si_pi->cac_weights = cac_weights_oland; 2040 si_pi->lcac_config = lcac_oland; 2041 si_pi->cac_override = cac_override_oland; 2042 si_pi->powertune_data = &powertune_data_oland; 2043 si_pi->dte_data = dte_data_oland; 2044 break; 2045 } 2046 } else if (rdev->family == CHIP_HAINAN) { 2047 si_pi->cac_weights = cac_weights_hainan; 2048 si_pi->lcac_config = lcac_oland; 2049 si_pi->cac_override = cac_override_oland; 2050 si_pi->powertune_data = &powertune_data_hainan; 2051 si_pi->dte_data = dte_data_sun_xt; 2052 update_dte_from_pl2 = true; 2053 } else { 2054 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2055 return; 2056 } 2057 2058 ni_pi->enable_power_containment = false; 2059 ni_pi->enable_cac = false; 2060 ni_pi->enable_sq_ramping = false; 2061 si_pi->enable_dte = false; 2062 2063 if (si_pi->powertune_data->enable_powertune_by_default) { 2064 ni_pi->enable_power_containment= true; 2065 ni_pi->enable_cac = true; 2066 if (si_pi->dte_data.enable_dte_by_default) { 2067 si_pi->enable_dte = true; 2068 if (update_dte_from_pl2) 2069 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2070 2071 } 2072 ni_pi->enable_sq_ramping = true; 2073 } 2074 2075 ni_pi->driver_calculate_cac_leakage = true; 2076 ni_pi->cac_configuration_required = true; 2077 2078 if (ni_pi->cac_configuration_required) { 2079 ni_pi->support_cac_long_term_average = true; 2080 si_pi->dyn_powertune_data.l2_lta_window_size = 2081 si_pi->powertune_data->l2_lta_window_size_default; 2082 si_pi->dyn_powertune_data.lts_truncate = 2083 si_pi->powertune_data->lts_truncate_default; 2084 } else { 2085 ni_pi->support_cac_long_term_average = false; 2086 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2087 si_pi->dyn_powertune_data.lts_truncate = 0; 2088 } 2089 2090 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2091 } 2092 2093 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2094 { 2095 return 1; 2096 } 2097 2098 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2099 { 2100 u32 xclk; 2101 u32 wintime; 2102 u32 cac_window; 2103 u32 cac_window_size; 2104 2105 xclk = radeon_get_xclk(rdev); 2106 2107 if (xclk == 0) 2108 return 0; 2109 2110 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2111 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2112 2113 wintime = (cac_window_size * 100) / xclk; 2114 2115 return wintime; 2116 } 2117 2118 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2119 { 2120 return power_in_watts; 2121 } 2122 2123 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2124 bool adjust_polarity, 2125 u32 tdp_adjustment, 2126 u32 *tdp_limit, 2127 u32 *near_tdp_limit) 2128 { 2129 u32 adjustment_delta, max_tdp_limit; 2130 2131 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2132 return -EINVAL; 2133 2134 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2135 2136 if (adjust_polarity) { 2137 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2138 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2139 } else { 2140 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2141 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2142 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2143 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2144 else 2145 *near_tdp_limit = 0; 2146 } 2147 2148 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2149 return -EINVAL; 2150 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2151 return -EINVAL; 2152 2153 return 0; 2154 } 2155 2156 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2157 struct radeon_ps *radeon_state) 2158 { 2159 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2160 struct si_power_info *si_pi = si_get_pi(rdev); 2161 2162 if (ni_pi->enable_power_containment) { 2163 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2164 PP_SIslands_PAPMParameters *papm_parm; 2165 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2166 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2167 u32 tdp_limit; 2168 u32 near_tdp_limit; 2169 int ret; 2170 2171 if (scaling_factor == 0) 2172 return -EINVAL; 2173 2174 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2175 2176 ret = si_calculate_adjusted_tdp_limits(rdev, 2177 false, /* ??? */ 2178 rdev->pm.dpm.tdp_adjustment, 2179 &tdp_limit, 2180 &near_tdp_limit); 2181 if (ret) 2182 return ret; 2183 2184 smc_table->dpm2Params.TDPLimit = 2185 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2186 smc_table->dpm2Params.NearTDPLimit = 2187 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2188 smc_table->dpm2Params.SafePowerLimit = 2189 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2190 2191 ret = si_copy_bytes_to_smc(rdev, 2192 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2193 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2194 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2195 sizeof(u32) * 3, 2196 si_pi->sram_end); 2197 if (ret) 2198 return ret; 2199 2200 if (si_pi->enable_ppm) { 2201 papm_parm = &si_pi->papm_parm; 2202 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2203 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2204 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2205 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2206 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2207 papm_parm->PlatformPowerLimit = 0xffffffff; 2208 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2209 2210 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2211 (u8 *)papm_parm, 2212 sizeof(PP_SIslands_PAPMParameters), 2213 si_pi->sram_end); 2214 if (ret) 2215 return ret; 2216 } 2217 } 2218 return 0; 2219 } 2220 2221 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2222 struct radeon_ps *radeon_state) 2223 { 2224 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2225 struct si_power_info *si_pi = si_get_pi(rdev); 2226 2227 if (ni_pi->enable_power_containment) { 2228 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2229 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2230 int ret; 2231 2232 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2233 2234 smc_table->dpm2Params.NearTDPLimit = 2235 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2236 smc_table->dpm2Params.SafePowerLimit = 2237 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2238 2239 ret = si_copy_bytes_to_smc(rdev, 2240 (si_pi->state_table_start + 2241 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2242 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2243 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2244 sizeof(u32) * 2, 2245 si_pi->sram_end); 2246 if (ret) 2247 return ret; 2248 } 2249 2250 return 0; 2251 } 2252 2253 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2254 const u16 prev_std_vddc, 2255 const u16 curr_std_vddc) 2256 { 2257 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2258 u64 prev_vddc = (u64)prev_std_vddc; 2259 u64 curr_vddc = (u64)curr_std_vddc; 2260 u64 pwr_efficiency_ratio, n, d; 2261 2262 if ((prev_vddc == 0) || (curr_vddc == 0)) 2263 return 0; 2264 2265 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2266 d = prev_vddc * prev_vddc; 2267 pwr_efficiency_ratio = div64_u64(n, d); 2268 2269 if (pwr_efficiency_ratio > (u64)0xFFFF) 2270 return 0; 2271 2272 return (u16)pwr_efficiency_ratio; 2273 } 2274 2275 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2276 struct radeon_ps *radeon_state) 2277 { 2278 struct si_power_info *si_pi = si_get_pi(rdev); 2279 2280 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2281 radeon_state->vclk && radeon_state->dclk) 2282 return true; 2283 2284 return false; 2285 } 2286 2287 static int si_populate_power_containment_values(struct radeon_device *rdev, 2288 struct radeon_ps *radeon_state, 2289 SISLANDS_SMC_SWSTATE *smc_state) 2290 { 2291 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2292 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2293 struct ni_ps *state = ni_get_ps(radeon_state); 2294 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2295 u32 prev_sclk; 2296 u32 max_sclk; 2297 u32 min_sclk; 2298 u16 prev_std_vddc; 2299 u16 curr_std_vddc; 2300 int i; 2301 u16 pwr_efficiency_ratio; 2302 u8 max_ps_percent; 2303 bool disable_uvd_power_tune; 2304 int ret; 2305 2306 if (ni_pi->enable_power_containment == false) 2307 return 0; 2308 2309 if (state->performance_level_count == 0) 2310 return -EINVAL; 2311 2312 if (smc_state->levelCount != state->performance_level_count) 2313 return -EINVAL; 2314 2315 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2316 2317 smc_state->levels[0].dpm2.MaxPS = 0; 2318 smc_state->levels[0].dpm2.NearTDPDec = 0; 2319 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2320 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2321 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2322 2323 for (i = 1; i < state->performance_level_count; i++) { 2324 prev_sclk = state->performance_levels[i-1].sclk; 2325 max_sclk = state->performance_levels[i].sclk; 2326 if (i == 1) 2327 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2328 else 2329 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2330 2331 if (prev_sclk > max_sclk) 2332 return -EINVAL; 2333 2334 if ((max_ps_percent == 0) || 2335 (prev_sclk == max_sclk) || 2336 disable_uvd_power_tune) { 2337 min_sclk = max_sclk; 2338 } else if (i == 1) { 2339 min_sclk = prev_sclk; 2340 } else { 2341 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2342 } 2343 2344 if (min_sclk < state->performance_levels[0].sclk) 2345 min_sclk = state->performance_levels[0].sclk; 2346 2347 if (min_sclk == 0) 2348 return -EINVAL; 2349 2350 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2351 state->performance_levels[i-1].vddc, &vddc); 2352 if (ret) 2353 return ret; 2354 2355 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2356 if (ret) 2357 return ret; 2358 2359 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2360 state->performance_levels[i].vddc, &vddc); 2361 if (ret) 2362 return ret; 2363 2364 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2365 if (ret) 2366 return ret; 2367 2368 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2369 prev_std_vddc, curr_std_vddc); 2370 2371 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2372 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2373 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2374 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2375 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2376 } 2377 2378 return 0; 2379 } 2380 2381 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2382 struct radeon_ps *radeon_state, 2383 SISLANDS_SMC_SWSTATE *smc_state) 2384 { 2385 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2386 struct ni_ps *state = ni_get_ps(radeon_state); 2387 u32 sq_power_throttle, sq_power_throttle2; 2388 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2389 int i; 2390 2391 if (state->performance_level_count == 0) 2392 return -EINVAL; 2393 2394 if (smc_state->levelCount != state->performance_level_count) 2395 return -EINVAL; 2396 2397 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2398 return -EINVAL; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2410 enable_sq_ramping = false; 2411 2412 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2413 enable_sq_ramping = false; 2414 2415 for (i = 0; i < state->performance_level_count; i++) { 2416 sq_power_throttle = 0; 2417 sq_power_throttle2 = 0; 2418 2419 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2420 enable_sq_ramping) { 2421 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2422 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2423 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2424 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2425 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2426 } else { 2427 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2428 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2429 } 2430 2431 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2432 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2433 } 2434 2435 return 0; 2436 } 2437 2438 static int si_enable_power_containment(struct radeon_device *rdev, 2439 struct radeon_ps *radeon_new_state, 2440 bool enable) 2441 { 2442 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2443 PPSMC_Result smc_result; 2444 int ret = 0; 2445 2446 if (ni_pi->enable_power_containment) { 2447 if (enable) { 2448 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2449 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2450 if (smc_result != PPSMC_Result_OK) { 2451 ret = -EINVAL; 2452 ni_pi->pc_enabled = false; 2453 } else { 2454 ni_pi->pc_enabled = true; 2455 } 2456 } 2457 } else { 2458 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2459 if (smc_result != PPSMC_Result_OK) 2460 ret = -EINVAL; 2461 ni_pi->pc_enabled = false; 2462 } 2463 } 2464 2465 return ret; 2466 } 2467 2468 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2469 { 2470 struct si_power_info *si_pi = si_get_pi(rdev); 2471 int ret = 0; 2472 struct si_dte_data *dte_data = &si_pi->dte_data; 2473 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2474 u32 table_size; 2475 u8 tdep_count; 2476 u32 i; 2477 2478 if (dte_data == NULL) 2479 si_pi->enable_dte = false; 2480 2481 if (si_pi->enable_dte == false) 2482 return 0; 2483 2484 if (dte_data->k <= 0) 2485 return -EINVAL; 2486 2487 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2488 if (dte_tables == NULL) { 2489 si_pi->enable_dte = false; 2490 return -ENOMEM; 2491 } 2492 2493 table_size = dte_data->k; 2494 2495 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2496 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2497 2498 tdep_count = dte_data->tdep_count; 2499 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2500 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2501 2502 dte_tables->K = cpu_to_be32(table_size); 2503 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2504 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2505 dte_tables->WindowSize = dte_data->window_size; 2506 dte_tables->temp_select = dte_data->temp_select; 2507 dte_tables->DTE_mode = dte_data->dte_mode; 2508 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2509 2510 if (tdep_count > 0) 2511 table_size--; 2512 2513 for (i = 0; i < table_size; i++) { 2514 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2515 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2516 } 2517 2518 dte_tables->Tdep_count = tdep_count; 2519 2520 for (i = 0; i < (u32)tdep_count; i++) { 2521 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2522 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2523 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2524 } 2525 2526 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2527 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2528 kfree(dte_tables); 2529 2530 return ret; 2531 } 2532 2533 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2534 u16 *max, u16 *min) 2535 { 2536 struct si_power_info *si_pi = si_get_pi(rdev); 2537 struct radeon_cac_leakage_table *table = 2538 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2539 u32 i; 2540 u32 v0_loadline; 2541 2542 2543 if (table == NULL) 2544 return -EINVAL; 2545 2546 *max = 0; 2547 *min = 0xFFFF; 2548 2549 for (i = 0; i < table->count; i++) { 2550 if (table->entries[i].vddc > *max) 2551 *max = table->entries[i].vddc; 2552 if (table->entries[i].vddc < *min) 2553 *min = table->entries[i].vddc; 2554 } 2555 2556 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2557 return -EINVAL; 2558 2559 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2560 2561 if (v0_loadline > 0xFFFFUL) 2562 return -EINVAL; 2563 2564 *min = (u16)v0_loadline; 2565 2566 if ((*min > *max) || (*max == 0) || (*min == 0)) 2567 return -EINVAL; 2568 2569 return 0; 2570 } 2571 2572 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2573 { 2574 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2575 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2576 } 2577 2578 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2579 PP_SIslands_CacConfig *cac_tables, 2580 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2581 u16 t0, u16 t_step) 2582 { 2583 struct si_power_info *si_pi = si_get_pi(rdev); 2584 u32 leakage; 2585 unsigned int i, j; 2586 s32 t; 2587 u32 smc_leakage; 2588 u32 scaling_factor; 2589 u16 voltage; 2590 2591 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2592 2593 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2594 t = (1000 * (i * t_step + t0)); 2595 2596 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2597 voltage = vddc_max - (vddc_step * j); 2598 2599 si_calculate_leakage_for_v_and_t(rdev, 2600 &si_pi->powertune_data->leakage_coefficients, 2601 voltage, 2602 t, 2603 si_pi->dyn_powertune_data.cac_leakage, 2604 &leakage); 2605 2606 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2607 2608 if (smc_leakage > 0xFFFF) 2609 smc_leakage = 0xFFFF; 2610 2611 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2612 cpu_to_be16((u16)smc_leakage); 2613 } 2614 } 2615 return 0; 2616 } 2617 2618 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2619 PP_SIslands_CacConfig *cac_tables, 2620 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2621 { 2622 struct si_power_info *si_pi = si_get_pi(rdev); 2623 u32 leakage; 2624 unsigned int i, j; 2625 u32 smc_leakage; 2626 u32 scaling_factor; 2627 u16 voltage; 2628 2629 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2630 2631 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2632 voltage = vddc_max - (vddc_step * j); 2633 2634 si_calculate_leakage_for_v(rdev, 2635 &si_pi->powertune_data->leakage_coefficients, 2636 si_pi->powertune_data->fixed_kt, 2637 voltage, 2638 si_pi->dyn_powertune_data.cac_leakage, 2639 &leakage); 2640 2641 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2642 2643 if (smc_leakage > 0xFFFF) 2644 smc_leakage = 0xFFFF; 2645 2646 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2647 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2648 cpu_to_be16((u16)smc_leakage); 2649 } 2650 return 0; 2651 } 2652 2653 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2654 { 2655 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2656 struct si_power_info *si_pi = si_get_pi(rdev); 2657 PP_SIslands_CacConfig *cac_tables = NULL; 2658 u16 vddc_max, vddc_min, vddc_step; 2659 u16 t0, t_step; 2660 u32 load_line_slope, reg; 2661 int ret = 0; 2662 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2663 2664 if (ni_pi->enable_cac == false) 2665 return 0; 2666 2667 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2668 if (!cac_tables) 2669 return -ENOMEM; 2670 2671 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2672 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2673 WREG32(CG_CAC_CTRL, reg); 2674 2675 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2676 si_pi->dyn_powertune_data.dc_pwr_value = 2677 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2678 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2679 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2680 2681 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2682 2683 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2684 if (ret) 2685 goto done_free; 2686 2687 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2688 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2689 t_step = 4; 2690 t0 = 60; 2691 2692 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2693 ret = si_init_dte_leakage_table(rdev, cac_tables, 2694 vddc_max, vddc_min, vddc_step, 2695 t0, t_step); 2696 else 2697 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2698 vddc_max, vddc_min, vddc_step); 2699 if (ret) 2700 goto done_free; 2701 2702 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2703 2704 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2705 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2706 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2707 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2708 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2709 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2710 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2711 cac_tables->calculation_repeats = cpu_to_be32(2); 2712 cac_tables->dc_cac = cpu_to_be32(0); 2713 cac_tables->log2_PG_LKG_SCALE = 12; 2714 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2715 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2716 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2717 2718 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2719 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2720 2721 if (ret) 2722 goto done_free; 2723 2724 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2725 2726 done_free: 2727 if (ret) { 2728 ni_pi->enable_cac = false; 2729 ni_pi->enable_power_containment = false; 2730 } 2731 2732 kfree(cac_tables); 2733 2734 return 0; 2735 } 2736 2737 static int si_program_cac_config_registers(struct radeon_device *rdev, 2738 const struct si_cac_config_reg *cac_config_regs) 2739 { 2740 const struct si_cac_config_reg *config_regs = cac_config_regs; 2741 u32 data = 0, offset; 2742 2743 if (!config_regs) 2744 return -EINVAL; 2745 2746 while (config_regs->offset != 0xFFFFFFFF) { 2747 switch (config_regs->type) { 2748 case SISLANDS_CACCONFIG_CGIND: 2749 offset = SMC_CG_IND_START + config_regs->offset; 2750 if (offset < SMC_CG_IND_END) 2751 data = RREG32_SMC(offset); 2752 break; 2753 default: 2754 data = RREG32(config_regs->offset << 2); 2755 break; 2756 } 2757 2758 data &= ~config_regs->mask; 2759 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2760 2761 switch (config_regs->type) { 2762 case SISLANDS_CACCONFIG_CGIND: 2763 offset = SMC_CG_IND_START + config_regs->offset; 2764 if (offset < SMC_CG_IND_END) 2765 WREG32_SMC(offset, data); 2766 break; 2767 default: 2768 WREG32(config_regs->offset << 2, data); 2769 break; 2770 } 2771 config_regs++; 2772 } 2773 return 0; 2774 } 2775 2776 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2777 { 2778 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2779 struct si_power_info *si_pi = si_get_pi(rdev); 2780 int ret; 2781 2782 if ((ni_pi->enable_cac == false) || 2783 (ni_pi->cac_configuration_required == false)) 2784 return 0; 2785 2786 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2787 if (ret) 2788 return ret; 2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2790 if (ret) 2791 return ret; 2792 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2793 if (ret) 2794 return ret; 2795 2796 return 0; 2797 } 2798 2799 static int si_enable_smc_cac(struct radeon_device *rdev, 2800 struct radeon_ps *radeon_new_state, 2801 bool enable) 2802 { 2803 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2804 struct si_power_info *si_pi = si_get_pi(rdev); 2805 PPSMC_Result smc_result; 2806 int ret = 0; 2807 2808 if (ni_pi->enable_cac) { 2809 if (enable) { 2810 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2811 if (ni_pi->support_cac_long_term_average) { 2812 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2813 if (smc_result != PPSMC_Result_OK) 2814 ni_pi->support_cac_long_term_average = false; 2815 } 2816 2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2818 if (smc_result != PPSMC_Result_OK) { 2819 ret = -EINVAL; 2820 ni_pi->cac_enabled = false; 2821 } else { 2822 ni_pi->cac_enabled = true; 2823 } 2824 2825 if (si_pi->enable_dte) { 2826 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2827 if (smc_result != PPSMC_Result_OK) 2828 ret = -EINVAL; 2829 } 2830 } 2831 } else if (ni_pi->cac_enabled) { 2832 if (si_pi->enable_dte) 2833 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2834 2835 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2836 2837 ni_pi->cac_enabled = false; 2838 2839 if (ni_pi->support_cac_long_term_average) 2840 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2841 } 2842 } 2843 return ret; 2844 } 2845 2846 static int si_init_smc_spll_table(struct radeon_device *rdev) 2847 { 2848 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2849 struct si_power_info *si_pi = si_get_pi(rdev); 2850 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2851 SISLANDS_SMC_SCLK_VALUE sclk_params; 2852 u32 fb_div, p_div; 2853 u32 clk_s, clk_v; 2854 u32 sclk = 0; 2855 int ret = 0; 2856 u32 tmp; 2857 int i; 2858 2859 if (si_pi->spll_table_start == 0) 2860 return -EINVAL; 2861 2862 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2863 if (spll_table == NULL) 2864 return -ENOMEM; 2865 2866 for (i = 0; i < 256; i++) { 2867 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2868 if (ret) 2869 break; 2870 2871 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2872 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2873 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2874 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2875 2876 fb_div &= ~0x00001FFF; 2877 fb_div >>= 1; 2878 clk_v >>= 6; 2879 2880 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2881 ret = -EINVAL; 2882 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2883 ret = -EINVAL; 2884 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2885 ret = -EINVAL; 2886 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2887 ret = -EINVAL; 2888 2889 if (ret) 2890 break; 2891 2892 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2893 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2894 spll_table->freq[i] = cpu_to_be32(tmp); 2895 2896 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2897 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2898 spll_table->ss[i] = cpu_to_be32(tmp); 2899 2900 sclk += 512; 2901 } 2902 2903 2904 if (!ret) 2905 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2906 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2907 si_pi->sram_end); 2908 2909 if (ret) 2910 ni_pi->enable_power_containment = false; 2911 2912 kfree(spll_table); 2913 2914 return ret; 2915 } 2916 2917 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2918 u16 vce_voltage) 2919 { 2920 u16 highest_leakage = 0; 2921 struct si_power_info *si_pi = si_get_pi(rdev); 2922 int i; 2923 2924 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2925 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2926 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2927 } 2928 2929 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2930 return highest_leakage; 2931 2932 return vce_voltage; 2933 } 2934 2935 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2936 u32 evclk, u32 ecclk, u16 *voltage) 2937 { 2938 u32 i; 2939 int ret = -EINVAL; 2940 struct radeon_vce_clock_voltage_dependency_table *table = 2941 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2942 2943 if (((evclk == 0) && (ecclk == 0)) || 2944 (table && (table->count == 0))) { 2945 *voltage = 0; 2946 return 0; 2947 } 2948 2949 for (i = 0; i < table->count; i++) { 2950 if ((evclk <= table->entries[i].evclk) && 2951 (ecclk <= table->entries[i].ecclk)) { 2952 *voltage = table->entries[i].v; 2953 ret = 0; 2954 break; 2955 } 2956 } 2957 2958 /* if no match return the highest voltage */ 2959 if (ret) 2960 *voltage = table->entries[table->count - 1].v; 2961 2962 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2963 2964 return ret; 2965 } 2966 2967 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2968 struct radeon_ps *rps) 2969 { 2970 struct ni_ps *ps = ni_get_ps(rps); 2971 struct radeon_clock_and_voltage_limits *max_limits; 2972 bool disable_mclk_switching = false; 2973 bool disable_sclk_switching = false; 2974 u32 mclk, sclk; 2975 u16 vddc, vddci, min_vce_voltage = 0; 2976 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2977 u32 max_sclk = 0, max_mclk = 0; 2978 int i; 2979 2980 if (rdev->family == CHIP_HAINAN) { 2981 if ((rdev->pdev->revision == 0x81) || 2982 (rdev->pdev->revision == 0x83) || 2983 (rdev->pdev->revision == 0xC3) || 2984 (rdev->pdev->device == 0x6664) || 2985 (rdev->pdev->device == 0x6665) || 2986 (rdev->pdev->device == 0x6667)) { 2987 max_sclk = 75000; 2988 } 2989 if ((rdev->pdev->revision == 0xC3) || 2990 (rdev->pdev->device == 0x6665)) { 2991 max_sclk = 60000; 2992 max_mclk = 80000; 2993 } 2994 } else if (rdev->family == CHIP_OLAND) { 2995 if ((rdev->pdev->revision == 0xC7) || 2996 (rdev->pdev->revision == 0x80) || 2997 (rdev->pdev->revision == 0x81) || 2998 (rdev->pdev->revision == 0x83) || 2999 (rdev->pdev->revision == 0x87) || 3000 (rdev->pdev->device == 0x6604) || 3001 (rdev->pdev->device == 0x6605)) { 3002 max_sclk = 75000; 3003 } 3004 } 3005 3006 if (rps->vce_active) { 3007 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3008 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3009 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3010 &min_vce_voltage); 3011 } else { 3012 rps->evclk = 0; 3013 rps->ecclk = 0; 3014 } 3015 3016 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3017 ni_dpm_vblank_too_short(rdev)) 3018 disable_mclk_switching = true; 3019 3020 if (rps->vclk || rps->dclk) { 3021 disable_mclk_switching = true; 3022 disable_sclk_switching = true; 3023 } 3024 3025 if (rdev->pm.dpm.ac_power) 3026 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3027 else 3028 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3029 3030 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3031 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3032 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3033 } 3034 if (rdev->pm.dpm.ac_power == false) { 3035 for (i = 0; i < ps->performance_level_count; i++) { 3036 if (ps->performance_levels[i].mclk > max_limits->mclk) 3037 ps->performance_levels[i].mclk = max_limits->mclk; 3038 if (ps->performance_levels[i].sclk > max_limits->sclk) 3039 ps->performance_levels[i].sclk = max_limits->sclk; 3040 if (ps->performance_levels[i].vddc > max_limits->vddc) 3041 ps->performance_levels[i].vddc = max_limits->vddc; 3042 if (ps->performance_levels[i].vddci > max_limits->vddci) 3043 ps->performance_levels[i].vddci = max_limits->vddci; 3044 } 3045 } 3046 3047 /* limit clocks to max supported clocks based on voltage dependency tables */ 3048 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3049 &max_sclk_vddc); 3050 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3051 &max_mclk_vddci); 3052 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3053 &max_mclk_vddc); 3054 3055 for (i = 0; i < ps->performance_level_count; i++) { 3056 if (max_sclk_vddc) { 3057 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3058 ps->performance_levels[i].sclk = max_sclk_vddc; 3059 } 3060 if (max_mclk_vddci) { 3061 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3062 ps->performance_levels[i].mclk = max_mclk_vddci; 3063 } 3064 if (max_mclk_vddc) { 3065 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3066 ps->performance_levels[i].mclk = max_mclk_vddc; 3067 } 3068 if (max_mclk) { 3069 if (ps->performance_levels[i].mclk > max_mclk) 3070 ps->performance_levels[i].mclk = max_mclk; 3071 } 3072 if (max_sclk) { 3073 if (ps->performance_levels[i].sclk > max_sclk) 3074 ps->performance_levels[i].sclk = max_sclk; 3075 } 3076 } 3077 3078 /* XXX validate the min clocks required for display */ 3079 3080 if (disable_mclk_switching) { 3081 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3082 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3083 } else { 3084 mclk = ps->performance_levels[0].mclk; 3085 vddci = ps->performance_levels[0].vddci; 3086 } 3087 3088 if (disable_sclk_switching) { 3089 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3090 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3091 } else { 3092 sclk = ps->performance_levels[0].sclk; 3093 vddc = ps->performance_levels[0].vddc; 3094 } 3095 3096 if (rps->vce_active) { 3097 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3098 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3099 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3100 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3101 } 3102 3103 /* adjusted low state */ 3104 ps->performance_levels[0].sclk = sclk; 3105 ps->performance_levels[0].mclk = mclk; 3106 ps->performance_levels[0].vddc = vddc; 3107 ps->performance_levels[0].vddci = vddci; 3108 3109 if (disable_sclk_switching) { 3110 sclk = ps->performance_levels[0].sclk; 3111 for (i = 1; i < ps->performance_level_count; i++) { 3112 if (sclk < ps->performance_levels[i].sclk) 3113 sclk = ps->performance_levels[i].sclk; 3114 } 3115 for (i = 0; i < ps->performance_level_count; i++) { 3116 ps->performance_levels[i].sclk = sclk; 3117 ps->performance_levels[i].vddc = vddc; 3118 } 3119 } else { 3120 for (i = 1; i < ps->performance_level_count; i++) { 3121 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3122 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3123 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3124 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3125 } 3126 } 3127 3128 if (disable_mclk_switching) { 3129 mclk = ps->performance_levels[0].mclk; 3130 for (i = 1; i < ps->performance_level_count; i++) { 3131 if (mclk < ps->performance_levels[i].mclk) 3132 mclk = ps->performance_levels[i].mclk; 3133 } 3134 for (i = 0; i < ps->performance_level_count; i++) { 3135 ps->performance_levels[i].mclk = mclk; 3136 ps->performance_levels[i].vddci = vddci; 3137 } 3138 } else { 3139 for (i = 1; i < ps->performance_level_count; i++) { 3140 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3141 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3142 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3143 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3144 } 3145 } 3146 3147 for (i = 0; i < ps->performance_level_count; i++) 3148 btc_adjust_clock_combinations(rdev, max_limits, 3149 &ps->performance_levels[i]); 3150 3151 for (i = 0; i < ps->performance_level_count; i++) { 3152 if (ps->performance_levels[i].vddc < min_vce_voltage) 3153 ps->performance_levels[i].vddc = min_vce_voltage; 3154 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3155 ps->performance_levels[i].sclk, 3156 max_limits->vddc, &ps->performance_levels[i].vddc); 3157 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3158 ps->performance_levels[i].mclk, 3159 max_limits->vddci, &ps->performance_levels[i].vddci); 3160 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3161 ps->performance_levels[i].mclk, 3162 max_limits->vddc, &ps->performance_levels[i].vddc); 3163 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3164 rdev->clock.current_dispclk, 3165 max_limits->vddc, &ps->performance_levels[i].vddc); 3166 } 3167 3168 for (i = 0; i < ps->performance_level_count; i++) { 3169 btc_apply_voltage_delta_rules(rdev, 3170 max_limits->vddc, max_limits->vddci, 3171 &ps->performance_levels[i].vddc, 3172 &ps->performance_levels[i].vddci); 3173 } 3174 3175 ps->dc_compatible = true; 3176 for (i = 0; i < ps->performance_level_count; i++) { 3177 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3178 ps->dc_compatible = false; 3179 } 3180 } 3181 3182 #if 0 3183 static int si_read_smc_soft_register(struct radeon_device *rdev, 3184 u16 reg_offset, u32 *value) 3185 { 3186 struct si_power_info *si_pi = si_get_pi(rdev); 3187 3188 return si_read_smc_sram_dword(rdev, 3189 si_pi->soft_regs_start + reg_offset, value, 3190 si_pi->sram_end); 3191 } 3192 #endif 3193 3194 static int si_write_smc_soft_register(struct radeon_device *rdev, 3195 u16 reg_offset, u32 value) 3196 { 3197 struct si_power_info *si_pi = si_get_pi(rdev); 3198 3199 return si_write_smc_sram_dword(rdev, 3200 si_pi->soft_regs_start + reg_offset, 3201 value, si_pi->sram_end); 3202 } 3203 3204 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3205 { 3206 bool ret = false; 3207 u32 tmp, width, row, column, bank, density; 3208 bool is_memory_gddr5, is_special; 3209 3210 tmp = RREG32(MC_SEQ_MISC0); 3211 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3212 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3213 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3214 3215 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3216 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3217 3218 tmp = RREG32(MC_ARB_RAMCFG); 3219 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3220 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3221 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3222 3223 density = (1 << (row + column - 20 + bank)) * width; 3224 3225 if ((rdev->pdev->device == 0x6819) && 3226 is_memory_gddr5 && is_special && (density == 0x400)) 3227 ret = true; 3228 3229 return ret; 3230 } 3231 3232 static void si_get_leakage_vddc(struct radeon_device *rdev) 3233 { 3234 struct si_power_info *si_pi = si_get_pi(rdev); 3235 u16 vddc, count = 0; 3236 int i, ret; 3237 3238 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3239 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3240 3241 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3242 si_pi->leakage_voltage.entries[count].voltage = vddc; 3243 si_pi->leakage_voltage.entries[count].leakage_index = 3244 SISLANDS_LEAKAGE_INDEX0 + i; 3245 count++; 3246 } 3247 } 3248 si_pi->leakage_voltage.count = count; 3249 } 3250 3251 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3252 u32 index, u16 *leakage_voltage) 3253 { 3254 struct si_power_info *si_pi = si_get_pi(rdev); 3255 int i; 3256 3257 if (leakage_voltage == NULL) 3258 return -EINVAL; 3259 3260 if ((index & 0xff00) != 0xff00) 3261 return -EINVAL; 3262 3263 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3264 return -EINVAL; 3265 3266 if (index < SISLANDS_LEAKAGE_INDEX0) 3267 return -EINVAL; 3268 3269 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3270 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3271 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3272 return 0; 3273 } 3274 } 3275 return -EAGAIN; 3276 } 3277 3278 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3279 { 3280 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3281 bool want_thermal_protection; 3282 enum radeon_dpm_event_src dpm_event_src; 3283 3284 switch (sources) { 3285 case 0: 3286 default: 3287 want_thermal_protection = false; 3288 break; 3289 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3290 want_thermal_protection = true; 3291 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3292 break; 3293 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3294 want_thermal_protection = true; 3295 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3296 break; 3297 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3298 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3299 want_thermal_protection = true; 3300 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3301 break; 3302 } 3303 3304 if (want_thermal_protection) { 3305 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3306 if (pi->thermal_protection) 3307 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3308 } else { 3309 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3310 } 3311 } 3312 3313 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3314 enum radeon_dpm_auto_throttle_src source, 3315 bool enable) 3316 { 3317 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3318 3319 if (enable) { 3320 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3321 pi->active_auto_throttle_sources |= 1 << source; 3322 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3323 } 3324 } else { 3325 if (pi->active_auto_throttle_sources & (1 << source)) { 3326 pi->active_auto_throttle_sources &= ~(1 << source); 3327 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3328 } 3329 } 3330 } 3331 3332 static void si_start_dpm(struct radeon_device *rdev) 3333 { 3334 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3335 } 3336 3337 static void si_stop_dpm(struct radeon_device *rdev) 3338 { 3339 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3340 } 3341 3342 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3343 { 3344 if (enable) 3345 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3346 else 3347 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3348 3349 } 3350 3351 #if 0 3352 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3353 u32 thermal_level) 3354 { 3355 PPSMC_Result ret; 3356 3357 if (thermal_level == 0) { 3358 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3359 if (ret == PPSMC_Result_OK) 3360 return 0; 3361 else 3362 return -EINVAL; 3363 } 3364 return 0; 3365 } 3366 3367 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3368 { 3369 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3370 } 3371 #endif 3372 3373 #if 0 3374 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3375 { 3376 if (ac_power) 3377 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3378 0 : -EINVAL; 3379 3380 return 0; 3381 } 3382 #endif 3383 3384 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3385 PPSMC_Msg msg, u32 parameter) 3386 { 3387 WREG32(SMC_SCRATCH0, parameter); 3388 return si_send_msg_to_smc(rdev, msg); 3389 } 3390 3391 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3392 { 3393 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3394 return -EINVAL; 3395 3396 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3397 0 : -EINVAL; 3398 } 3399 3400 int si_dpm_force_performance_level(struct radeon_device *rdev, 3401 enum radeon_dpm_forced_level level) 3402 { 3403 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3404 struct ni_ps *ps = ni_get_ps(rps); 3405 u32 levels = ps->performance_level_count; 3406 3407 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3408 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3409 return -EINVAL; 3410 3411 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3412 return -EINVAL; 3413 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3414 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3415 return -EINVAL; 3416 3417 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3418 return -EINVAL; 3419 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3420 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3421 return -EINVAL; 3422 3423 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3424 return -EINVAL; 3425 } 3426 3427 rdev->pm.dpm.forced_level = level; 3428 3429 return 0; 3430 } 3431 3432 #if 0 3433 static int si_set_boot_state(struct radeon_device *rdev) 3434 { 3435 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3436 0 : -EINVAL; 3437 } 3438 #endif 3439 3440 static int si_set_sw_state(struct radeon_device *rdev) 3441 { 3442 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3443 0 : -EINVAL; 3444 } 3445 3446 static int si_halt_smc(struct radeon_device *rdev) 3447 { 3448 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3449 return -EINVAL; 3450 3451 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3452 0 : -EINVAL; 3453 } 3454 3455 static int si_resume_smc(struct radeon_device *rdev) 3456 { 3457 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3458 return -EINVAL; 3459 3460 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3461 0 : -EINVAL; 3462 } 3463 3464 static void si_dpm_start_smc(struct radeon_device *rdev) 3465 { 3466 si_program_jump_on_start(rdev); 3467 si_start_smc(rdev); 3468 si_start_smc_clock(rdev); 3469 } 3470 3471 static void si_dpm_stop_smc(struct radeon_device *rdev) 3472 { 3473 si_reset_smc(rdev); 3474 si_stop_smc_clock(rdev); 3475 } 3476 3477 static int si_process_firmware_header(struct radeon_device *rdev) 3478 { 3479 struct si_power_info *si_pi = si_get_pi(rdev); 3480 u32 tmp; 3481 int ret; 3482 3483 ret = si_read_smc_sram_dword(rdev, 3484 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3485 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3486 &tmp, si_pi->sram_end); 3487 if (ret) 3488 return ret; 3489 3490 si_pi->state_table_start = tmp; 3491 3492 ret = si_read_smc_sram_dword(rdev, 3493 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3494 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3495 &tmp, si_pi->sram_end); 3496 if (ret) 3497 return ret; 3498 3499 si_pi->soft_regs_start = tmp; 3500 3501 ret = si_read_smc_sram_dword(rdev, 3502 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3503 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3504 &tmp, si_pi->sram_end); 3505 if (ret) 3506 return ret; 3507 3508 si_pi->mc_reg_table_start = tmp; 3509 3510 ret = si_read_smc_sram_dword(rdev, 3511 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3512 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3513 &tmp, si_pi->sram_end); 3514 if (ret) 3515 return ret; 3516 3517 si_pi->fan_table_start = tmp; 3518 3519 ret = si_read_smc_sram_dword(rdev, 3520 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3521 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3522 &tmp, si_pi->sram_end); 3523 if (ret) 3524 return ret; 3525 3526 si_pi->arb_table_start = tmp; 3527 3528 ret = si_read_smc_sram_dword(rdev, 3529 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3530 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3531 &tmp, si_pi->sram_end); 3532 if (ret) 3533 return ret; 3534 3535 si_pi->cac_table_start = tmp; 3536 3537 ret = si_read_smc_sram_dword(rdev, 3538 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3539 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3540 &tmp, si_pi->sram_end); 3541 if (ret) 3542 return ret; 3543 3544 si_pi->dte_table_start = tmp; 3545 3546 ret = si_read_smc_sram_dword(rdev, 3547 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3548 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3549 &tmp, si_pi->sram_end); 3550 if (ret) 3551 return ret; 3552 3553 si_pi->spll_table_start = tmp; 3554 3555 ret = si_read_smc_sram_dword(rdev, 3556 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3557 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3558 &tmp, si_pi->sram_end); 3559 if (ret) 3560 return ret; 3561 3562 si_pi->papm_cfg_table_start = tmp; 3563 3564 return ret; 3565 } 3566 3567 static void si_read_clock_registers(struct radeon_device *rdev) 3568 { 3569 struct si_power_info *si_pi = si_get_pi(rdev); 3570 3571 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3572 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3573 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3574 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3575 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3576 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3577 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3578 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3579 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3580 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3581 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3582 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3583 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3584 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3585 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3586 } 3587 3588 static void si_enable_thermal_protection(struct radeon_device *rdev, 3589 bool enable) 3590 { 3591 if (enable) 3592 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3593 else 3594 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3595 } 3596 3597 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3598 { 3599 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3600 } 3601 3602 #if 0 3603 static int si_enter_ulp_state(struct radeon_device *rdev) 3604 { 3605 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3606 3607 udelay(25000); 3608 3609 return 0; 3610 } 3611 3612 static int si_exit_ulp_state(struct radeon_device *rdev) 3613 { 3614 int i; 3615 3616 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3617 3618 udelay(7000); 3619 3620 for (i = 0; i < rdev->usec_timeout; i++) { 3621 if (RREG32(SMC_RESP_0) == 1) 3622 break; 3623 udelay(1000); 3624 } 3625 3626 return 0; 3627 } 3628 #endif 3629 3630 static int si_notify_smc_display_change(struct radeon_device *rdev, 3631 bool has_display) 3632 { 3633 PPSMC_Msg msg = has_display ? 3634 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3635 3636 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3637 0 : -EINVAL; 3638 } 3639 3640 static void si_program_response_times(struct radeon_device *rdev) 3641 { 3642 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3643 u32 vddc_dly, acpi_dly, vbi_dly; 3644 u32 reference_clock; 3645 3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3647 3648 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3649 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3650 3651 if (voltage_response_time == 0) 3652 voltage_response_time = 1000; 3653 3654 acpi_delay_time = 15000; 3655 vbi_time_out = 100000; 3656 3657 reference_clock = radeon_get_xclk(rdev); 3658 3659 vddc_dly = (voltage_response_time * reference_clock) / 100; 3660 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3661 vbi_dly = (vbi_time_out * reference_clock) / 100; 3662 3663 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3665 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3666 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3667 } 3668 3669 static void si_program_ds_registers(struct radeon_device *rdev) 3670 { 3671 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3672 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3673 3674 if (eg_pi->sclk_deep_sleep) { 3675 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3676 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3677 ~AUTOSCALE_ON_SS_CLEAR); 3678 } 3679 } 3680 3681 static void si_program_display_gap(struct radeon_device *rdev) 3682 { 3683 u32 tmp, pipe; 3684 int i; 3685 3686 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3687 if (rdev->pm.dpm.new_active_crtc_count > 0) 3688 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3689 else 3690 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3691 3692 if (rdev->pm.dpm.new_active_crtc_count > 1) 3693 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3694 else 3695 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3696 3697 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3698 3699 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3700 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3701 3702 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3703 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3704 /* find the first active crtc */ 3705 for (i = 0; i < rdev->num_crtc; i++) { 3706 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3707 break; 3708 } 3709 if (i == rdev->num_crtc) 3710 pipe = 0; 3711 else 3712 pipe = i; 3713 3714 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3715 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3716 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3717 } 3718 3719 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3720 * This can be a problem on PowerXpress systems or if you want to use the card 3721 * for offscreen rendering or compute if there are no crtcs enabled. 3722 */ 3723 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3724 } 3725 3726 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3727 { 3728 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3729 3730 if (enable) { 3731 if (pi->sclk_ss) 3732 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3733 } else { 3734 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3735 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3736 } 3737 } 3738 3739 static void si_setup_bsp(struct radeon_device *rdev) 3740 { 3741 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3742 u32 xclk = radeon_get_xclk(rdev); 3743 3744 r600_calculate_u_and_p(pi->asi, 3745 xclk, 3746 16, 3747 &pi->bsp, 3748 &pi->bsu); 3749 3750 r600_calculate_u_and_p(pi->pasi, 3751 xclk, 3752 16, 3753 &pi->pbsp, 3754 &pi->pbsu); 3755 3756 3757 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3758 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3759 3760 WREG32(CG_BSP, pi->dsp); 3761 } 3762 3763 static void si_program_git(struct radeon_device *rdev) 3764 { 3765 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3766 } 3767 3768 static void si_program_tp(struct radeon_device *rdev) 3769 { 3770 int i; 3771 enum r600_td td = R600_TD_DFLT; 3772 3773 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3774 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3775 3776 if (td == R600_TD_AUTO) 3777 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3778 else 3779 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3780 3781 if (td == R600_TD_UP) 3782 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3783 3784 if (td == R600_TD_DOWN) 3785 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3786 } 3787 3788 static void si_program_tpp(struct radeon_device *rdev) 3789 { 3790 WREG32(CG_TPC, R600_TPC_DFLT); 3791 } 3792 3793 static void si_program_sstp(struct radeon_device *rdev) 3794 { 3795 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3796 } 3797 3798 static void si_enable_display_gap(struct radeon_device *rdev) 3799 { 3800 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3801 3802 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3803 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3804 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3805 3806 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3807 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3808 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3809 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3810 } 3811 3812 static void si_program_vc(struct radeon_device *rdev) 3813 { 3814 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3815 3816 WREG32(CG_FTV, pi->vrc); 3817 } 3818 3819 static void si_clear_vc(struct radeon_device *rdev) 3820 { 3821 WREG32(CG_FTV, 0); 3822 } 3823 3824 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3825 { 3826 u8 mc_para_index; 3827 3828 if (memory_clock < 10000) 3829 mc_para_index = 0; 3830 else if (memory_clock >= 80000) 3831 mc_para_index = 0x0f; 3832 else 3833 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3834 return mc_para_index; 3835 } 3836 3837 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3838 { 3839 u8 mc_para_index; 3840 3841 if (strobe_mode) { 3842 if (memory_clock < 12500) 3843 mc_para_index = 0x00; 3844 else if (memory_clock > 47500) 3845 mc_para_index = 0x0f; 3846 else 3847 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3848 } else { 3849 if (memory_clock < 65000) 3850 mc_para_index = 0x00; 3851 else if (memory_clock > 135000) 3852 mc_para_index = 0x0f; 3853 else 3854 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3855 } 3856 return mc_para_index; 3857 } 3858 3859 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3860 { 3861 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3862 bool strobe_mode = false; 3863 u8 result = 0; 3864 3865 if (mclk <= pi->mclk_strobe_mode_threshold) 3866 strobe_mode = true; 3867 3868 if (pi->mem_gddr5) 3869 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3870 else 3871 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3872 3873 if (strobe_mode) 3874 result |= SISLANDS_SMC_STROBE_ENABLE; 3875 3876 return result; 3877 } 3878 3879 static int si_upload_firmware(struct radeon_device *rdev) 3880 { 3881 struct si_power_info *si_pi = si_get_pi(rdev); 3882 int ret; 3883 3884 si_reset_smc(rdev); 3885 si_stop_smc_clock(rdev); 3886 3887 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3888 3889 return ret; 3890 } 3891 3892 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3893 const struct atom_voltage_table *table, 3894 const struct radeon_phase_shedding_limits_table *limits) 3895 { 3896 u32 data, num_bits, num_levels; 3897 3898 if ((table == NULL) || (limits == NULL)) 3899 return false; 3900 3901 data = table->mask_low; 3902 3903 num_bits = hweight32(data); 3904 3905 if (num_bits == 0) 3906 return false; 3907 3908 num_levels = (1 << num_bits); 3909 3910 if (table->count != num_levels) 3911 return false; 3912 3913 if (limits->count != (num_levels - 1)) 3914 return false; 3915 3916 return true; 3917 } 3918 3919 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3920 u32 max_voltage_steps, 3921 struct atom_voltage_table *voltage_table) 3922 { 3923 unsigned int i, diff; 3924 3925 if (voltage_table->count <= max_voltage_steps) 3926 return; 3927 3928 diff = voltage_table->count - max_voltage_steps; 3929 3930 for (i= 0; i < max_voltage_steps; i++) 3931 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3932 3933 voltage_table->count = max_voltage_steps; 3934 } 3935 3936 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3937 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3938 struct atom_voltage_table *voltage_table) 3939 { 3940 u32 i; 3941 3942 if (voltage_dependency_table == NULL) 3943 return -EINVAL; 3944 3945 voltage_table->mask_low = 0; 3946 voltage_table->phase_delay = 0; 3947 3948 voltage_table->count = voltage_dependency_table->count; 3949 for (i = 0; i < voltage_table->count; i++) { 3950 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3951 voltage_table->entries[i].smio_low = 0; 3952 } 3953 3954 return 0; 3955 } 3956 3957 static int si_construct_voltage_tables(struct radeon_device *rdev) 3958 { 3959 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3960 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3961 struct si_power_info *si_pi = si_get_pi(rdev); 3962 int ret; 3963 3964 if (pi->voltage_control) { 3965 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3966 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3967 if (ret) 3968 return ret; 3969 3970 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3971 si_trim_voltage_table_to_fit_state_table(rdev, 3972 SISLANDS_MAX_NO_VREG_STEPS, 3973 &eg_pi->vddc_voltage_table); 3974 } else if (si_pi->voltage_control_svi2) { 3975 ret = si_get_svi2_voltage_table(rdev, 3976 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3977 &eg_pi->vddc_voltage_table); 3978 if (ret) 3979 return ret; 3980 } else { 3981 return -EINVAL; 3982 } 3983 3984 if (eg_pi->vddci_control) { 3985 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3986 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3987 if (ret) 3988 return ret; 3989 3990 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3991 si_trim_voltage_table_to_fit_state_table(rdev, 3992 SISLANDS_MAX_NO_VREG_STEPS, 3993 &eg_pi->vddci_voltage_table); 3994 } 3995 if (si_pi->vddci_control_svi2) { 3996 ret = si_get_svi2_voltage_table(rdev, 3997 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3998 &eg_pi->vddci_voltage_table); 3999 if (ret) 4000 return ret; 4001 } 4002 4003 if (pi->mvdd_control) { 4004 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4005 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4006 4007 if (ret) { 4008 pi->mvdd_control = false; 4009 return ret; 4010 } 4011 4012 if (si_pi->mvdd_voltage_table.count == 0) { 4013 pi->mvdd_control = false; 4014 return -EINVAL; 4015 } 4016 4017 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4018 si_trim_voltage_table_to_fit_state_table(rdev, 4019 SISLANDS_MAX_NO_VREG_STEPS, 4020 &si_pi->mvdd_voltage_table); 4021 } 4022 4023 if (si_pi->vddc_phase_shed_control) { 4024 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4025 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4026 if (ret) 4027 si_pi->vddc_phase_shed_control = false; 4028 4029 if ((si_pi->vddc_phase_shed_table.count == 0) || 4030 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4031 si_pi->vddc_phase_shed_control = false; 4032 } 4033 4034 return 0; 4035 } 4036 4037 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4038 const struct atom_voltage_table *voltage_table, 4039 SISLANDS_SMC_STATETABLE *table) 4040 { 4041 unsigned int i; 4042 4043 for (i = 0; i < voltage_table->count; i++) 4044 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4045 } 4046 4047 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4048 SISLANDS_SMC_STATETABLE *table) 4049 { 4050 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4051 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4052 struct si_power_info *si_pi = si_get_pi(rdev); 4053 u8 i; 4054 4055 if (si_pi->voltage_control_svi2) { 4056 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4057 si_pi->svc_gpio_id); 4058 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4059 si_pi->svd_gpio_id); 4060 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4061 2); 4062 } else { 4063 if (eg_pi->vddc_voltage_table.count) { 4064 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4065 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4066 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4067 4068 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4069 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4070 table->maxVDDCIndexInPPTable = i; 4071 break; 4072 } 4073 } 4074 } 4075 4076 if (eg_pi->vddci_voltage_table.count) { 4077 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4078 4079 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4080 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4081 } 4082 4083 4084 if (si_pi->mvdd_voltage_table.count) { 4085 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4086 4087 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4088 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4089 } 4090 4091 if (si_pi->vddc_phase_shed_control) { 4092 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4093 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4094 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4095 4096 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4097 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4098 4099 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4100 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4101 } else { 4102 si_pi->vddc_phase_shed_control = false; 4103 } 4104 } 4105 } 4106 4107 return 0; 4108 } 4109 4110 static int si_populate_voltage_value(struct radeon_device *rdev, 4111 const struct atom_voltage_table *table, 4112 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4113 { 4114 unsigned int i; 4115 4116 for (i = 0; i < table->count; i++) { 4117 if (value <= table->entries[i].value) { 4118 voltage->index = (u8)i; 4119 voltage->value = cpu_to_be16(table->entries[i].value); 4120 break; 4121 } 4122 } 4123 4124 if (i >= table->count) 4125 return -EINVAL; 4126 4127 return 0; 4128 } 4129 4130 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4131 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4132 { 4133 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4134 struct si_power_info *si_pi = si_get_pi(rdev); 4135 4136 if (pi->mvdd_control) { 4137 if (mclk <= pi->mvdd_split_frequency) 4138 voltage->index = 0; 4139 else 4140 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4141 4142 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4143 } 4144 return 0; 4145 } 4146 4147 static int si_get_std_voltage_value(struct radeon_device *rdev, 4148 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4149 u16 *std_voltage) 4150 { 4151 u16 v_index; 4152 bool voltage_found = false; 4153 *std_voltage = be16_to_cpu(voltage->value); 4154 4155 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4156 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4157 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4158 return -EINVAL; 4159 4160 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4161 if (be16_to_cpu(voltage->value) == 4162 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4163 voltage_found = true; 4164 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4165 *std_voltage = 4166 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4167 else 4168 *std_voltage = 4169 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4170 break; 4171 } 4172 } 4173 4174 if (!voltage_found) { 4175 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4176 if (be16_to_cpu(voltage->value) <= 4177 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4178 voltage_found = true; 4179 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4180 *std_voltage = 4181 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4182 else 4183 *std_voltage = 4184 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4185 break; 4186 } 4187 } 4188 } 4189 } else { 4190 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4191 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4192 } 4193 } 4194 4195 return 0; 4196 } 4197 4198 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4199 u16 value, u8 index, 4200 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4201 { 4202 voltage->index = index; 4203 voltage->value = cpu_to_be16(value); 4204 4205 return 0; 4206 } 4207 4208 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4209 const struct radeon_phase_shedding_limits_table *limits, 4210 u16 voltage, u32 sclk, u32 mclk, 4211 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4212 { 4213 unsigned int i; 4214 4215 for (i = 0; i < limits->count; i++) { 4216 if ((voltage <= limits->entries[i].voltage) && 4217 (sclk <= limits->entries[i].sclk) && 4218 (mclk <= limits->entries[i].mclk)) 4219 break; 4220 } 4221 4222 smc_voltage->phase_settings = (u8)i; 4223 4224 return 0; 4225 } 4226 4227 static int si_init_arb_table_index(struct radeon_device *rdev) 4228 { 4229 struct si_power_info *si_pi = si_get_pi(rdev); 4230 u32 tmp; 4231 int ret; 4232 4233 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4234 if (ret) 4235 return ret; 4236 4237 tmp &= 0x00FFFFFF; 4238 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4239 4240 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4241 } 4242 4243 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4244 { 4245 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4246 } 4247 4248 static int si_reset_to_default(struct radeon_device *rdev) 4249 { 4250 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4251 0 : -EINVAL; 4252 } 4253 4254 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4255 { 4256 struct si_power_info *si_pi = si_get_pi(rdev); 4257 u32 tmp; 4258 int ret; 4259 4260 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4261 &tmp, si_pi->sram_end); 4262 if (ret) 4263 return ret; 4264 4265 tmp = (tmp >> 24) & 0xff; 4266 4267 if (tmp == MC_CG_ARB_FREQ_F0) 4268 return 0; 4269 4270 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4271 } 4272 4273 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4274 u32 engine_clock) 4275 { 4276 u32 dram_rows; 4277 u32 dram_refresh_rate; 4278 u32 mc_arb_rfsh_rate; 4279 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4280 4281 if (tmp >= 4) 4282 dram_rows = 16384; 4283 else 4284 dram_rows = 1 << (tmp + 10); 4285 4286 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4287 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4288 4289 return mc_arb_rfsh_rate; 4290 } 4291 4292 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4293 struct rv7xx_pl *pl, 4294 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4295 { 4296 u32 dram_timing; 4297 u32 dram_timing2; 4298 u32 burst_time; 4299 4300 arb_regs->mc_arb_rfsh_rate = 4301 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4302 4303 radeon_atom_set_engine_dram_timings(rdev, 4304 pl->sclk, 4305 pl->mclk); 4306 4307 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4308 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4309 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4310 4311 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4312 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4313 arb_regs->mc_arb_burst_time = (u8)burst_time; 4314 4315 return 0; 4316 } 4317 4318 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4319 struct radeon_ps *radeon_state, 4320 unsigned int first_arb_set) 4321 { 4322 struct si_power_info *si_pi = si_get_pi(rdev); 4323 struct ni_ps *state = ni_get_ps(radeon_state); 4324 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4325 int i, ret = 0; 4326 4327 for (i = 0; i < state->performance_level_count; i++) { 4328 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4329 if (ret) 4330 break; 4331 ret = si_copy_bytes_to_smc(rdev, 4332 si_pi->arb_table_start + 4333 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4334 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4335 (u8 *)&arb_regs, 4336 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4337 si_pi->sram_end); 4338 if (ret) 4339 break; 4340 } 4341 4342 return ret; 4343 } 4344 4345 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4346 struct radeon_ps *radeon_new_state) 4347 { 4348 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4349 SISLANDS_DRIVER_STATE_ARB_INDEX); 4350 } 4351 4352 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4353 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4354 { 4355 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4356 struct si_power_info *si_pi = si_get_pi(rdev); 4357 4358 if (pi->mvdd_control) 4359 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4360 si_pi->mvdd_bootup_value, voltage); 4361 4362 return 0; 4363 } 4364 4365 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4366 struct radeon_ps *radeon_initial_state, 4367 SISLANDS_SMC_STATETABLE *table) 4368 { 4369 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4370 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4371 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4372 struct si_power_info *si_pi = si_get_pi(rdev); 4373 u32 reg; 4374 int ret; 4375 4376 table->initialState.levels[0].mclk.vDLL_CNTL = 4377 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4378 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4379 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4380 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4381 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4382 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4383 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4384 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4385 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4386 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4387 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4388 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4389 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4390 table->initialState.levels[0].mclk.vMPLL_SS = 4391 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4392 table->initialState.levels[0].mclk.vMPLL_SS2 = 4393 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4394 4395 table->initialState.levels[0].mclk.mclk_value = 4396 cpu_to_be32(initial_state->performance_levels[0].mclk); 4397 4398 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4399 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4400 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4401 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4402 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4403 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4404 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4405 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4406 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4407 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4408 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4409 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4410 4411 table->initialState.levels[0].sclk.sclk_value = 4412 cpu_to_be32(initial_state->performance_levels[0].sclk); 4413 4414 table->initialState.levels[0].arbRefreshState = 4415 SISLANDS_INITIAL_STATE_ARB_INDEX; 4416 4417 table->initialState.levels[0].ACIndex = 0; 4418 4419 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4420 initial_state->performance_levels[0].vddc, 4421 &table->initialState.levels[0].vddc); 4422 4423 if (!ret) { 4424 u16 std_vddc; 4425 4426 ret = si_get_std_voltage_value(rdev, 4427 &table->initialState.levels[0].vddc, 4428 &std_vddc); 4429 if (!ret) 4430 si_populate_std_voltage_value(rdev, std_vddc, 4431 table->initialState.levels[0].vddc.index, 4432 &table->initialState.levels[0].std_vddc); 4433 } 4434 4435 if (eg_pi->vddci_control) 4436 si_populate_voltage_value(rdev, 4437 &eg_pi->vddci_voltage_table, 4438 initial_state->performance_levels[0].vddci, 4439 &table->initialState.levels[0].vddci); 4440 4441 if (si_pi->vddc_phase_shed_control) 4442 si_populate_phase_shedding_value(rdev, 4443 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4444 initial_state->performance_levels[0].vddc, 4445 initial_state->performance_levels[0].sclk, 4446 initial_state->performance_levels[0].mclk, 4447 &table->initialState.levels[0].vddc); 4448 4449 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4450 4451 reg = CG_R(0xffff) | CG_L(0); 4452 table->initialState.levels[0].aT = cpu_to_be32(reg); 4453 4454 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4455 4456 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4457 4458 if (pi->mem_gddr5) { 4459 table->initialState.levels[0].strobeMode = 4460 si_get_strobe_mode_settings(rdev, 4461 initial_state->performance_levels[0].mclk); 4462 4463 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4464 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4465 else 4466 table->initialState.levels[0].mcFlags = 0; 4467 } 4468 4469 table->initialState.levelCount = 1; 4470 4471 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4472 4473 table->initialState.levels[0].dpm2.MaxPS = 0; 4474 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4475 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4476 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4477 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4478 4479 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4480 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4481 4482 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4483 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4484 4485 return 0; 4486 } 4487 4488 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4489 SISLANDS_SMC_STATETABLE *table) 4490 { 4491 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4492 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4493 struct si_power_info *si_pi = si_get_pi(rdev); 4494 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4495 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4496 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4497 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4498 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4499 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4500 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4501 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4502 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4503 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4504 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4505 u32 reg; 4506 int ret; 4507 4508 table->ACPIState = table->initialState; 4509 4510 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4511 4512 if (pi->acpi_vddc) { 4513 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4514 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4515 if (!ret) { 4516 u16 std_vddc; 4517 4518 ret = si_get_std_voltage_value(rdev, 4519 &table->ACPIState.levels[0].vddc, &std_vddc); 4520 if (!ret) 4521 si_populate_std_voltage_value(rdev, std_vddc, 4522 table->ACPIState.levels[0].vddc.index, 4523 &table->ACPIState.levels[0].std_vddc); 4524 } 4525 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4526 4527 if (si_pi->vddc_phase_shed_control) { 4528 si_populate_phase_shedding_value(rdev, 4529 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4530 pi->acpi_vddc, 4531 0, 4532 0, 4533 &table->ACPIState.levels[0].vddc); 4534 } 4535 } else { 4536 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4537 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4538 if (!ret) { 4539 u16 std_vddc; 4540 4541 ret = si_get_std_voltage_value(rdev, 4542 &table->ACPIState.levels[0].vddc, &std_vddc); 4543 4544 if (!ret) 4545 si_populate_std_voltage_value(rdev, std_vddc, 4546 table->ACPIState.levels[0].vddc.index, 4547 &table->ACPIState.levels[0].std_vddc); 4548 } 4549 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4550 si_pi->sys_pcie_mask, 4551 si_pi->boot_pcie_gen, 4552 RADEON_PCIE_GEN1); 4553 4554 if (si_pi->vddc_phase_shed_control) 4555 si_populate_phase_shedding_value(rdev, 4556 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4557 pi->min_vddc_in_table, 4558 0, 4559 0, 4560 &table->ACPIState.levels[0].vddc); 4561 } 4562 4563 if (pi->acpi_vddc) { 4564 if (eg_pi->acpi_vddci) 4565 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4566 eg_pi->acpi_vddci, 4567 &table->ACPIState.levels[0].vddci); 4568 } 4569 4570 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4571 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4572 4573 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4574 4575 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4576 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4577 4578 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4579 cpu_to_be32(dll_cntl); 4580 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4581 cpu_to_be32(mclk_pwrmgt_cntl); 4582 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4583 cpu_to_be32(mpll_ad_func_cntl); 4584 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4585 cpu_to_be32(mpll_dq_func_cntl); 4586 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4587 cpu_to_be32(mpll_func_cntl); 4588 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4589 cpu_to_be32(mpll_func_cntl_1); 4590 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4591 cpu_to_be32(mpll_func_cntl_2); 4592 table->ACPIState.levels[0].mclk.vMPLL_SS = 4593 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4594 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4595 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4596 4597 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4598 cpu_to_be32(spll_func_cntl); 4599 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4600 cpu_to_be32(spll_func_cntl_2); 4601 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4602 cpu_to_be32(spll_func_cntl_3); 4603 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4604 cpu_to_be32(spll_func_cntl_4); 4605 4606 table->ACPIState.levels[0].mclk.mclk_value = 0; 4607 table->ACPIState.levels[0].sclk.sclk_value = 0; 4608 4609 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4610 4611 if (eg_pi->dynamic_ac_timing) 4612 table->ACPIState.levels[0].ACIndex = 0; 4613 4614 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4615 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4616 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4617 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4618 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4619 4620 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4621 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4622 4623 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4624 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4625 4626 return 0; 4627 } 4628 4629 static int si_populate_ulv_state(struct radeon_device *rdev, 4630 SISLANDS_SMC_SWSTATE *state) 4631 { 4632 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4633 struct si_power_info *si_pi = si_get_pi(rdev); 4634 struct si_ulv_param *ulv = &si_pi->ulv; 4635 u32 sclk_in_sr = 1350; /* ??? */ 4636 int ret; 4637 4638 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4639 &state->levels[0]); 4640 if (!ret) { 4641 if (eg_pi->sclk_deep_sleep) { 4642 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4643 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4644 else 4645 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4646 } 4647 if (ulv->one_pcie_lane_in_ulv) 4648 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4649 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4650 state->levels[0].ACIndex = 1; 4651 state->levels[0].std_vddc = state->levels[0].vddc; 4652 state->levelCount = 1; 4653 4654 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4655 } 4656 4657 return ret; 4658 } 4659 4660 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4661 { 4662 struct si_power_info *si_pi = si_get_pi(rdev); 4663 struct si_ulv_param *ulv = &si_pi->ulv; 4664 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4665 int ret; 4666 4667 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4668 &arb_regs); 4669 if (ret) 4670 return ret; 4671 4672 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4673 ulv->volt_change_delay); 4674 4675 ret = si_copy_bytes_to_smc(rdev, 4676 si_pi->arb_table_start + 4677 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4678 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4679 (u8 *)&arb_regs, 4680 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4681 si_pi->sram_end); 4682 4683 return ret; 4684 } 4685 4686 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4687 { 4688 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4689 4690 pi->mvdd_split_frequency = 30000; 4691 } 4692 4693 static int si_init_smc_table(struct radeon_device *rdev) 4694 { 4695 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4696 struct si_power_info *si_pi = si_get_pi(rdev); 4697 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4698 const struct si_ulv_param *ulv = &si_pi->ulv; 4699 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4700 int ret; 4701 u32 lane_width; 4702 u32 vr_hot_gpio; 4703 4704 si_populate_smc_voltage_tables(rdev, table); 4705 4706 switch (rdev->pm.int_thermal_type) { 4707 case THERMAL_TYPE_SI: 4708 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4709 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4710 break; 4711 case THERMAL_TYPE_NONE: 4712 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4713 break; 4714 default: 4715 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4716 break; 4717 } 4718 4719 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4720 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4721 4722 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4723 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4724 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4725 } 4726 4727 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4728 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4729 4730 if (pi->mem_gddr5) 4731 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4732 4733 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4734 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4735 4736 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4737 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4738 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4739 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4740 vr_hot_gpio); 4741 } 4742 4743 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4744 if (ret) 4745 return ret; 4746 4747 ret = si_populate_smc_acpi_state(rdev, table); 4748 if (ret) 4749 return ret; 4750 4751 table->driverState = table->initialState; 4752 4753 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4754 SISLANDS_INITIAL_STATE_ARB_INDEX); 4755 if (ret) 4756 return ret; 4757 4758 if (ulv->supported && ulv->pl.vddc) { 4759 ret = si_populate_ulv_state(rdev, &table->ULVState); 4760 if (ret) 4761 return ret; 4762 4763 ret = si_program_ulv_memory_timing_parameters(rdev); 4764 if (ret) 4765 return ret; 4766 4767 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4768 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4769 4770 lane_width = radeon_get_pcie_lanes(rdev); 4771 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4772 } else { 4773 table->ULVState = table->initialState; 4774 } 4775 4776 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4777 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4778 si_pi->sram_end); 4779 } 4780 4781 static int si_calculate_sclk_params(struct radeon_device *rdev, 4782 u32 engine_clock, 4783 SISLANDS_SMC_SCLK_VALUE *sclk) 4784 { 4785 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4786 struct si_power_info *si_pi = si_get_pi(rdev); 4787 struct atom_clock_dividers dividers; 4788 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4789 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4790 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4791 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4792 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4793 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4794 u64 tmp; 4795 u32 reference_clock = rdev->clock.spll.reference_freq; 4796 u32 reference_divider; 4797 u32 fbdiv; 4798 int ret; 4799 4800 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4801 engine_clock, false, ÷rs); 4802 if (ret) 4803 return ret; 4804 4805 reference_divider = 1 + dividers.ref_div; 4806 4807 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4808 do_div(tmp, reference_clock); 4809 fbdiv = (u32) tmp; 4810 4811 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4812 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4813 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4814 4815 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4816 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4817 4818 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4819 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4820 spll_func_cntl_3 |= SPLL_DITHEN; 4821 4822 if (pi->sclk_ss) { 4823 struct radeon_atom_ss ss; 4824 u32 vco_freq = engine_clock * dividers.post_div; 4825 4826 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4827 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4828 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4829 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4830 4831 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4832 cg_spll_spread_spectrum |= CLK_S(clk_s); 4833 cg_spll_spread_spectrum |= SSEN; 4834 4835 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4836 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4837 } 4838 } 4839 4840 sclk->sclk_value = engine_clock; 4841 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4842 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4843 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4844 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4845 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4846 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4847 4848 return 0; 4849 } 4850 4851 static int si_populate_sclk_value(struct radeon_device *rdev, 4852 u32 engine_clock, 4853 SISLANDS_SMC_SCLK_VALUE *sclk) 4854 { 4855 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4856 int ret; 4857 4858 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4859 if (!ret) { 4860 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4861 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4862 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4863 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4864 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4865 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4866 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4867 } 4868 4869 return ret; 4870 } 4871 4872 static int si_populate_mclk_value(struct radeon_device *rdev, 4873 u32 engine_clock, 4874 u32 memory_clock, 4875 SISLANDS_SMC_MCLK_VALUE *mclk, 4876 bool strobe_mode, 4877 bool dll_state_on) 4878 { 4879 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4880 struct si_power_info *si_pi = si_get_pi(rdev); 4881 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4882 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4883 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4884 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4885 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4886 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4887 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4888 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4889 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4890 struct atom_mpll_param mpll_param; 4891 int ret; 4892 4893 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4894 if (ret) 4895 return ret; 4896 4897 mpll_func_cntl &= ~BWCTRL_MASK; 4898 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4899 4900 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4901 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4902 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4903 4904 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4905 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4906 4907 if (pi->mem_gddr5) { 4908 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4909 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4910 YCLK_POST_DIV(mpll_param.post_div); 4911 } 4912 4913 if (pi->mclk_ss) { 4914 struct radeon_atom_ss ss; 4915 u32 freq_nom; 4916 u32 tmp; 4917 u32 reference_clock = rdev->clock.mpll.reference_freq; 4918 4919 if (pi->mem_gddr5) 4920 freq_nom = memory_clock * 4; 4921 else 4922 freq_nom = memory_clock * 2; 4923 4924 tmp = freq_nom / reference_clock; 4925 tmp = tmp * tmp; 4926 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4927 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4928 u32 clks = reference_clock * 5 / ss.rate; 4929 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4930 4931 mpll_ss1 &= ~CLKV_MASK; 4932 mpll_ss1 |= CLKV(clkv); 4933 4934 mpll_ss2 &= ~CLKS_MASK; 4935 mpll_ss2 |= CLKS(clks); 4936 } 4937 } 4938 4939 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4940 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4941 4942 if (dll_state_on) 4943 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4944 else 4945 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4946 4947 mclk->mclk_value = cpu_to_be32(memory_clock); 4948 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4949 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4950 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4951 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4952 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4953 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4954 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4955 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4956 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4957 4958 return 0; 4959 } 4960 4961 static void si_populate_smc_sp(struct radeon_device *rdev, 4962 struct radeon_ps *radeon_state, 4963 SISLANDS_SMC_SWSTATE *smc_state) 4964 { 4965 struct ni_ps *ps = ni_get_ps(radeon_state); 4966 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4967 int i; 4968 4969 for (i = 0; i < ps->performance_level_count - 1; i++) 4970 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4971 4972 smc_state->levels[ps->performance_level_count - 1].bSP = 4973 cpu_to_be32(pi->psp); 4974 } 4975 4976 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4977 struct rv7xx_pl *pl, 4978 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4979 { 4980 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4981 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4982 struct si_power_info *si_pi = si_get_pi(rdev); 4983 int ret; 4984 bool dll_state_on; 4985 u16 std_vddc; 4986 bool gmc_pg = false; 4987 4988 if (eg_pi->pcie_performance_request && 4989 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4990 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4991 else 4992 level->gen2PCIE = (u8)pl->pcie_gen; 4993 4994 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4995 if (ret) 4996 return ret; 4997 4998 level->mcFlags = 0; 4999 5000 if (pi->mclk_stutter_mode_threshold && 5001 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5002 !eg_pi->uvd_enabled && 5003 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5004 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5005 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5006 5007 if (gmc_pg) 5008 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5009 } 5010 5011 if (pi->mem_gddr5) { 5012 if (pl->mclk > pi->mclk_edc_enable_threshold) 5013 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5014 5015 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5016 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5017 5018 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5019 5020 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5021 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5022 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5023 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5024 else 5025 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5026 } else { 5027 dll_state_on = false; 5028 } 5029 } else { 5030 level->strobeMode = si_get_strobe_mode_settings(rdev, 5031 pl->mclk); 5032 5033 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5034 } 5035 5036 ret = si_populate_mclk_value(rdev, 5037 pl->sclk, 5038 pl->mclk, 5039 &level->mclk, 5040 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5041 if (ret) 5042 return ret; 5043 5044 ret = si_populate_voltage_value(rdev, 5045 &eg_pi->vddc_voltage_table, 5046 pl->vddc, &level->vddc); 5047 if (ret) 5048 return ret; 5049 5050 5051 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5052 if (ret) 5053 return ret; 5054 5055 ret = si_populate_std_voltage_value(rdev, std_vddc, 5056 level->vddc.index, &level->std_vddc); 5057 if (ret) 5058 return ret; 5059 5060 if (eg_pi->vddci_control) { 5061 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5062 pl->vddci, &level->vddci); 5063 if (ret) 5064 return ret; 5065 } 5066 5067 if (si_pi->vddc_phase_shed_control) { 5068 ret = si_populate_phase_shedding_value(rdev, 5069 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5070 pl->vddc, 5071 pl->sclk, 5072 pl->mclk, 5073 &level->vddc); 5074 if (ret) 5075 return ret; 5076 } 5077 5078 level->MaxPoweredUpCU = si_pi->max_cu; 5079 5080 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5081 5082 return ret; 5083 } 5084 5085 static int si_populate_smc_t(struct radeon_device *rdev, 5086 struct radeon_ps *radeon_state, 5087 SISLANDS_SMC_SWSTATE *smc_state) 5088 { 5089 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5090 struct ni_ps *state = ni_get_ps(radeon_state); 5091 u32 a_t; 5092 u32 t_l, t_h; 5093 u32 high_bsp; 5094 int i, ret; 5095 5096 if (state->performance_level_count >= 9) 5097 return -EINVAL; 5098 5099 if (state->performance_level_count < 2) { 5100 a_t = CG_R(0xffff) | CG_L(0); 5101 smc_state->levels[0].aT = cpu_to_be32(a_t); 5102 return 0; 5103 } 5104 5105 smc_state->levels[0].aT = cpu_to_be32(0); 5106 5107 for (i = 0; i <= state->performance_level_count - 2; i++) { 5108 ret = r600_calculate_at( 5109 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5110 100 * R600_AH_DFLT, 5111 state->performance_levels[i + 1].sclk, 5112 state->performance_levels[i].sclk, 5113 &t_l, 5114 &t_h); 5115 5116 if (ret) { 5117 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5118 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5119 } 5120 5121 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5122 a_t |= CG_R(t_l * pi->bsp / 20000); 5123 smc_state->levels[i].aT = cpu_to_be32(a_t); 5124 5125 high_bsp = (i == state->performance_level_count - 2) ? 5126 pi->pbsp : pi->bsp; 5127 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5128 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5129 } 5130 5131 return 0; 5132 } 5133 5134 static int si_disable_ulv(struct radeon_device *rdev) 5135 { 5136 struct si_power_info *si_pi = si_get_pi(rdev); 5137 struct si_ulv_param *ulv = &si_pi->ulv; 5138 5139 if (ulv->supported) 5140 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5141 0 : -EINVAL; 5142 5143 return 0; 5144 } 5145 5146 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5147 struct radeon_ps *radeon_state) 5148 { 5149 const struct si_power_info *si_pi = si_get_pi(rdev); 5150 const struct si_ulv_param *ulv = &si_pi->ulv; 5151 const struct ni_ps *state = ni_get_ps(radeon_state); 5152 int i; 5153 5154 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5155 return false; 5156 5157 /* XXX validate against display requirements! */ 5158 5159 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5160 if (rdev->clock.current_dispclk <= 5161 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5162 if (ulv->pl.vddc < 5163 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5164 return false; 5165 } 5166 } 5167 5168 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5169 return false; 5170 5171 return true; 5172 } 5173 5174 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5175 struct radeon_ps *radeon_new_state) 5176 { 5177 const struct si_power_info *si_pi = si_get_pi(rdev); 5178 const struct si_ulv_param *ulv = &si_pi->ulv; 5179 5180 if (ulv->supported) { 5181 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5182 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5183 0 : -EINVAL; 5184 } 5185 return 0; 5186 } 5187 5188 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5189 struct radeon_ps *radeon_state, 5190 SISLANDS_SMC_SWSTATE *smc_state) 5191 { 5192 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5193 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5194 struct si_power_info *si_pi = si_get_pi(rdev); 5195 struct ni_ps *state = ni_get_ps(radeon_state); 5196 int i, ret; 5197 u32 threshold; 5198 u32 sclk_in_sr = 1350; /* ??? */ 5199 5200 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5201 return -EINVAL; 5202 5203 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5204 5205 if (radeon_state->vclk && radeon_state->dclk) { 5206 eg_pi->uvd_enabled = true; 5207 if (eg_pi->smu_uvd_hs) 5208 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5209 } else { 5210 eg_pi->uvd_enabled = false; 5211 } 5212 5213 if (state->dc_compatible) 5214 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5215 5216 smc_state->levelCount = 0; 5217 for (i = 0; i < state->performance_level_count; i++) { 5218 if (eg_pi->sclk_deep_sleep) { 5219 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5220 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5221 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5222 else 5223 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5224 } 5225 } 5226 5227 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5228 &smc_state->levels[i]); 5229 smc_state->levels[i].arbRefreshState = 5230 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5231 5232 if (ret) 5233 return ret; 5234 5235 if (ni_pi->enable_power_containment) 5236 smc_state->levels[i].displayWatermark = 5237 (state->performance_levels[i].sclk < threshold) ? 5238 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5239 else 5240 smc_state->levels[i].displayWatermark = (i < 2) ? 5241 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5242 5243 if (eg_pi->dynamic_ac_timing) 5244 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5245 else 5246 smc_state->levels[i].ACIndex = 0; 5247 5248 smc_state->levelCount++; 5249 } 5250 5251 si_write_smc_soft_register(rdev, 5252 SI_SMC_SOFT_REGISTER_watermark_threshold, 5253 threshold / 512); 5254 5255 si_populate_smc_sp(rdev, radeon_state, smc_state); 5256 5257 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5258 if (ret) 5259 ni_pi->enable_power_containment = false; 5260 5261 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5262 if (ret) 5263 ni_pi->enable_sq_ramping = false; 5264 5265 return si_populate_smc_t(rdev, radeon_state, smc_state); 5266 } 5267 5268 static int si_upload_sw_state(struct radeon_device *rdev, 5269 struct radeon_ps *radeon_new_state) 5270 { 5271 struct si_power_info *si_pi = si_get_pi(rdev); 5272 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5273 int ret; 5274 u32 address = si_pi->state_table_start + 5275 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5276 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5277 ((new_state->performance_level_count - 1) * 5278 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5279 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5280 5281 memset(smc_state, 0, state_size); 5282 5283 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5284 if (ret) 5285 return ret; 5286 5287 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5288 state_size, si_pi->sram_end); 5289 5290 return ret; 5291 } 5292 5293 static int si_upload_ulv_state(struct radeon_device *rdev) 5294 { 5295 struct si_power_info *si_pi = si_get_pi(rdev); 5296 struct si_ulv_param *ulv = &si_pi->ulv; 5297 int ret = 0; 5298 5299 if (ulv->supported && ulv->pl.vddc) { 5300 u32 address = si_pi->state_table_start + 5301 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5302 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5303 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5304 5305 memset(smc_state, 0, state_size); 5306 5307 ret = si_populate_ulv_state(rdev, smc_state); 5308 if (!ret) 5309 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5310 state_size, si_pi->sram_end); 5311 } 5312 5313 return ret; 5314 } 5315 5316 static int si_upload_smc_data(struct radeon_device *rdev) 5317 { 5318 struct radeon_crtc *radeon_crtc = NULL; 5319 int i; 5320 5321 if (rdev->pm.dpm.new_active_crtc_count == 0) 5322 return 0; 5323 5324 for (i = 0; i < rdev->num_crtc; i++) { 5325 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5326 radeon_crtc = rdev->mode_info.crtcs[i]; 5327 break; 5328 } 5329 } 5330 5331 if (radeon_crtc == NULL) 5332 return 0; 5333 5334 if (radeon_crtc->line_time <= 0) 5335 return 0; 5336 5337 if (si_write_smc_soft_register(rdev, 5338 SI_SMC_SOFT_REGISTER_crtc_index, 5339 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5340 return 0; 5341 5342 if (si_write_smc_soft_register(rdev, 5343 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5344 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5345 return 0; 5346 5347 if (si_write_smc_soft_register(rdev, 5348 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5349 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5350 return 0; 5351 5352 return 0; 5353 } 5354 5355 static int si_set_mc_special_registers(struct radeon_device *rdev, 5356 struct si_mc_reg_table *table) 5357 { 5358 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5359 u8 i, j, k; 5360 u32 temp_reg; 5361 5362 for (i = 0, j = table->last; i < table->last; i++) { 5363 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5364 return -EINVAL; 5365 switch (table->mc_reg_address[i].s1 << 2) { 5366 case MC_SEQ_MISC1: 5367 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5368 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5369 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5370 for (k = 0; k < table->num_entries; k++) 5371 table->mc_reg_table_entry[k].mc_data[j] = 5372 ((temp_reg & 0xffff0000)) | 5373 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5374 j++; 5375 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5376 return -EINVAL; 5377 5378 temp_reg = RREG32(MC_PMG_CMD_MRS); 5379 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5380 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5381 for (k = 0; k < table->num_entries; k++) { 5382 table->mc_reg_table_entry[k].mc_data[j] = 5383 (temp_reg & 0xffff0000) | 5384 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5385 if (!pi->mem_gddr5) 5386 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5387 } 5388 j++; 5389 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5390 return -EINVAL; 5391 5392 if (!pi->mem_gddr5) { 5393 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5394 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5395 for (k = 0; k < table->num_entries; k++) 5396 table->mc_reg_table_entry[k].mc_data[j] = 5397 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5398 j++; 5399 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5400 return -EINVAL; 5401 } 5402 break; 5403 case MC_SEQ_RESERVE_M: 5404 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5405 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5406 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5407 for(k = 0; k < table->num_entries; k++) 5408 table->mc_reg_table_entry[k].mc_data[j] = 5409 (temp_reg & 0xffff0000) | 5410 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5411 j++; 5412 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5413 return -EINVAL; 5414 break; 5415 default: 5416 break; 5417 } 5418 } 5419 5420 table->last = j; 5421 5422 return 0; 5423 } 5424 5425 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5426 { 5427 bool result = true; 5428 5429 switch (in_reg) { 5430 case MC_SEQ_RAS_TIMING >> 2: 5431 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5432 break; 5433 case MC_SEQ_CAS_TIMING >> 2: 5434 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5435 break; 5436 case MC_SEQ_MISC_TIMING >> 2: 5437 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5438 break; 5439 case MC_SEQ_MISC_TIMING2 >> 2: 5440 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5441 break; 5442 case MC_SEQ_RD_CTL_D0 >> 2: 5443 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5444 break; 5445 case MC_SEQ_RD_CTL_D1 >> 2: 5446 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5447 break; 5448 case MC_SEQ_WR_CTL_D0 >> 2: 5449 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5450 break; 5451 case MC_SEQ_WR_CTL_D1 >> 2: 5452 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5453 break; 5454 case MC_PMG_CMD_EMRS >> 2: 5455 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5456 break; 5457 case MC_PMG_CMD_MRS >> 2: 5458 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5459 break; 5460 case MC_PMG_CMD_MRS1 >> 2: 5461 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5462 break; 5463 case MC_SEQ_PMG_TIMING >> 2: 5464 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5465 break; 5466 case MC_PMG_CMD_MRS2 >> 2: 5467 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5468 break; 5469 case MC_SEQ_WR_CTL_2 >> 2: 5470 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5471 break; 5472 default: 5473 result = false; 5474 break; 5475 } 5476 5477 return result; 5478 } 5479 5480 static void si_set_valid_flag(struct si_mc_reg_table *table) 5481 { 5482 u8 i, j; 5483 5484 for (i = 0; i < table->last; i++) { 5485 for (j = 1; j < table->num_entries; j++) { 5486 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5487 table->valid_flag |= 1 << i; 5488 break; 5489 } 5490 } 5491 } 5492 } 5493 5494 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5495 { 5496 u32 i; 5497 u16 address; 5498 5499 for (i = 0; i < table->last; i++) 5500 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5501 address : table->mc_reg_address[i].s1; 5502 5503 } 5504 5505 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5506 struct si_mc_reg_table *si_table) 5507 { 5508 u8 i, j; 5509 5510 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5511 return -EINVAL; 5512 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5513 return -EINVAL; 5514 5515 for (i = 0; i < table->last; i++) 5516 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5517 si_table->last = table->last; 5518 5519 for (i = 0; i < table->num_entries; i++) { 5520 si_table->mc_reg_table_entry[i].mclk_max = 5521 table->mc_reg_table_entry[i].mclk_max; 5522 for (j = 0; j < table->last; j++) { 5523 si_table->mc_reg_table_entry[i].mc_data[j] = 5524 table->mc_reg_table_entry[i].mc_data[j]; 5525 } 5526 } 5527 si_table->num_entries = table->num_entries; 5528 5529 return 0; 5530 } 5531 5532 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5533 { 5534 struct si_power_info *si_pi = si_get_pi(rdev); 5535 struct atom_mc_reg_table *table; 5536 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5537 u8 module_index = rv770_get_memory_module_index(rdev); 5538 int ret; 5539 5540 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5541 if (!table) 5542 return -ENOMEM; 5543 5544 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5545 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5546 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5547 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5548 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5549 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5550 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5551 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5552 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5553 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5554 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5555 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5556 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5557 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5558 5559 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5560 if (ret) 5561 goto init_mc_done; 5562 5563 ret = si_copy_vbios_mc_reg_table(table, si_table); 5564 if (ret) 5565 goto init_mc_done; 5566 5567 si_set_s0_mc_reg_index(si_table); 5568 5569 ret = si_set_mc_special_registers(rdev, si_table); 5570 if (ret) 5571 goto init_mc_done; 5572 5573 si_set_valid_flag(si_table); 5574 5575 init_mc_done: 5576 kfree(table); 5577 5578 return ret; 5579 5580 } 5581 5582 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5583 SMC_SIslands_MCRegisters *mc_reg_table) 5584 { 5585 struct si_power_info *si_pi = si_get_pi(rdev); 5586 u32 i, j; 5587 5588 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5589 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5590 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5591 break; 5592 mc_reg_table->address[i].s0 = 5593 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5594 mc_reg_table->address[i].s1 = 5595 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5596 i++; 5597 } 5598 } 5599 mc_reg_table->last = (u8)i; 5600 } 5601 5602 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5603 SMC_SIslands_MCRegisterSet *data, 5604 u32 num_entries, u32 valid_flag) 5605 { 5606 u32 i, j; 5607 5608 for(i = 0, j = 0; j < num_entries; j++) { 5609 if (valid_flag & (1 << j)) { 5610 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5611 i++; 5612 } 5613 } 5614 } 5615 5616 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5617 struct rv7xx_pl *pl, 5618 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5619 { 5620 struct si_power_info *si_pi = si_get_pi(rdev); 5621 u32 i = 0; 5622 5623 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5624 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5625 break; 5626 } 5627 5628 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5629 --i; 5630 5631 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5632 mc_reg_table_data, si_pi->mc_reg_table.last, 5633 si_pi->mc_reg_table.valid_flag); 5634 } 5635 5636 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5637 struct radeon_ps *radeon_state, 5638 SMC_SIslands_MCRegisters *mc_reg_table) 5639 { 5640 struct ni_ps *state = ni_get_ps(radeon_state); 5641 int i; 5642 5643 for (i = 0; i < state->performance_level_count; i++) { 5644 si_convert_mc_reg_table_entry_to_smc(rdev, 5645 &state->performance_levels[i], 5646 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5647 } 5648 } 5649 5650 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5651 struct radeon_ps *radeon_boot_state) 5652 { 5653 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5654 struct si_power_info *si_pi = si_get_pi(rdev); 5655 struct si_ulv_param *ulv = &si_pi->ulv; 5656 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5657 5658 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5659 5660 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5661 5662 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5663 5664 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5665 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5666 5667 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5668 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5669 si_pi->mc_reg_table.last, 5670 si_pi->mc_reg_table.valid_flag); 5671 5672 if (ulv->supported && ulv->pl.vddc != 0) 5673 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5674 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5675 else 5676 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5677 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5678 si_pi->mc_reg_table.last, 5679 si_pi->mc_reg_table.valid_flag); 5680 5681 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5682 5683 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5684 (u8 *)smc_mc_reg_table, 5685 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5686 } 5687 5688 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5689 struct radeon_ps *radeon_new_state) 5690 { 5691 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5692 struct si_power_info *si_pi = si_get_pi(rdev); 5693 u32 address = si_pi->mc_reg_table_start + 5694 offsetof(SMC_SIslands_MCRegisters, 5695 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5696 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5697 5698 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5699 5700 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5701 5702 5703 return si_copy_bytes_to_smc(rdev, address, 5704 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5705 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5706 si_pi->sram_end); 5707 5708 } 5709 5710 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5711 { 5712 if (enable) 5713 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5714 else 5715 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5716 } 5717 5718 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5719 struct radeon_ps *radeon_state) 5720 { 5721 struct ni_ps *state = ni_get_ps(radeon_state); 5722 int i; 5723 u16 pcie_speed, max_speed = 0; 5724 5725 for (i = 0; i < state->performance_level_count; i++) { 5726 pcie_speed = state->performance_levels[i].pcie_gen; 5727 if (max_speed < pcie_speed) 5728 max_speed = pcie_speed; 5729 } 5730 return max_speed; 5731 } 5732 5733 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5734 { 5735 u32 speed_cntl; 5736 5737 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5738 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5739 5740 return (u16)speed_cntl; 5741 } 5742 5743 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5744 struct radeon_ps *radeon_new_state, 5745 struct radeon_ps *radeon_current_state) 5746 { 5747 struct si_power_info *si_pi = si_get_pi(rdev); 5748 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5749 enum radeon_pcie_gen current_link_speed; 5750 5751 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5752 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5753 else 5754 current_link_speed = si_pi->force_pcie_gen; 5755 5756 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5757 si_pi->pspp_notify_required = false; 5758 if (target_link_speed > current_link_speed) { 5759 switch (target_link_speed) { 5760 #if defined(CONFIG_ACPI) 5761 case RADEON_PCIE_GEN3: 5762 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5763 break; 5764 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5765 if (current_link_speed == RADEON_PCIE_GEN2) 5766 break; 5767 /* fall through */ 5768 case RADEON_PCIE_GEN2: 5769 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5770 break; 5771 #endif 5772 /* fall through */ 5773 default: 5774 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5775 break; 5776 } 5777 } else { 5778 if (target_link_speed < current_link_speed) 5779 si_pi->pspp_notify_required = true; 5780 } 5781 } 5782 5783 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5784 struct radeon_ps *radeon_new_state, 5785 struct radeon_ps *radeon_current_state) 5786 { 5787 struct si_power_info *si_pi = si_get_pi(rdev); 5788 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5789 u8 request; 5790 5791 if (si_pi->pspp_notify_required) { 5792 if (target_link_speed == RADEON_PCIE_GEN3) 5793 request = PCIE_PERF_REQ_PECI_GEN3; 5794 else if (target_link_speed == RADEON_PCIE_GEN2) 5795 request = PCIE_PERF_REQ_PECI_GEN2; 5796 else 5797 request = PCIE_PERF_REQ_PECI_GEN1; 5798 5799 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5800 (si_get_current_pcie_speed(rdev) > 0)) 5801 return; 5802 5803 #if defined(CONFIG_ACPI) 5804 radeon_acpi_pcie_performance_request(rdev, request, false); 5805 #endif 5806 } 5807 } 5808 5809 #if 0 5810 static int si_ds_request(struct radeon_device *rdev, 5811 bool ds_status_on, u32 count_write) 5812 { 5813 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5814 5815 if (eg_pi->sclk_deep_sleep) { 5816 if (ds_status_on) 5817 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5818 PPSMC_Result_OK) ? 5819 0 : -EINVAL; 5820 else 5821 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5822 PPSMC_Result_OK) ? 0 : -EINVAL; 5823 } 5824 return 0; 5825 } 5826 #endif 5827 5828 static void si_set_max_cu_value(struct radeon_device *rdev) 5829 { 5830 struct si_power_info *si_pi = si_get_pi(rdev); 5831 5832 if (rdev->family == CHIP_VERDE) { 5833 switch (rdev->pdev->device) { 5834 case 0x6820: 5835 case 0x6825: 5836 case 0x6821: 5837 case 0x6823: 5838 case 0x6827: 5839 si_pi->max_cu = 10; 5840 break; 5841 case 0x682D: 5842 case 0x6824: 5843 case 0x682F: 5844 case 0x6826: 5845 si_pi->max_cu = 8; 5846 break; 5847 case 0x6828: 5848 case 0x6830: 5849 case 0x6831: 5850 case 0x6838: 5851 case 0x6839: 5852 case 0x683D: 5853 si_pi->max_cu = 10; 5854 break; 5855 case 0x683B: 5856 case 0x683F: 5857 case 0x6829: 5858 si_pi->max_cu = 8; 5859 break; 5860 default: 5861 si_pi->max_cu = 0; 5862 break; 5863 } 5864 } else { 5865 si_pi->max_cu = 0; 5866 } 5867 } 5868 5869 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5870 struct radeon_clock_voltage_dependency_table *table) 5871 { 5872 u32 i; 5873 int j; 5874 u16 leakage_voltage; 5875 5876 if (table) { 5877 for (i = 0; i < table->count; i++) { 5878 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5879 table->entries[i].v, 5880 &leakage_voltage)) { 5881 case 0: 5882 table->entries[i].v = leakage_voltage; 5883 break; 5884 case -EAGAIN: 5885 return -EINVAL; 5886 case -EINVAL: 5887 default: 5888 break; 5889 } 5890 } 5891 5892 for (j = (table->count - 2); j >= 0; j--) { 5893 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5894 table->entries[j].v : table->entries[j + 1].v; 5895 } 5896 } 5897 return 0; 5898 } 5899 5900 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5901 { 5902 int ret = 0; 5903 5904 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5906 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5907 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5908 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5909 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5910 return ret; 5911 } 5912 5913 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5914 struct radeon_ps *radeon_new_state, 5915 struct radeon_ps *radeon_current_state) 5916 { 5917 u32 lane_width; 5918 u32 new_lane_width = 5919 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5920 u32 current_lane_width = 5921 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5922 5923 if (new_lane_width != current_lane_width) { 5924 radeon_set_pcie_lanes(rdev, new_lane_width); 5925 lane_width = radeon_get_pcie_lanes(rdev); 5926 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5927 } 5928 } 5929 5930 static void si_set_vce_clock(struct radeon_device *rdev, 5931 struct radeon_ps *new_rps, 5932 struct radeon_ps *old_rps) 5933 { 5934 if ((old_rps->evclk != new_rps->evclk) || 5935 (old_rps->ecclk != new_rps->ecclk)) { 5936 /* turn the clocks on when encoding, off otherwise */ 5937 if (new_rps->evclk || new_rps->ecclk) 5938 vce_v1_0_enable_mgcg(rdev, false); 5939 else 5940 vce_v1_0_enable_mgcg(rdev, true); 5941 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5942 } 5943 } 5944 5945 void si_dpm_setup_asic(struct radeon_device *rdev) 5946 { 5947 int r; 5948 5949 r = si_mc_load_microcode(rdev); 5950 if (r) 5951 DRM_ERROR("Failed to load MC firmware!\n"); 5952 rv770_get_memory_type(rdev); 5953 si_read_clock_registers(rdev); 5954 si_enable_acpi_power_management(rdev); 5955 } 5956 5957 static int si_thermal_enable_alert(struct radeon_device *rdev, 5958 bool enable) 5959 { 5960 u32 thermal_int = RREG32(CG_THERMAL_INT); 5961 5962 if (enable) { 5963 PPSMC_Result result; 5964 5965 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5966 WREG32(CG_THERMAL_INT, thermal_int); 5967 rdev->irq.dpm_thermal = false; 5968 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5969 if (result != PPSMC_Result_OK) { 5970 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5971 return -EINVAL; 5972 } 5973 } else { 5974 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5975 WREG32(CG_THERMAL_INT, thermal_int); 5976 rdev->irq.dpm_thermal = true; 5977 } 5978 5979 return 0; 5980 } 5981 5982 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5983 int min_temp, int max_temp) 5984 { 5985 int low_temp = 0 * 1000; 5986 int high_temp = 255 * 1000; 5987 5988 if (low_temp < min_temp) 5989 low_temp = min_temp; 5990 if (high_temp > max_temp) 5991 high_temp = max_temp; 5992 if (high_temp < low_temp) { 5993 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5994 return -EINVAL; 5995 } 5996 5997 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5998 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5999 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6000 6001 rdev->pm.dpm.thermal.min_temp = low_temp; 6002 rdev->pm.dpm.thermal.max_temp = high_temp; 6003 6004 return 0; 6005 } 6006 6007 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6008 { 6009 struct si_power_info *si_pi = si_get_pi(rdev); 6010 u32 tmp; 6011 6012 if (si_pi->fan_ctrl_is_in_default_mode) { 6013 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6014 si_pi->fan_ctrl_default_mode = tmp; 6015 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6016 si_pi->t_min = tmp; 6017 si_pi->fan_ctrl_is_in_default_mode = false; 6018 } 6019 6020 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6021 tmp |= TMIN(0); 6022 WREG32(CG_FDO_CTRL2, tmp); 6023 6024 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6025 tmp |= FDO_PWM_MODE(mode); 6026 WREG32(CG_FDO_CTRL2, tmp); 6027 } 6028 6029 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6030 { 6031 struct si_power_info *si_pi = si_get_pi(rdev); 6032 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6033 u32 duty100; 6034 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6035 u16 fdo_min, slope1, slope2; 6036 u32 reference_clock, tmp; 6037 int ret; 6038 u64 tmp64; 6039 6040 if (!si_pi->fan_table_start) { 6041 rdev->pm.dpm.fan.ucode_fan_control = false; 6042 return 0; 6043 } 6044 6045 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6046 6047 if (duty100 == 0) { 6048 rdev->pm.dpm.fan.ucode_fan_control = false; 6049 return 0; 6050 } 6051 6052 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6053 do_div(tmp64, 10000); 6054 fdo_min = (u16)tmp64; 6055 6056 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6057 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6058 6059 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6060 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6061 6062 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6063 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6064 6065 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6066 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6067 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6068 6069 fan_table.slope1 = cpu_to_be16(slope1); 6070 fan_table.slope2 = cpu_to_be16(slope2); 6071 6072 fan_table.fdo_min = cpu_to_be16(fdo_min); 6073 6074 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6075 6076 fan_table.hys_up = cpu_to_be16(1); 6077 6078 fan_table.hys_slope = cpu_to_be16(1); 6079 6080 fan_table.temp_resp_lim = cpu_to_be16(5); 6081 6082 reference_clock = radeon_get_xclk(rdev); 6083 6084 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6085 reference_clock) / 1600); 6086 6087 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6088 6089 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6090 fan_table.temp_src = (uint8_t)tmp; 6091 6092 ret = si_copy_bytes_to_smc(rdev, 6093 si_pi->fan_table_start, 6094 (u8 *)(&fan_table), 6095 sizeof(fan_table), 6096 si_pi->sram_end); 6097 6098 if (ret) { 6099 DRM_ERROR("Failed to load fan table to the SMC."); 6100 rdev->pm.dpm.fan.ucode_fan_control = false; 6101 } 6102 6103 return 0; 6104 } 6105 6106 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6107 { 6108 struct si_power_info *si_pi = si_get_pi(rdev); 6109 PPSMC_Result ret; 6110 6111 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6112 if (ret == PPSMC_Result_OK) { 6113 si_pi->fan_is_controlled_by_smc = true; 6114 return 0; 6115 } else { 6116 return -EINVAL; 6117 } 6118 } 6119 6120 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6121 { 6122 struct si_power_info *si_pi = si_get_pi(rdev); 6123 PPSMC_Result ret; 6124 6125 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6126 6127 if (ret == PPSMC_Result_OK) { 6128 si_pi->fan_is_controlled_by_smc = false; 6129 return 0; 6130 } else { 6131 return -EINVAL; 6132 } 6133 } 6134 6135 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6136 u32 *speed) 6137 { 6138 u32 duty, duty100; 6139 u64 tmp64; 6140 6141 if (rdev->pm.no_fan) 6142 return -ENOENT; 6143 6144 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6145 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6146 6147 if (duty100 == 0) 6148 return -EINVAL; 6149 6150 tmp64 = (u64)duty * 100; 6151 do_div(tmp64, duty100); 6152 *speed = (u32)tmp64; 6153 6154 if (*speed > 100) 6155 *speed = 100; 6156 6157 return 0; 6158 } 6159 6160 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6161 u32 speed) 6162 { 6163 struct si_power_info *si_pi = si_get_pi(rdev); 6164 u32 tmp; 6165 u32 duty, duty100; 6166 u64 tmp64; 6167 6168 if (rdev->pm.no_fan) 6169 return -ENOENT; 6170 6171 if (si_pi->fan_is_controlled_by_smc) 6172 return -EINVAL; 6173 6174 if (speed > 100) 6175 return -EINVAL; 6176 6177 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6178 6179 if (duty100 == 0) 6180 return -EINVAL; 6181 6182 tmp64 = (u64)speed * duty100; 6183 do_div(tmp64, 100); 6184 duty = (u32)tmp64; 6185 6186 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6187 tmp |= FDO_STATIC_DUTY(duty); 6188 WREG32(CG_FDO_CTRL0, tmp); 6189 6190 return 0; 6191 } 6192 6193 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6194 { 6195 if (mode) { 6196 /* stop auto-manage */ 6197 if (rdev->pm.dpm.fan.ucode_fan_control) 6198 si_fan_ctrl_stop_smc_fan_control(rdev); 6199 si_fan_ctrl_set_static_mode(rdev, mode); 6200 } else { 6201 /* restart auto-manage */ 6202 if (rdev->pm.dpm.fan.ucode_fan_control) 6203 si_thermal_start_smc_fan_control(rdev); 6204 else 6205 si_fan_ctrl_set_default_mode(rdev); 6206 } 6207 } 6208 6209 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6210 { 6211 struct si_power_info *si_pi = si_get_pi(rdev); 6212 u32 tmp; 6213 6214 if (si_pi->fan_is_controlled_by_smc) 6215 return 0; 6216 6217 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6218 return (tmp >> FDO_PWM_MODE_SHIFT); 6219 } 6220 6221 #if 0 6222 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6223 u32 *speed) 6224 { 6225 u32 tach_period; 6226 u32 xclk = radeon_get_xclk(rdev); 6227 6228 if (rdev->pm.no_fan) 6229 return -ENOENT; 6230 6231 if (rdev->pm.fan_pulses_per_revolution == 0) 6232 return -ENOENT; 6233 6234 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6235 if (tach_period == 0) 6236 return -ENOENT; 6237 6238 *speed = 60 * xclk * 10000 / tach_period; 6239 6240 return 0; 6241 } 6242 6243 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6244 u32 speed) 6245 { 6246 u32 tach_period, tmp; 6247 u32 xclk = radeon_get_xclk(rdev); 6248 6249 if (rdev->pm.no_fan) 6250 return -ENOENT; 6251 6252 if (rdev->pm.fan_pulses_per_revolution == 0) 6253 return -ENOENT; 6254 6255 if ((speed < rdev->pm.fan_min_rpm) || 6256 (speed > rdev->pm.fan_max_rpm)) 6257 return -EINVAL; 6258 6259 if (rdev->pm.dpm.fan.ucode_fan_control) 6260 si_fan_ctrl_stop_smc_fan_control(rdev); 6261 6262 tach_period = 60 * xclk * 10000 / (8 * speed); 6263 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6264 tmp |= TARGET_PERIOD(tach_period); 6265 WREG32(CG_TACH_CTRL, tmp); 6266 6267 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6268 6269 return 0; 6270 } 6271 #endif 6272 6273 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6274 { 6275 struct si_power_info *si_pi = si_get_pi(rdev); 6276 u32 tmp; 6277 6278 if (!si_pi->fan_ctrl_is_in_default_mode) { 6279 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6280 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6281 WREG32(CG_FDO_CTRL2, tmp); 6282 6283 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6284 tmp |= TMIN(si_pi->t_min); 6285 WREG32(CG_FDO_CTRL2, tmp); 6286 si_pi->fan_ctrl_is_in_default_mode = true; 6287 } 6288 } 6289 6290 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6291 { 6292 if (rdev->pm.dpm.fan.ucode_fan_control) { 6293 si_fan_ctrl_start_smc_fan_control(rdev); 6294 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6295 } 6296 } 6297 6298 static void si_thermal_initialize(struct radeon_device *rdev) 6299 { 6300 u32 tmp; 6301 6302 if (rdev->pm.fan_pulses_per_revolution) { 6303 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6304 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6305 WREG32(CG_TACH_CTRL, tmp); 6306 } 6307 6308 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6309 tmp |= TACH_PWM_RESP_RATE(0x28); 6310 WREG32(CG_FDO_CTRL2, tmp); 6311 } 6312 6313 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6314 { 6315 int ret; 6316 6317 si_thermal_initialize(rdev); 6318 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6319 if (ret) 6320 return ret; 6321 ret = si_thermal_enable_alert(rdev, true); 6322 if (ret) 6323 return ret; 6324 if (rdev->pm.dpm.fan.ucode_fan_control) { 6325 ret = si_halt_smc(rdev); 6326 if (ret) 6327 return ret; 6328 ret = si_thermal_setup_fan_table(rdev); 6329 if (ret) 6330 return ret; 6331 ret = si_resume_smc(rdev); 6332 if (ret) 6333 return ret; 6334 si_thermal_start_smc_fan_control(rdev); 6335 } 6336 6337 return 0; 6338 } 6339 6340 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6341 { 6342 if (!rdev->pm.no_fan) { 6343 si_fan_ctrl_set_default_mode(rdev); 6344 si_fan_ctrl_stop_smc_fan_control(rdev); 6345 } 6346 } 6347 6348 int si_dpm_enable(struct radeon_device *rdev) 6349 { 6350 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6351 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6352 struct si_power_info *si_pi = si_get_pi(rdev); 6353 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6354 int ret; 6355 6356 if (si_is_smc_running(rdev)) 6357 return -EINVAL; 6358 if (pi->voltage_control || si_pi->voltage_control_svi2) 6359 si_enable_voltage_control(rdev, true); 6360 if (pi->mvdd_control) 6361 si_get_mvdd_configuration(rdev); 6362 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6363 ret = si_construct_voltage_tables(rdev); 6364 if (ret) { 6365 DRM_ERROR("si_construct_voltage_tables failed\n"); 6366 return ret; 6367 } 6368 } 6369 if (eg_pi->dynamic_ac_timing) { 6370 ret = si_initialize_mc_reg_table(rdev); 6371 if (ret) 6372 eg_pi->dynamic_ac_timing = false; 6373 } 6374 if (pi->dynamic_ss) 6375 si_enable_spread_spectrum(rdev, true); 6376 if (pi->thermal_protection) 6377 si_enable_thermal_protection(rdev, true); 6378 si_setup_bsp(rdev); 6379 si_program_git(rdev); 6380 si_program_tp(rdev); 6381 si_program_tpp(rdev); 6382 si_program_sstp(rdev); 6383 si_enable_display_gap(rdev); 6384 si_program_vc(rdev); 6385 ret = si_upload_firmware(rdev); 6386 if (ret) { 6387 DRM_ERROR("si_upload_firmware failed\n"); 6388 return ret; 6389 } 6390 ret = si_process_firmware_header(rdev); 6391 if (ret) { 6392 DRM_ERROR("si_process_firmware_header failed\n"); 6393 return ret; 6394 } 6395 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6396 if (ret) { 6397 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6398 return ret; 6399 } 6400 ret = si_init_smc_table(rdev); 6401 if (ret) { 6402 DRM_ERROR("si_init_smc_table failed\n"); 6403 return ret; 6404 } 6405 ret = si_init_smc_spll_table(rdev); 6406 if (ret) { 6407 DRM_ERROR("si_init_smc_spll_table failed\n"); 6408 return ret; 6409 } 6410 ret = si_init_arb_table_index(rdev); 6411 if (ret) { 6412 DRM_ERROR("si_init_arb_table_index failed\n"); 6413 return ret; 6414 } 6415 if (eg_pi->dynamic_ac_timing) { 6416 ret = si_populate_mc_reg_table(rdev, boot_ps); 6417 if (ret) { 6418 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6419 return ret; 6420 } 6421 } 6422 ret = si_initialize_smc_cac_tables(rdev); 6423 if (ret) { 6424 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6425 return ret; 6426 } 6427 ret = si_initialize_hardware_cac_manager(rdev); 6428 if (ret) { 6429 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6430 return ret; 6431 } 6432 ret = si_initialize_smc_dte_tables(rdev); 6433 if (ret) { 6434 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6435 return ret; 6436 } 6437 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6438 if (ret) { 6439 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6440 return ret; 6441 } 6442 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6443 if (ret) { 6444 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6445 return ret; 6446 } 6447 si_program_response_times(rdev); 6448 si_program_ds_registers(rdev); 6449 si_dpm_start_smc(rdev); 6450 ret = si_notify_smc_display_change(rdev, false); 6451 if (ret) { 6452 DRM_ERROR("si_notify_smc_display_change failed\n"); 6453 return ret; 6454 } 6455 si_enable_sclk_control(rdev, true); 6456 si_start_dpm(rdev); 6457 6458 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6459 6460 si_thermal_start_thermal_controller(rdev); 6461 6462 ni_update_current_ps(rdev, boot_ps); 6463 6464 return 0; 6465 } 6466 6467 static int si_set_temperature_range(struct radeon_device *rdev) 6468 { 6469 int ret; 6470 6471 ret = si_thermal_enable_alert(rdev, false); 6472 if (ret) 6473 return ret; 6474 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6475 if (ret) 6476 return ret; 6477 ret = si_thermal_enable_alert(rdev, true); 6478 if (ret) 6479 return ret; 6480 6481 return ret; 6482 } 6483 6484 int si_dpm_late_enable(struct radeon_device *rdev) 6485 { 6486 int ret; 6487 6488 ret = si_set_temperature_range(rdev); 6489 if (ret) 6490 return ret; 6491 6492 return ret; 6493 } 6494 6495 void si_dpm_disable(struct radeon_device *rdev) 6496 { 6497 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6498 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6499 6500 if (!si_is_smc_running(rdev)) 6501 return; 6502 si_thermal_stop_thermal_controller(rdev); 6503 si_disable_ulv(rdev); 6504 si_clear_vc(rdev); 6505 if (pi->thermal_protection) 6506 si_enable_thermal_protection(rdev, false); 6507 si_enable_power_containment(rdev, boot_ps, false); 6508 si_enable_smc_cac(rdev, boot_ps, false); 6509 si_enable_spread_spectrum(rdev, false); 6510 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6511 si_stop_dpm(rdev); 6512 si_reset_to_default(rdev); 6513 si_dpm_stop_smc(rdev); 6514 si_force_switch_to_arb_f0(rdev); 6515 6516 ni_update_current_ps(rdev, boot_ps); 6517 } 6518 6519 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6520 { 6521 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6522 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6523 struct radeon_ps *new_ps = &requested_ps; 6524 6525 ni_update_requested_ps(rdev, new_ps); 6526 6527 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6528 6529 return 0; 6530 } 6531 6532 static int si_power_control_set_level(struct radeon_device *rdev) 6533 { 6534 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6535 int ret; 6536 6537 ret = si_restrict_performance_levels_before_switch(rdev); 6538 if (ret) 6539 return ret; 6540 ret = si_halt_smc(rdev); 6541 if (ret) 6542 return ret; 6543 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6544 if (ret) 6545 return ret; 6546 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6547 if (ret) 6548 return ret; 6549 ret = si_resume_smc(rdev); 6550 if (ret) 6551 return ret; 6552 ret = si_set_sw_state(rdev); 6553 if (ret) 6554 return ret; 6555 return 0; 6556 } 6557 6558 int si_dpm_set_power_state(struct radeon_device *rdev) 6559 { 6560 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6561 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6562 struct radeon_ps *old_ps = &eg_pi->current_rps; 6563 int ret; 6564 6565 ret = si_disable_ulv(rdev); 6566 if (ret) { 6567 DRM_ERROR("si_disable_ulv failed\n"); 6568 return ret; 6569 } 6570 ret = si_restrict_performance_levels_before_switch(rdev); 6571 if (ret) { 6572 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6573 return ret; 6574 } 6575 if (eg_pi->pcie_performance_request) 6576 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6577 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6578 ret = si_enable_power_containment(rdev, new_ps, false); 6579 if (ret) { 6580 DRM_ERROR("si_enable_power_containment failed\n"); 6581 return ret; 6582 } 6583 ret = si_enable_smc_cac(rdev, new_ps, false); 6584 if (ret) { 6585 DRM_ERROR("si_enable_smc_cac failed\n"); 6586 return ret; 6587 } 6588 ret = si_halt_smc(rdev); 6589 if (ret) { 6590 DRM_ERROR("si_halt_smc failed\n"); 6591 return ret; 6592 } 6593 ret = si_upload_sw_state(rdev, new_ps); 6594 if (ret) { 6595 DRM_ERROR("si_upload_sw_state failed\n"); 6596 return ret; 6597 } 6598 ret = si_upload_smc_data(rdev); 6599 if (ret) { 6600 DRM_ERROR("si_upload_smc_data failed\n"); 6601 return ret; 6602 } 6603 ret = si_upload_ulv_state(rdev); 6604 if (ret) { 6605 DRM_ERROR("si_upload_ulv_state failed\n"); 6606 return ret; 6607 } 6608 if (eg_pi->dynamic_ac_timing) { 6609 ret = si_upload_mc_reg_table(rdev, new_ps); 6610 if (ret) { 6611 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6612 return ret; 6613 } 6614 } 6615 ret = si_program_memory_timing_parameters(rdev, new_ps); 6616 if (ret) { 6617 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6618 return ret; 6619 } 6620 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6621 6622 ret = si_resume_smc(rdev); 6623 if (ret) { 6624 DRM_ERROR("si_resume_smc failed\n"); 6625 return ret; 6626 } 6627 ret = si_set_sw_state(rdev); 6628 if (ret) { 6629 DRM_ERROR("si_set_sw_state failed\n"); 6630 return ret; 6631 } 6632 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6633 si_set_vce_clock(rdev, new_ps, old_ps); 6634 if (eg_pi->pcie_performance_request) 6635 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6636 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6637 if (ret) { 6638 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6639 return ret; 6640 } 6641 ret = si_enable_smc_cac(rdev, new_ps, true); 6642 if (ret) { 6643 DRM_ERROR("si_enable_smc_cac failed\n"); 6644 return ret; 6645 } 6646 ret = si_enable_power_containment(rdev, new_ps, true); 6647 if (ret) { 6648 DRM_ERROR("si_enable_power_containment failed\n"); 6649 return ret; 6650 } 6651 6652 ret = si_power_control_set_level(rdev); 6653 if (ret) { 6654 DRM_ERROR("si_power_control_set_level failed\n"); 6655 return ret; 6656 } 6657 6658 return 0; 6659 } 6660 6661 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6662 { 6663 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6664 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6665 6666 ni_update_current_ps(rdev, new_ps); 6667 } 6668 6669 #if 0 6670 void si_dpm_reset_asic(struct radeon_device *rdev) 6671 { 6672 si_restrict_performance_levels_before_switch(rdev); 6673 si_disable_ulv(rdev); 6674 si_set_boot_state(rdev); 6675 } 6676 #endif 6677 6678 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6679 { 6680 si_program_display_gap(rdev); 6681 } 6682 6683 union power_info { 6684 struct _ATOM_POWERPLAY_INFO info; 6685 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6686 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6687 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6688 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6689 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6690 }; 6691 6692 union pplib_clock_info { 6693 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6694 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6695 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6696 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6697 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6698 }; 6699 6700 union pplib_power_state { 6701 struct _ATOM_PPLIB_STATE v1; 6702 struct _ATOM_PPLIB_STATE_V2 v2; 6703 }; 6704 6705 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6706 struct radeon_ps *rps, 6707 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6708 u8 table_rev) 6709 { 6710 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6711 rps->class = le16_to_cpu(non_clock_info->usClassification); 6712 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6713 6714 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6715 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6716 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6717 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6718 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6719 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6720 } else { 6721 rps->vclk = 0; 6722 rps->dclk = 0; 6723 } 6724 6725 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6726 rdev->pm.dpm.boot_ps = rps; 6727 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6728 rdev->pm.dpm.uvd_ps = rps; 6729 } 6730 6731 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6732 struct radeon_ps *rps, int index, 6733 union pplib_clock_info *clock_info) 6734 { 6735 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6736 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6737 struct si_power_info *si_pi = si_get_pi(rdev); 6738 struct ni_ps *ps = ni_get_ps(rps); 6739 u16 leakage_voltage; 6740 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6741 int ret; 6742 6743 ps->performance_level_count = index + 1; 6744 6745 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6746 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6747 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6748 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6749 6750 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6751 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6752 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6753 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6754 si_pi->sys_pcie_mask, 6755 si_pi->boot_pcie_gen, 6756 clock_info->si.ucPCIEGen); 6757 6758 /* patch up vddc if necessary */ 6759 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6760 &leakage_voltage); 6761 if (ret == 0) 6762 pl->vddc = leakage_voltage; 6763 6764 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6765 pi->acpi_vddc = pl->vddc; 6766 eg_pi->acpi_vddci = pl->vddci; 6767 si_pi->acpi_pcie_gen = pl->pcie_gen; 6768 } 6769 6770 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6771 index == 0) { 6772 /* XXX disable for A0 tahiti */ 6773 si_pi->ulv.supported = false; 6774 si_pi->ulv.pl = *pl; 6775 si_pi->ulv.one_pcie_lane_in_ulv = false; 6776 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6777 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6778 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6779 } 6780 6781 if (pi->min_vddc_in_table > pl->vddc) 6782 pi->min_vddc_in_table = pl->vddc; 6783 6784 if (pi->max_vddc_in_table < pl->vddc) 6785 pi->max_vddc_in_table = pl->vddc; 6786 6787 /* patch up boot state */ 6788 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6789 u16 vddc, vddci, mvdd; 6790 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6791 pl->mclk = rdev->clock.default_mclk; 6792 pl->sclk = rdev->clock.default_sclk; 6793 pl->vddc = vddc; 6794 pl->vddci = vddci; 6795 si_pi->mvdd_bootup_value = mvdd; 6796 } 6797 6798 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6799 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6800 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6801 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6802 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6803 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6804 } 6805 } 6806 6807 static int si_parse_power_table(struct radeon_device *rdev) 6808 { 6809 struct radeon_mode_info *mode_info = &rdev->mode_info; 6810 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6811 union pplib_power_state *power_state; 6812 int i, j, k, non_clock_array_index, clock_array_index; 6813 union pplib_clock_info *clock_info; 6814 struct _StateArray *state_array; 6815 struct _ClockInfoArray *clock_info_array; 6816 struct _NonClockInfoArray *non_clock_info_array; 6817 union power_info *power_info; 6818 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6819 u16 data_offset; 6820 u8 frev, crev; 6821 u8 *power_state_offset; 6822 struct ni_ps *ps; 6823 6824 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6825 &frev, &crev, &data_offset)) 6826 return -EINVAL; 6827 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6828 6829 state_array = (struct _StateArray *) 6830 (mode_info->atom_context->bios + data_offset + 6831 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6832 clock_info_array = (struct _ClockInfoArray *) 6833 (mode_info->atom_context->bios + data_offset + 6834 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6835 non_clock_info_array = (struct _NonClockInfoArray *) 6836 (mode_info->atom_context->bios + data_offset + 6837 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6838 6839 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6840 sizeof(struct radeon_ps), 6841 GFP_KERNEL); 6842 if (!rdev->pm.dpm.ps) 6843 return -ENOMEM; 6844 power_state_offset = (u8 *)state_array->states; 6845 for (i = 0; i < state_array->ucNumEntries; i++) { 6846 u8 *idx; 6847 power_state = (union pplib_power_state *)power_state_offset; 6848 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6849 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6850 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6851 if (!rdev->pm.power_state[i].clock_info) 6852 return -EINVAL; 6853 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6854 if (ps == NULL) { 6855 kfree(rdev->pm.dpm.ps); 6856 return -ENOMEM; 6857 } 6858 rdev->pm.dpm.ps[i].ps_priv = ps; 6859 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6860 non_clock_info, 6861 non_clock_info_array->ucEntrySize); 6862 k = 0; 6863 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6864 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6865 clock_array_index = idx[j]; 6866 if (clock_array_index >= clock_info_array->ucNumEntries) 6867 continue; 6868 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6869 break; 6870 clock_info = (union pplib_clock_info *) 6871 ((u8 *)&clock_info_array->clockInfo[0] + 6872 (clock_array_index * clock_info_array->ucEntrySize)); 6873 si_parse_pplib_clock_info(rdev, 6874 &rdev->pm.dpm.ps[i], k, 6875 clock_info); 6876 k++; 6877 } 6878 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6879 } 6880 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6881 6882 /* fill in the vce power states */ 6883 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6884 u32 sclk, mclk; 6885 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6886 clock_info = (union pplib_clock_info *) 6887 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6888 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6889 sclk |= clock_info->si.ucEngineClockHigh << 16; 6890 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6891 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6892 rdev->pm.dpm.vce_states[i].sclk = sclk; 6893 rdev->pm.dpm.vce_states[i].mclk = mclk; 6894 } 6895 6896 return 0; 6897 } 6898 6899 int si_dpm_init(struct radeon_device *rdev) 6900 { 6901 struct rv7xx_power_info *pi; 6902 struct evergreen_power_info *eg_pi; 6903 struct ni_power_info *ni_pi; 6904 struct si_power_info *si_pi; 6905 struct atom_clock_dividers dividers; 6906 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6907 struct pci_dev *root = rdev->pdev->bus->self; 6908 int ret; 6909 6910 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6911 if (si_pi == NULL) 6912 return -ENOMEM; 6913 rdev->pm.dpm.priv = si_pi; 6914 ni_pi = &si_pi->ni; 6915 eg_pi = &ni_pi->eg; 6916 pi = &eg_pi->rv7xx; 6917 6918 if (!pci_is_root_bus(rdev->pdev->bus)) 6919 speed_cap = pcie_get_speed_cap(root); 6920 if (speed_cap == PCI_SPEED_UNKNOWN) { 6921 si_pi->sys_pcie_mask = 0; 6922 } else { 6923 if (speed_cap == PCIE_SPEED_8_0GT) 6924 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6925 RADEON_PCIE_SPEED_50 | 6926 RADEON_PCIE_SPEED_80; 6927 else if (speed_cap == PCIE_SPEED_5_0GT) 6928 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6929 RADEON_PCIE_SPEED_50; 6930 else 6931 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6932 } 6933 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6934 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6935 6936 si_set_max_cu_value(rdev); 6937 6938 rv770_get_max_vddc(rdev); 6939 si_get_leakage_vddc(rdev); 6940 si_patch_dependency_tables_based_on_leakage(rdev); 6941 6942 pi->acpi_vddc = 0; 6943 eg_pi->acpi_vddci = 0; 6944 pi->min_vddc_in_table = 0; 6945 pi->max_vddc_in_table = 0; 6946 6947 ret = r600_get_platform_caps(rdev); 6948 if (ret) 6949 return ret; 6950 6951 ret = r600_parse_extended_power_table(rdev); 6952 if (ret) 6953 return ret; 6954 6955 ret = si_parse_power_table(rdev); 6956 if (ret) 6957 return ret; 6958 6959 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6960 kcalloc(4, 6961 sizeof(struct radeon_clock_voltage_dependency_entry), 6962 GFP_KERNEL); 6963 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6964 r600_free_extended_power_table(rdev); 6965 return -ENOMEM; 6966 } 6967 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6968 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6969 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6970 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6976 6977 if (rdev->pm.dpm.voltage_response_time == 0) 6978 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6979 if (rdev->pm.dpm.backbias_response_time == 0) 6980 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6981 6982 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6983 0, false, ÷rs); 6984 if (ret) 6985 pi->ref_div = dividers.ref_div + 1; 6986 else 6987 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6988 6989 eg_pi->smu_uvd_hs = false; 6990 6991 pi->mclk_strobe_mode_threshold = 40000; 6992 if (si_is_special_1gb_platform(rdev)) 6993 pi->mclk_stutter_mode_threshold = 0; 6994 else 6995 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6996 pi->mclk_edc_enable_threshold = 40000; 6997 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6998 6999 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7000 7001 pi->voltage_control = 7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7003 VOLTAGE_OBJ_GPIO_LUT); 7004 if (!pi->voltage_control) { 7005 si_pi->voltage_control_svi2 = 7006 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7007 VOLTAGE_OBJ_SVID2); 7008 if (si_pi->voltage_control_svi2) 7009 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7010 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7011 } 7012 7013 pi->mvdd_control = 7014 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7015 VOLTAGE_OBJ_GPIO_LUT); 7016 7017 eg_pi->vddci_control = 7018 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7019 VOLTAGE_OBJ_GPIO_LUT); 7020 if (!eg_pi->vddci_control) 7021 si_pi->vddci_control_svi2 = 7022 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7023 VOLTAGE_OBJ_SVID2); 7024 7025 si_pi->vddc_phase_shed_control = 7026 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7027 VOLTAGE_OBJ_PHASE_LUT); 7028 7029 rv770_get_engine_memory_ss(rdev); 7030 7031 pi->asi = RV770_ASI_DFLT; 7032 pi->pasi = CYPRESS_HASI_DFLT; 7033 pi->vrc = SISLANDS_VRC_DFLT; 7034 7035 pi->gfx_clock_gating = true; 7036 7037 eg_pi->sclk_deep_sleep = true; 7038 si_pi->sclk_deep_sleep_above_low = false; 7039 7040 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7041 pi->thermal_protection = true; 7042 else 7043 pi->thermal_protection = false; 7044 7045 eg_pi->dynamic_ac_timing = true; 7046 7047 eg_pi->light_sleep = true; 7048 #if defined(CONFIG_ACPI) 7049 eg_pi->pcie_performance_request = 7050 radeon_acpi_is_pcie_performance_request_supported(rdev); 7051 #else 7052 eg_pi->pcie_performance_request = false; 7053 #endif 7054 7055 si_pi->sram_end = SMC_RAM_END; 7056 7057 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7058 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7059 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7060 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7061 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7062 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7063 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7064 7065 si_initialize_powertune_defaults(rdev); 7066 7067 /* make sure dc limits are valid */ 7068 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7069 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7070 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7071 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7072 7073 si_pi->fan_ctrl_is_in_default_mode = true; 7074 7075 return 0; 7076 } 7077 7078 void si_dpm_fini(struct radeon_device *rdev) 7079 { 7080 int i; 7081 7082 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7083 kfree(rdev->pm.dpm.ps[i].ps_priv); 7084 } 7085 kfree(rdev->pm.dpm.ps); 7086 kfree(rdev->pm.dpm.priv); 7087 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7088 r600_free_extended_power_table(rdev); 7089 } 7090 7091 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7092 struct seq_file *m) 7093 { 7094 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7095 struct radeon_ps *rps = &eg_pi->current_rps; 7096 struct ni_ps *ps = ni_get_ps(rps); 7097 struct rv7xx_pl *pl; 7098 u32 current_index = 7099 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7100 CURRENT_STATE_INDEX_SHIFT; 7101 7102 if (current_index >= ps->performance_level_count) { 7103 seq_printf(m, "invalid dpm profile %d\n", current_index); 7104 } else { 7105 pl = &ps->performance_levels[current_index]; 7106 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7107 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7108 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7109 } 7110 } 7111 7112 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7113 { 7114 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7115 struct radeon_ps *rps = &eg_pi->current_rps; 7116 struct ni_ps *ps = ni_get_ps(rps); 7117 struct rv7xx_pl *pl; 7118 u32 current_index = 7119 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7120 CURRENT_STATE_INDEX_SHIFT; 7121 7122 if (current_index >= ps->performance_level_count) { 7123 return 0; 7124 } else { 7125 pl = &ps->performance_levels[current_index]; 7126 return pl->sclk; 7127 } 7128 } 7129 7130 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7131 { 7132 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7133 struct radeon_ps *rps = &eg_pi->current_rps; 7134 struct ni_ps *ps = ni_get_ps(rps); 7135 struct rv7xx_pl *pl; 7136 u32 current_index = 7137 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7138 CURRENT_STATE_INDEX_SHIFT; 7139 7140 if (current_index >= ps->performance_level_count) { 7141 return 0; 7142 } else { 7143 pl = &ps->performance_levels[current_index]; 7144 return pl->mclk; 7145 } 7146 } 7147