1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "sid.h" 27 #include "r600_dpm.h" 28 #include "si_dpm.h" 29 #include "atom.h" 30 #include <linux/math64.h> 31 #include <linux/seq_file.h> 32 33 #define MC_CG_ARB_FREQ_F0 0x0a 34 #define MC_CG_ARB_FREQ_F1 0x0b 35 #define MC_CG_ARB_FREQ_F2 0x0c 36 #define MC_CG_ARB_FREQ_F3 0x0d 37 38 #define SMC_RAM_END 0x20000 39 40 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 41 42 static const struct si_cac_config_reg cac_weights_tahiti[] = 43 { 44 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 45 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 46 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 48 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 49 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 57 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 58 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 62 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 64 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 66 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 79 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 82 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 104 { 0xFFFFFFFF } 105 }; 106 107 static const struct si_cac_config_reg lcac_tahiti[] = 108 { 109 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 110 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 111 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0xFFFFFFFF } 196 197 }; 198 199 static const struct si_cac_config_reg cac_override_tahiti[] = 200 { 201 { 0xFFFFFFFF } 202 }; 203 204 static const struct si_powertune_data powertune_data_tahiti = 205 { 206 ((1 << 16) | 27027), 207 6, 208 0, 209 4, 210 95, 211 { 212 0UL, 213 0UL, 214 4521550UL, 215 309631529UL, 216 -1270850L, 217 4513710L, 218 40 219 }, 220 595000000UL, 221 12, 222 { 223 0, 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0 231 }, 232 true 233 }; 234 235 static const struct si_dte_data dte_data_tahiti = 236 { 237 { 1159409, 0, 0, 0, 0 }, 238 { 777, 0, 0, 0, 0 }, 239 2, 240 54000, 241 127000, 242 25, 243 2, 244 10, 245 13, 246 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 247 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 248 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 249 85, 250 false 251 }; 252 253 static const struct si_dte_data dte_data_tahiti_le = 254 { 255 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 256 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 257 0x5, 258 0xAFC8, 259 0x64, 260 0x32, 261 1, 262 0, 263 0x10, 264 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 265 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 266 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 267 85, 268 true 269 }; 270 271 static const struct si_dte_data dte_data_tahiti_pro = 272 { 273 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 274 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 275 5, 276 45000, 277 100, 278 0xA, 279 1, 280 0, 281 0x10, 282 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 283 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 284 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 285 90, 286 true 287 }; 288 289 static const struct si_dte_data dte_data_new_zealand = 290 { 291 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 292 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 293 0x5, 294 0xAFC8, 295 0x69, 296 0x32, 297 1, 298 0, 299 0x10, 300 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 301 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 302 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 303 85, 304 true 305 }; 306 307 static const struct si_dte_data dte_data_aruba_pro = 308 { 309 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 310 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 311 5, 312 45000, 313 100, 314 0xA, 315 1, 316 0, 317 0x10, 318 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 319 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 320 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 321 90, 322 true 323 }; 324 325 static const struct si_dte_data dte_data_malta = 326 { 327 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 328 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 329 5, 330 45000, 331 100, 332 0xA, 333 1, 334 0, 335 0x10, 336 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 337 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 338 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 339 90, 340 true 341 }; 342 343 struct si_cac_config_reg cac_weights_pitcairn[] = 344 { 345 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 346 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 347 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 349 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 350 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 352 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 356 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 358 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 359 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 363 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 364 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 365 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 367 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 368 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 371 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 378 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 380 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 381 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 384 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 405 { 0xFFFFFFFF } 406 }; 407 408 static const struct si_cac_config_reg lcac_pitcairn[] = 409 { 410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497 }; 498 499 static const struct si_cac_config_reg cac_override_pitcairn[] = 500 { 501 { 0xFFFFFFFF } 502 }; 503 504 static const struct si_powertune_data powertune_data_pitcairn = 505 { 506 ((1 << 16) | 27027), 507 5, 508 0, 509 6, 510 100, 511 { 512 51600000UL, 513 1800000UL, 514 7194395UL, 515 309631529UL, 516 -1270850L, 517 4513710L, 518 100 519 }, 520 117830498UL, 521 12, 522 { 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0 531 }, 532 true 533 }; 534 535 static const struct si_dte_data dte_data_pitcairn = 536 { 537 { 0, 0, 0, 0, 0 }, 538 { 0, 0, 0, 0, 0 }, 539 0, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 0, 550 false 551 }; 552 553 static const struct si_dte_data dte_data_curacao_xt = 554 { 555 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 556 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 557 5, 558 45000, 559 100, 560 0xA, 561 1, 562 0, 563 0x10, 564 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 565 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 566 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 567 90, 568 true 569 }; 570 571 static const struct si_dte_data dte_data_curacao_pro = 572 { 573 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 574 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 575 5, 576 45000, 577 100, 578 0xA, 579 1, 580 0, 581 0x10, 582 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 583 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 584 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 585 90, 586 true 587 }; 588 589 static const struct si_dte_data dte_data_neptune_xt = 590 { 591 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 592 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 593 5, 594 45000, 595 100, 596 0xA, 597 1, 598 0, 599 0x10, 600 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 601 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 602 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 603 90, 604 true 605 }; 606 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 608 { 609 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 610 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 611 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 613 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 614 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 616 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 618 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 620 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 622 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 623 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 625 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 627 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 628 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 629 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 631 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 632 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 635 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 641 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 642 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 645 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 647 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 650 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 669 { 0xFFFFFFFF } 670 }; 671 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 673 { 674 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 675 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 676 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 678 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 679 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 681 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 683 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 685 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 687 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 688 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 690 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 692 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 693 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 694 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 696 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 697 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 700 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 706 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 707 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 710 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 712 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 715 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 734 { 0xFFFFFFFF } 735 }; 736 737 static const struct si_cac_config_reg cac_weights_heathrow[] = 738 { 739 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 740 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 741 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 743 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 746 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 748 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 750 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 752 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 753 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 755 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 757 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 758 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 759 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 761 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 762 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 765 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 771 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 772 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 775 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 777 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 780 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 799 { 0xFFFFFFFF } 800 }; 801 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 803 { 804 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 805 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 806 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 808 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 811 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 813 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 815 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 817 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 818 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 820 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 822 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 823 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 824 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 826 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 827 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 830 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 836 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 837 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 840 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 842 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 845 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 864 { 0xFFFFFFFF } 865 }; 866 867 static const struct si_cac_config_reg cac_weights_cape_verde[] = 868 { 869 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 870 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 871 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 873 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 876 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 878 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 880 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 882 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 883 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 885 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 887 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 888 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 889 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 891 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 892 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 895 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 901 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 902 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 905 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 907 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 910 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 929 { 0xFFFFFFFF } 930 }; 931 932 static const struct si_cac_config_reg lcac_cape_verde[] = 933 { 934 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 935 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0xFFFFFFFF } 989 }; 990 991 static const struct si_cac_config_reg cac_override_cape_verde[] = 992 { 993 { 0xFFFFFFFF } 994 }; 995 996 static const struct si_powertune_data powertune_data_cape_verde = 997 { 998 ((1 << 16) | 0x6993), 999 5, 1000 0, 1001 7, 1002 105, 1003 { 1004 0UL, 1005 0UL, 1006 7194395UL, 1007 309631529UL, 1008 -1270850L, 1009 4513710L, 1010 100 1011 }, 1012 117830498UL, 1013 12, 1014 { 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0 1023 }, 1024 true 1025 }; 1026 1027 static const struct si_dte_data dte_data_cape_verde = 1028 { 1029 { 0, 0, 0, 0, 0 }, 1030 { 0, 0, 0, 0, 0 }, 1031 0, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 0, 1042 false 1043 }; 1044 1045 static const struct si_dte_data dte_data_venus_xtx = 1046 { 1047 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1048 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1049 5, 1050 55000, 1051 0x69, 1052 0xA, 1053 1, 1054 0, 1055 0x3, 1056 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1057 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 90, 1060 true 1061 }; 1062 1063 static const struct si_dte_data dte_data_venus_xt = 1064 { 1065 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1066 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1067 5, 1068 55000, 1069 0x69, 1070 0xA, 1071 1, 1072 0, 1073 0x3, 1074 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1075 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 90, 1078 true 1079 }; 1080 1081 static const struct si_dte_data dte_data_venus_pro = 1082 { 1083 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1084 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1085 5, 1086 55000, 1087 0x69, 1088 0xA, 1089 1, 1090 0, 1091 0x3, 1092 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1093 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 90, 1096 true 1097 }; 1098 1099 struct si_cac_config_reg cac_weights_oland[] = 1100 { 1101 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1120 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1161 { 0xFFFFFFFF } 1162 }; 1163 1164 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1165 { 1166 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1185 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0xFFFFFFFF } 1227 }; 1228 1229 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1230 { 1231 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1250 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1291 { 0xFFFFFFFF } 1292 }; 1293 1294 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1295 { 1296 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1315 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1356 { 0xFFFFFFFF } 1357 }; 1358 1359 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1360 { 1361 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1380 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0xFFFFFFFF } 1422 }; 1423 1424 static const struct si_cac_config_reg lcac_oland[] = 1425 { 1426 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0xFFFFFFFF } 1469 }; 1470 1471 static const struct si_cac_config_reg lcac_mars_pro[] = 1472 { 1473 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0xFFFFFFFF } 1516 }; 1517 1518 static const struct si_cac_config_reg cac_override_oland[] = 1519 { 1520 { 0xFFFFFFFF } 1521 }; 1522 1523 static const struct si_powertune_data powertune_data_oland = 1524 { 1525 ((1 << 16) | 0x6993), 1526 5, 1527 0, 1528 7, 1529 105, 1530 { 1531 0UL, 1532 0UL, 1533 7194395UL, 1534 309631529UL, 1535 -1270850L, 1536 4513710L, 1537 100 1538 }, 1539 117830498UL, 1540 12, 1541 { 1542 0, 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0 1550 }, 1551 true 1552 }; 1553 1554 static const struct si_powertune_data powertune_data_mars_pro = 1555 { 1556 ((1 << 16) | 0x6993), 1557 5, 1558 0, 1559 7, 1560 105, 1561 { 1562 0UL, 1563 0UL, 1564 7194395UL, 1565 309631529UL, 1566 -1270850L, 1567 4513710L, 1568 100 1569 }, 1570 117830498UL, 1571 12, 1572 { 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0 1581 }, 1582 true 1583 }; 1584 1585 static const struct si_dte_data dte_data_oland = 1586 { 1587 { 0, 0, 0, 0, 0 }, 1588 { 0, 0, 0, 0, 0 }, 1589 0, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 0, 1600 false 1601 }; 1602 1603 static const struct si_dte_data dte_data_mars_pro = 1604 { 1605 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1606 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1607 5, 1608 55000, 1609 105, 1610 0xA, 1611 1, 1612 0, 1613 0x10, 1614 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1615 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1616 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1617 90, 1618 true 1619 }; 1620 1621 static const struct si_dte_data dte_data_sun_xt = 1622 { 1623 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1624 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1625 5, 1626 55000, 1627 105, 1628 0xA, 1629 1, 1630 0, 1631 0x10, 1632 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1633 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1634 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1635 90, 1636 true 1637 }; 1638 1639 1640 static const struct si_cac_config_reg cac_weights_hainan[] = 1641 { 1642 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1661 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1702 { 0xFFFFFFFF } 1703 }; 1704 1705 static const struct si_powertune_data powertune_data_hainan = 1706 { 1707 ((1 << 16) | 0x6993), 1708 5, 1709 0, 1710 9, 1711 105, 1712 { 1713 0UL, 1714 0UL, 1715 7194395UL, 1716 309631529UL, 1717 -1270850L, 1718 4513710L, 1719 100 1720 }, 1721 117830498UL, 1722 12, 1723 { 1724 0, 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0 1732 }, 1733 true 1734 }; 1735 1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1740 1741 static int si_populate_voltage_value(struct radeon_device *rdev, 1742 const struct atom_voltage_table *table, 1743 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1744 static int si_get_std_voltage_value(struct radeon_device *rdev, 1745 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1746 u16 *std_voltage); 1747 static int si_write_smc_soft_register(struct radeon_device *rdev, 1748 u16 reg_offset, u32 value); 1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1750 struct rv7xx_pl *pl, 1751 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1752 static int si_calculate_sclk_params(struct radeon_device *rdev, 1753 u32 engine_clock, 1754 SISLANDS_SMC_SCLK_VALUE *sclk); 1755 1756 extern void si_update_cg(struct radeon_device *rdev, 1757 u32 block, bool enable); 1758 1759 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1760 { 1761 struct si_power_info *pi = rdev->pm.dpm.priv; 1762 1763 return pi; 1764 } 1765 1766 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1767 u16 v, s32 t, u32 ileakage, u32 *leakage) 1768 { 1769 s64 kt, kv, leakage_w, i_leakage, vddc; 1770 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1771 s64 tmp; 1772 1773 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1774 vddc = div64_s64(drm_int2fixp(v), 1000); 1775 temperature = div64_s64(drm_int2fixp(t), 1000); 1776 1777 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1778 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1779 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1780 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1781 t_ref = drm_int2fixp(coeff->t_ref); 1782 1783 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1784 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1785 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1786 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1787 1788 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1789 1790 *leakage = drm_fixp2int(leakage_w * 1000); 1791 } 1792 1793 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1794 const struct ni_leakage_coeffients *coeff, 1795 u16 v, 1796 s32 t, 1797 u32 i_leakage, 1798 u32 *leakage) 1799 { 1800 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1801 } 1802 1803 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1804 const u32 fixed_kt, u16 v, 1805 u32 ileakage, u32 *leakage) 1806 { 1807 s64 kt, kv, leakage_w, i_leakage, vddc; 1808 1809 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1810 vddc = div64_s64(drm_int2fixp(v), 1000); 1811 1812 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1813 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1814 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1815 1816 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1817 1818 *leakage = drm_fixp2int(leakage_w * 1000); 1819 } 1820 1821 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1822 const struct ni_leakage_coeffients *coeff, 1823 const u32 fixed_kt, 1824 u16 v, 1825 u32 i_leakage, 1826 u32 *leakage) 1827 { 1828 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1829 } 1830 1831 1832 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1833 struct si_dte_data *dte_data) 1834 { 1835 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1836 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1837 u32 k = dte_data->k; 1838 u32 t_max = dte_data->max_t; 1839 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1840 u32 t_0 = dte_data->t0; 1841 u32 i; 1842 1843 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1844 dte_data->tdep_count = 3; 1845 1846 for (i = 0; i < k; i++) { 1847 dte_data->r[i] = 1848 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1849 (p_limit2 * (u32)100); 1850 } 1851 1852 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1853 1854 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1855 dte_data->tdep_r[i] = dte_data->r[4]; 1856 } 1857 } else { 1858 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1859 } 1860 } 1861 1862 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1863 { 1864 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1865 struct si_power_info *si_pi = si_get_pi(rdev); 1866 bool update_dte_from_pl2 = false; 1867 1868 if (rdev->family == CHIP_TAHITI) { 1869 si_pi->cac_weights = cac_weights_tahiti; 1870 si_pi->lcac_config = lcac_tahiti; 1871 si_pi->cac_override = cac_override_tahiti; 1872 si_pi->powertune_data = &powertune_data_tahiti; 1873 si_pi->dte_data = dte_data_tahiti; 1874 1875 switch (rdev->pdev->device) { 1876 case 0x6798: 1877 si_pi->dte_data.enable_dte_by_default = true; 1878 break; 1879 case 0x6799: 1880 si_pi->dte_data = dte_data_new_zealand; 1881 break; 1882 case 0x6790: 1883 case 0x6791: 1884 case 0x6792: 1885 case 0x679E: 1886 si_pi->dte_data = dte_data_aruba_pro; 1887 update_dte_from_pl2 = true; 1888 break; 1889 case 0x679B: 1890 si_pi->dte_data = dte_data_malta; 1891 update_dte_from_pl2 = true; 1892 break; 1893 case 0x679A: 1894 si_pi->dte_data = dte_data_tahiti_pro; 1895 update_dte_from_pl2 = true; 1896 break; 1897 default: 1898 if (si_pi->dte_data.enable_dte_by_default == true) 1899 DRM_ERROR("DTE is not enabled!\n"); 1900 break; 1901 } 1902 } else if (rdev->family == CHIP_PITCAIRN) { 1903 switch (rdev->pdev->device) { 1904 case 0x6810: 1905 case 0x6818: 1906 si_pi->cac_weights = cac_weights_pitcairn; 1907 si_pi->lcac_config = lcac_pitcairn; 1908 si_pi->cac_override = cac_override_pitcairn; 1909 si_pi->powertune_data = &powertune_data_pitcairn; 1910 si_pi->dte_data = dte_data_curacao_xt; 1911 update_dte_from_pl2 = true; 1912 break; 1913 case 0x6819: 1914 case 0x6811: 1915 si_pi->cac_weights = cac_weights_pitcairn; 1916 si_pi->lcac_config = lcac_pitcairn; 1917 si_pi->cac_override = cac_override_pitcairn; 1918 si_pi->powertune_data = &powertune_data_pitcairn; 1919 si_pi->dte_data = dte_data_curacao_pro; 1920 update_dte_from_pl2 = true; 1921 break; 1922 case 0x6800: 1923 case 0x6806: 1924 si_pi->cac_weights = cac_weights_pitcairn; 1925 si_pi->lcac_config = lcac_pitcairn; 1926 si_pi->cac_override = cac_override_pitcairn; 1927 si_pi->powertune_data = &powertune_data_pitcairn; 1928 si_pi->dte_data = dte_data_neptune_xt; 1929 update_dte_from_pl2 = true; 1930 break; 1931 default: 1932 si_pi->cac_weights = cac_weights_pitcairn; 1933 si_pi->lcac_config = lcac_pitcairn; 1934 si_pi->cac_override = cac_override_pitcairn; 1935 si_pi->powertune_data = &powertune_data_pitcairn; 1936 si_pi->dte_data = dte_data_pitcairn; 1937 break; 1938 } 1939 } else if (rdev->family == CHIP_VERDE) { 1940 si_pi->lcac_config = lcac_cape_verde; 1941 si_pi->cac_override = cac_override_cape_verde; 1942 si_pi->powertune_data = &powertune_data_cape_verde; 1943 1944 switch (rdev->pdev->device) { 1945 case 0x683B: 1946 case 0x683F: 1947 case 0x6829: 1948 case 0x6835: 1949 si_pi->cac_weights = cac_weights_cape_verde_pro; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x6825: 1953 case 0x6827: 1954 si_pi->cac_weights = cac_weights_heathrow; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x6824: 1958 case 0x682D: 1959 si_pi->cac_weights = cac_weights_chelsea_xt; 1960 si_pi->dte_data = dte_data_cape_verde; 1961 break; 1962 case 0x682F: 1963 si_pi->cac_weights = cac_weights_chelsea_pro; 1964 si_pi->dte_data = dte_data_cape_verde; 1965 break; 1966 case 0x6820: 1967 si_pi->cac_weights = cac_weights_heathrow; 1968 si_pi->dte_data = dte_data_venus_xtx; 1969 break; 1970 case 0x6821: 1971 si_pi->cac_weights = cac_weights_heathrow; 1972 si_pi->dte_data = dte_data_venus_xt; 1973 break; 1974 case 0x6823: 1975 si_pi->cac_weights = cac_weights_chelsea_pro; 1976 si_pi->dte_data = dte_data_venus_pro; 1977 break; 1978 case 0x682B: 1979 si_pi->cac_weights = cac_weights_chelsea_pro; 1980 si_pi->dte_data = dte_data_venus_pro; 1981 break; 1982 default: 1983 si_pi->cac_weights = cac_weights_cape_verde; 1984 si_pi->dte_data = dte_data_cape_verde; 1985 break; 1986 } 1987 } else if (rdev->family == CHIP_OLAND) { 1988 switch (rdev->pdev->device) { 1989 case 0x6601: 1990 case 0x6621: 1991 case 0x6603: 1992 si_pi->cac_weights = cac_weights_mars_pro; 1993 si_pi->lcac_config = lcac_mars_pro; 1994 si_pi->cac_override = cac_override_oland; 1995 si_pi->powertune_data = &powertune_data_mars_pro; 1996 si_pi->dte_data = dte_data_mars_pro; 1997 update_dte_from_pl2 = true; 1998 break; 1999 case 0x6600: 2000 case 0x6606: 2001 case 0x6620: 2002 si_pi->cac_weights = cac_weights_mars_xt; 2003 si_pi->lcac_config = lcac_mars_pro; 2004 si_pi->cac_override = cac_override_oland; 2005 si_pi->powertune_data = &powertune_data_mars_pro; 2006 si_pi->dte_data = dte_data_mars_pro; 2007 update_dte_from_pl2 = true; 2008 break; 2009 case 0x6611: 2010 si_pi->cac_weights = cac_weights_oland_pro; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 case 0x6610: 2018 si_pi->cac_weights = cac_weights_oland_xt; 2019 si_pi->lcac_config = lcac_mars_pro; 2020 si_pi->cac_override = cac_override_oland; 2021 si_pi->powertune_data = &powertune_data_mars_pro; 2022 si_pi->dte_data = dte_data_mars_pro; 2023 update_dte_from_pl2 = true; 2024 break; 2025 default: 2026 si_pi->cac_weights = cac_weights_oland; 2027 si_pi->lcac_config = lcac_oland; 2028 si_pi->cac_override = cac_override_oland; 2029 si_pi->powertune_data = &powertune_data_oland; 2030 si_pi->dte_data = dte_data_oland; 2031 break; 2032 } 2033 } else if (rdev->family == CHIP_HAINAN) { 2034 si_pi->cac_weights = cac_weights_hainan; 2035 si_pi->lcac_config = lcac_oland; 2036 si_pi->cac_override = cac_override_oland; 2037 si_pi->powertune_data = &powertune_data_hainan; 2038 si_pi->dte_data = dte_data_sun_xt; 2039 update_dte_from_pl2 = true; 2040 } else { 2041 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2042 return; 2043 } 2044 2045 ni_pi->enable_power_containment = false; 2046 ni_pi->enable_cac = false; 2047 ni_pi->enable_sq_ramping = false; 2048 si_pi->enable_dte = false; 2049 2050 if (si_pi->powertune_data->enable_powertune_by_default) { 2051 ni_pi->enable_power_containment= true; 2052 ni_pi->enable_cac = true; 2053 if (si_pi->dte_data.enable_dte_by_default) { 2054 si_pi->enable_dte = true; 2055 if (update_dte_from_pl2) 2056 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2057 2058 } 2059 ni_pi->enable_sq_ramping = true; 2060 } 2061 2062 ni_pi->driver_calculate_cac_leakage = true; 2063 ni_pi->cac_configuration_required = true; 2064 2065 if (ni_pi->cac_configuration_required) { 2066 ni_pi->support_cac_long_term_average = true; 2067 si_pi->dyn_powertune_data.l2_lta_window_size = 2068 si_pi->powertune_data->l2_lta_window_size_default; 2069 si_pi->dyn_powertune_data.lts_truncate = 2070 si_pi->powertune_data->lts_truncate_default; 2071 } else { 2072 ni_pi->support_cac_long_term_average = false; 2073 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2074 si_pi->dyn_powertune_data.lts_truncate = 0; 2075 } 2076 2077 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2078 } 2079 2080 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2081 { 2082 return 1; 2083 } 2084 2085 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2086 { 2087 u32 xclk; 2088 u32 wintime; 2089 u32 cac_window; 2090 u32 cac_window_size; 2091 2092 xclk = radeon_get_xclk(rdev); 2093 2094 if (xclk == 0) 2095 return 0; 2096 2097 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2098 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2099 2100 wintime = (cac_window_size * 100) / xclk; 2101 2102 return wintime; 2103 } 2104 2105 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2106 { 2107 return power_in_watts; 2108 } 2109 2110 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2111 bool adjust_polarity, 2112 u32 tdp_adjustment, 2113 u32 *tdp_limit, 2114 u32 *near_tdp_limit) 2115 { 2116 u32 adjustment_delta, max_tdp_limit; 2117 2118 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2119 return -EINVAL; 2120 2121 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2122 2123 if (adjust_polarity) { 2124 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2126 } else { 2127 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2128 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2129 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2130 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2131 else 2132 *near_tdp_limit = 0; 2133 } 2134 2135 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2136 return -EINVAL; 2137 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2138 return -EINVAL; 2139 2140 return 0; 2141 } 2142 2143 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2144 struct radeon_ps *radeon_state) 2145 { 2146 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2147 struct si_power_info *si_pi = si_get_pi(rdev); 2148 2149 if (ni_pi->enable_power_containment) { 2150 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2151 PP_SIslands_PAPMParameters *papm_parm; 2152 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2153 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2154 u32 tdp_limit; 2155 u32 near_tdp_limit; 2156 int ret; 2157 2158 if (scaling_factor == 0) 2159 return -EINVAL; 2160 2161 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2162 2163 ret = si_calculate_adjusted_tdp_limits(rdev, 2164 false, /* ??? */ 2165 rdev->pm.dpm.tdp_adjustment, 2166 &tdp_limit, 2167 &near_tdp_limit); 2168 if (ret) 2169 return ret; 2170 2171 smc_table->dpm2Params.TDPLimit = 2172 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2173 smc_table->dpm2Params.NearTDPLimit = 2174 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2175 smc_table->dpm2Params.SafePowerLimit = 2176 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2177 2178 ret = si_copy_bytes_to_smc(rdev, 2179 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2180 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2181 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2182 sizeof(u32) * 3, 2183 si_pi->sram_end); 2184 if (ret) 2185 return ret; 2186 2187 if (si_pi->enable_ppm) { 2188 papm_parm = &si_pi->papm_parm; 2189 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2190 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2191 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2192 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2193 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2194 papm_parm->PlatformPowerLimit = 0xffffffff; 2195 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2196 2197 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2198 (u8 *)papm_parm, 2199 sizeof(PP_SIslands_PAPMParameters), 2200 si_pi->sram_end); 2201 if (ret) 2202 return ret; 2203 } 2204 } 2205 return 0; 2206 } 2207 2208 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2209 struct radeon_ps *radeon_state) 2210 { 2211 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2212 struct si_power_info *si_pi = si_get_pi(rdev); 2213 2214 if (ni_pi->enable_power_containment) { 2215 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2216 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2217 int ret; 2218 2219 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2220 2221 smc_table->dpm2Params.NearTDPLimit = 2222 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2223 smc_table->dpm2Params.SafePowerLimit = 2224 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2225 2226 ret = si_copy_bytes_to_smc(rdev, 2227 (si_pi->state_table_start + 2228 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2229 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2230 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2231 sizeof(u32) * 2, 2232 si_pi->sram_end); 2233 if (ret) 2234 return ret; 2235 } 2236 2237 return 0; 2238 } 2239 2240 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2241 const u16 prev_std_vddc, 2242 const u16 curr_std_vddc) 2243 { 2244 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2245 u64 prev_vddc = (u64)prev_std_vddc; 2246 u64 curr_vddc = (u64)curr_std_vddc; 2247 u64 pwr_efficiency_ratio, n, d; 2248 2249 if ((prev_vddc == 0) || (curr_vddc == 0)) 2250 return 0; 2251 2252 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2253 d = prev_vddc * prev_vddc; 2254 pwr_efficiency_ratio = div64_u64(n, d); 2255 2256 if (pwr_efficiency_ratio > (u64)0xFFFF) 2257 return 0; 2258 2259 return (u16)pwr_efficiency_ratio; 2260 } 2261 2262 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2263 struct radeon_ps *radeon_state) 2264 { 2265 struct si_power_info *si_pi = si_get_pi(rdev); 2266 2267 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2268 radeon_state->vclk && radeon_state->dclk) 2269 return true; 2270 2271 return false; 2272 } 2273 2274 static int si_populate_power_containment_values(struct radeon_device *rdev, 2275 struct radeon_ps *radeon_state, 2276 SISLANDS_SMC_SWSTATE *smc_state) 2277 { 2278 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2279 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2280 struct ni_ps *state = ni_get_ps(radeon_state); 2281 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2282 u32 prev_sclk; 2283 u32 max_sclk; 2284 u32 min_sclk; 2285 u16 prev_std_vddc; 2286 u16 curr_std_vddc; 2287 int i; 2288 u16 pwr_efficiency_ratio; 2289 u8 max_ps_percent; 2290 bool disable_uvd_power_tune; 2291 int ret; 2292 2293 if (ni_pi->enable_power_containment == false) 2294 return 0; 2295 2296 if (state->performance_level_count == 0) 2297 return -EINVAL; 2298 2299 if (smc_state->levelCount != state->performance_level_count) 2300 return -EINVAL; 2301 2302 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2303 2304 smc_state->levels[0].dpm2.MaxPS = 0; 2305 smc_state->levels[0].dpm2.NearTDPDec = 0; 2306 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2307 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2308 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2309 2310 for (i = 1; i < state->performance_level_count; i++) { 2311 prev_sclk = state->performance_levels[i-1].sclk; 2312 max_sclk = state->performance_levels[i].sclk; 2313 if (i == 1) 2314 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2315 else 2316 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2317 2318 if (prev_sclk > max_sclk) 2319 return -EINVAL; 2320 2321 if ((max_ps_percent == 0) || 2322 (prev_sclk == max_sclk) || 2323 disable_uvd_power_tune) { 2324 min_sclk = max_sclk; 2325 } else if (i == 1) { 2326 min_sclk = prev_sclk; 2327 } else { 2328 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2329 } 2330 2331 if (min_sclk < state->performance_levels[0].sclk) 2332 min_sclk = state->performance_levels[0].sclk; 2333 2334 if (min_sclk == 0) 2335 return -EINVAL; 2336 2337 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2338 state->performance_levels[i-1].vddc, &vddc); 2339 if (ret) 2340 return ret; 2341 2342 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2343 if (ret) 2344 return ret; 2345 2346 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2347 state->performance_levels[i].vddc, &vddc); 2348 if (ret) 2349 return ret; 2350 2351 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2352 if (ret) 2353 return ret; 2354 2355 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2356 prev_std_vddc, curr_std_vddc); 2357 2358 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2359 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2360 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2361 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2362 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2363 } 2364 2365 return 0; 2366 } 2367 2368 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2369 struct radeon_ps *radeon_state, 2370 SISLANDS_SMC_SWSTATE *smc_state) 2371 { 2372 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2373 struct ni_ps *state = ni_get_ps(radeon_state); 2374 u32 sq_power_throttle, sq_power_throttle2; 2375 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2376 int i; 2377 2378 if (state->performance_level_count == 0) 2379 return -EINVAL; 2380 2381 if (smc_state->levelCount != state->performance_level_count) 2382 return -EINVAL; 2383 2384 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2385 return -EINVAL; 2386 2387 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2388 enable_sq_ramping = false; 2389 2390 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2391 enable_sq_ramping = false; 2392 2393 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2394 enable_sq_ramping = false; 2395 2396 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2397 enable_sq_ramping = false; 2398 2399 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2400 enable_sq_ramping = false; 2401 2402 for (i = 0; i < state->performance_level_count; i++) { 2403 sq_power_throttle = 0; 2404 sq_power_throttle2 = 0; 2405 2406 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2407 enable_sq_ramping) { 2408 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2409 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2410 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2411 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2412 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2413 } else { 2414 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2415 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2416 } 2417 2418 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2419 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2420 } 2421 2422 return 0; 2423 } 2424 2425 static int si_enable_power_containment(struct radeon_device *rdev, 2426 struct radeon_ps *radeon_new_state, 2427 bool enable) 2428 { 2429 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2430 PPSMC_Result smc_result; 2431 int ret = 0; 2432 2433 if (ni_pi->enable_power_containment) { 2434 if (enable) { 2435 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2436 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2437 if (smc_result != PPSMC_Result_OK) { 2438 ret = -EINVAL; 2439 ni_pi->pc_enabled = false; 2440 } else { 2441 ni_pi->pc_enabled = true; 2442 } 2443 } 2444 } else { 2445 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2446 if (smc_result != PPSMC_Result_OK) 2447 ret = -EINVAL; 2448 ni_pi->pc_enabled = false; 2449 } 2450 } 2451 2452 return ret; 2453 } 2454 2455 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2456 { 2457 struct si_power_info *si_pi = si_get_pi(rdev); 2458 int ret = 0; 2459 struct si_dte_data *dte_data = &si_pi->dte_data; 2460 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2461 u32 table_size; 2462 u8 tdep_count; 2463 u32 i; 2464 2465 if (dte_data == NULL) 2466 si_pi->enable_dte = false; 2467 2468 if (si_pi->enable_dte == false) 2469 return 0; 2470 2471 if (dte_data->k <= 0) 2472 return -EINVAL; 2473 2474 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2475 if (dte_tables == NULL) { 2476 si_pi->enable_dte = false; 2477 return -ENOMEM; 2478 } 2479 2480 table_size = dte_data->k; 2481 2482 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2483 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2484 2485 tdep_count = dte_data->tdep_count; 2486 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2487 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2488 2489 dte_tables->K = cpu_to_be32(table_size); 2490 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2491 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2492 dte_tables->WindowSize = dte_data->window_size; 2493 dte_tables->temp_select = dte_data->temp_select; 2494 dte_tables->DTE_mode = dte_data->dte_mode; 2495 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2496 2497 if (tdep_count > 0) 2498 table_size--; 2499 2500 for (i = 0; i < table_size; i++) { 2501 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2502 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2503 } 2504 2505 dte_tables->Tdep_count = tdep_count; 2506 2507 for (i = 0; i < (u32)tdep_count; i++) { 2508 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2509 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2510 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2511 } 2512 2513 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2514 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2515 kfree(dte_tables); 2516 2517 return ret; 2518 } 2519 2520 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2521 u16 *max, u16 *min) 2522 { 2523 struct si_power_info *si_pi = si_get_pi(rdev); 2524 struct radeon_cac_leakage_table *table = 2525 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2526 u32 i; 2527 u32 v0_loadline; 2528 2529 2530 if (table == NULL) 2531 return -EINVAL; 2532 2533 *max = 0; 2534 *min = 0xFFFF; 2535 2536 for (i = 0; i < table->count; i++) { 2537 if (table->entries[i].vddc > *max) 2538 *max = table->entries[i].vddc; 2539 if (table->entries[i].vddc < *min) 2540 *min = table->entries[i].vddc; 2541 } 2542 2543 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2544 return -EINVAL; 2545 2546 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2547 2548 if (v0_loadline > 0xFFFFUL) 2549 return -EINVAL; 2550 2551 *min = (u16)v0_loadline; 2552 2553 if ((*min > *max) || (*max == 0) || (*min == 0)) 2554 return -EINVAL; 2555 2556 return 0; 2557 } 2558 2559 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2560 { 2561 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2562 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2563 } 2564 2565 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2566 PP_SIslands_CacConfig *cac_tables, 2567 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2568 u16 t0, u16 t_step) 2569 { 2570 struct si_power_info *si_pi = si_get_pi(rdev); 2571 u32 leakage; 2572 unsigned int i, j; 2573 s32 t; 2574 u32 smc_leakage; 2575 u32 scaling_factor; 2576 u16 voltage; 2577 2578 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2579 2580 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2581 t = (1000 * (i * t_step + t0)); 2582 2583 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2584 voltage = vddc_max - (vddc_step * j); 2585 2586 si_calculate_leakage_for_v_and_t(rdev, 2587 &si_pi->powertune_data->leakage_coefficients, 2588 voltage, 2589 t, 2590 si_pi->dyn_powertune_data.cac_leakage, 2591 &leakage); 2592 2593 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2594 2595 if (smc_leakage > 0xFFFF) 2596 smc_leakage = 0xFFFF; 2597 2598 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2599 cpu_to_be16((u16)smc_leakage); 2600 } 2601 } 2602 return 0; 2603 } 2604 2605 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2606 PP_SIslands_CacConfig *cac_tables, 2607 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2608 { 2609 struct si_power_info *si_pi = si_get_pi(rdev); 2610 u32 leakage; 2611 unsigned int i, j; 2612 u32 smc_leakage; 2613 u32 scaling_factor; 2614 u16 voltage; 2615 2616 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2617 2618 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2619 voltage = vddc_max - (vddc_step * j); 2620 2621 si_calculate_leakage_for_v(rdev, 2622 &si_pi->powertune_data->leakage_coefficients, 2623 si_pi->powertune_data->fixed_kt, 2624 voltage, 2625 si_pi->dyn_powertune_data.cac_leakage, 2626 &leakage); 2627 2628 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2629 2630 if (smc_leakage > 0xFFFF) 2631 smc_leakage = 0xFFFF; 2632 2633 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2634 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2635 cpu_to_be16((u16)smc_leakage); 2636 } 2637 return 0; 2638 } 2639 2640 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2641 { 2642 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2643 struct si_power_info *si_pi = si_get_pi(rdev); 2644 PP_SIslands_CacConfig *cac_tables = NULL; 2645 u16 vddc_max, vddc_min, vddc_step; 2646 u16 t0, t_step; 2647 u32 load_line_slope, reg; 2648 int ret = 0; 2649 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2650 2651 if (ni_pi->enable_cac == false) 2652 return 0; 2653 2654 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2655 if (!cac_tables) 2656 return -ENOMEM; 2657 2658 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2659 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2660 WREG32(CG_CAC_CTRL, reg); 2661 2662 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2663 si_pi->dyn_powertune_data.dc_pwr_value = 2664 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2665 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2666 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2667 2668 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2669 2670 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2671 if (ret) 2672 goto done_free; 2673 2674 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2675 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2676 t_step = 4; 2677 t0 = 60; 2678 2679 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2680 ret = si_init_dte_leakage_table(rdev, cac_tables, 2681 vddc_max, vddc_min, vddc_step, 2682 t0, t_step); 2683 else 2684 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2685 vddc_max, vddc_min, vddc_step); 2686 if (ret) 2687 goto done_free; 2688 2689 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2690 2691 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2692 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2693 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2694 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2695 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2696 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2697 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2698 cac_tables->calculation_repeats = cpu_to_be32(2); 2699 cac_tables->dc_cac = cpu_to_be32(0); 2700 cac_tables->log2_PG_LKG_SCALE = 12; 2701 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2702 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2703 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2704 2705 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2706 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2707 2708 if (ret) 2709 goto done_free; 2710 2711 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2712 2713 done_free: 2714 if (ret) { 2715 ni_pi->enable_cac = false; 2716 ni_pi->enable_power_containment = false; 2717 } 2718 2719 kfree(cac_tables); 2720 2721 return 0; 2722 } 2723 2724 static int si_program_cac_config_registers(struct radeon_device *rdev, 2725 const struct si_cac_config_reg *cac_config_regs) 2726 { 2727 const struct si_cac_config_reg *config_regs = cac_config_regs; 2728 u32 data = 0, offset; 2729 2730 if (!config_regs) 2731 return -EINVAL; 2732 2733 while (config_regs->offset != 0xFFFFFFFF) { 2734 switch (config_regs->type) { 2735 case SISLANDS_CACCONFIG_CGIND: 2736 offset = SMC_CG_IND_START + config_regs->offset; 2737 if (offset < SMC_CG_IND_END) 2738 data = RREG32_SMC(offset); 2739 break; 2740 default: 2741 data = RREG32(config_regs->offset << 2); 2742 break; 2743 } 2744 2745 data &= ~config_regs->mask; 2746 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2747 2748 switch (config_regs->type) { 2749 case SISLANDS_CACCONFIG_CGIND: 2750 offset = SMC_CG_IND_START + config_regs->offset; 2751 if (offset < SMC_CG_IND_END) 2752 WREG32_SMC(offset, data); 2753 break; 2754 default: 2755 WREG32(config_regs->offset << 2, data); 2756 break; 2757 } 2758 config_regs++; 2759 } 2760 return 0; 2761 } 2762 2763 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2764 { 2765 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2766 struct si_power_info *si_pi = si_get_pi(rdev); 2767 int ret; 2768 2769 if ((ni_pi->enable_cac == false) || 2770 (ni_pi->cac_configuration_required == false)) 2771 return 0; 2772 2773 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2774 if (ret) 2775 return ret; 2776 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2777 if (ret) 2778 return ret; 2779 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2780 if (ret) 2781 return ret; 2782 2783 return 0; 2784 } 2785 2786 static int si_enable_smc_cac(struct radeon_device *rdev, 2787 struct radeon_ps *radeon_new_state, 2788 bool enable) 2789 { 2790 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2791 struct si_power_info *si_pi = si_get_pi(rdev); 2792 PPSMC_Result smc_result; 2793 int ret = 0; 2794 2795 if (ni_pi->enable_cac) { 2796 if (enable) { 2797 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2798 if (ni_pi->support_cac_long_term_average) { 2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2800 if (smc_result != PPSMC_Result_OK) 2801 ni_pi->support_cac_long_term_average = false; 2802 } 2803 2804 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2805 if (smc_result != PPSMC_Result_OK) { 2806 ret = -EINVAL; 2807 ni_pi->cac_enabled = false; 2808 } else { 2809 ni_pi->cac_enabled = true; 2810 } 2811 2812 if (si_pi->enable_dte) { 2813 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2814 if (smc_result != PPSMC_Result_OK) 2815 ret = -EINVAL; 2816 } 2817 } 2818 } else if (ni_pi->cac_enabled) { 2819 if (si_pi->enable_dte) 2820 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2821 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2823 2824 ni_pi->cac_enabled = false; 2825 2826 if (ni_pi->support_cac_long_term_average) 2827 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2828 } 2829 } 2830 return ret; 2831 } 2832 2833 static int si_init_smc_spll_table(struct radeon_device *rdev) 2834 { 2835 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2836 struct si_power_info *si_pi = si_get_pi(rdev); 2837 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2838 SISLANDS_SMC_SCLK_VALUE sclk_params; 2839 u32 fb_div, p_div; 2840 u32 clk_s, clk_v; 2841 u32 sclk = 0; 2842 int ret = 0; 2843 u32 tmp; 2844 int i; 2845 2846 if (si_pi->spll_table_start == 0) 2847 return -EINVAL; 2848 2849 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2850 if (spll_table == NULL) 2851 return -ENOMEM; 2852 2853 for (i = 0; i < 256; i++) { 2854 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2855 if (ret) 2856 break; 2857 2858 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2859 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2860 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2861 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2862 2863 fb_div &= ~0x00001FFF; 2864 fb_div >>= 1; 2865 clk_v >>= 6; 2866 2867 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2868 ret = -EINVAL; 2869 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2870 ret = -EINVAL; 2871 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2872 ret = -EINVAL; 2873 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2874 ret = -EINVAL; 2875 2876 if (ret) 2877 break; 2878 2879 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2880 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2881 spll_table->freq[i] = cpu_to_be32(tmp); 2882 2883 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2884 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2885 spll_table->ss[i] = cpu_to_be32(tmp); 2886 2887 sclk += 512; 2888 } 2889 2890 2891 if (!ret) 2892 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2893 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2894 si_pi->sram_end); 2895 2896 if (ret) 2897 ni_pi->enable_power_containment = false; 2898 2899 kfree(spll_table); 2900 2901 return ret; 2902 } 2903 2904 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2905 struct radeon_ps *rps) 2906 { 2907 struct ni_ps *ps = ni_get_ps(rps); 2908 struct radeon_clock_and_voltage_limits *max_limits; 2909 bool disable_mclk_switching = false; 2910 bool disable_sclk_switching = false; 2911 u32 mclk, sclk; 2912 u16 vddc, vddci; 2913 int i; 2914 2915 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2916 ni_dpm_vblank_too_short(rdev)) 2917 disable_mclk_switching = true; 2918 2919 if (rps->vclk || rps->dclk) { 2920 disable_mclk_switching = true; 2921 disable_sclk_switching = true; 2922 } 2923 2924 if (rdev->pm.dpm.ac_power) 2925 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2926 else 2927 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2928 2929 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2930 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2931 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2932 } 2933 if (rdev->pm.dpm.ac_power == false) { 2934 for (i = 0; i < ps->performance_level_count; i++) { 2935 if (ps->performance_levels[i].mclk > max_limits->mclk) 2936 ps->performance_levels[i].mclk = max_limits->mclk; 2937 if (ps->performance_levels[i].sclk > max_limits->sclk) 2938 ps->performance_levels[i].sclk = max_limits->sclk; 2939 if (ps->performance_levels[i].vddc > max_limits->vddc) 2940 ps->performance_levels[i].vddc = max_limits->vddc; 2941 if (ps->performance_levels[i].vddci > max_limits->vddci) 2942 ps->performance_levels[i].vddci = max_limits->vddci; 2943 } 2944 } 2945 2946 /* XXX validate the min clocks required for display */ 2947 2948 if (disable_mclk_switching) { 2949 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2950 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2951 } else { 2952 mclk = ps->performance_levels[0].mclk; 2953 vddci = ps->performance_levels[0].vddci; 2954 } 2955 2956 if (disable_sclk_switching) { 2957 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 2958 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 2959 } else { 2960 sclk = ps->performance_levels[0].sclk; 2961 vddc = ps->performance_levels[0].vddc; 2962 } 2963 2964 /* adjusted low state */ 2965 ps->performance_levels[0].sclk = sclk; 2966 ps->performance_levels[0].mclk = mclk; 2967 ps->performance_levels[0].vddc = vddc; 2968 ps->performance_levels[0].vddci = vddci; 2969 2970 if (disable_sclk_switching) { 2971 sclk = ps->performance_levels[0].sclk; 2972 for (i = 1; i < ps->performance_level_count; i++) { 2973 if (sclk < ps->performance_levels[i].sclk) 2974 sclk = ps->performance_levels[i].sclk; 2975 } 2976 for (i = 0; i < ps->performance_level_count; i++) { 2977 ps->performance_levels[i].sclk = sclk; 2978 ps->performance_levels[i].vddc = vddc; 2979 } 2980 } else { 2981 for (i = 1; i < ps->performance_level_count; i++) { 2982 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2983 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2984 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2985 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2986 } 2987 } 2988 2989 if (disable_mclk_switching) { 2990 mclk = ps->performance_levels[0].mclk; 2991 for (i = 1; i < ps->performance_level_count; i++) { 2992 if (mclk < ps->performance_levels[i].mclk) 2993 mclk = ps->performance_levels[i].mclk; 2994 } 2995 for (i = 0; i < ps->performance_level_count; i++) { 2996 ps->performance_levels[i].mclk = mclk; 2997 ps->performance_levels[i].vddci = vddci; 2998 } 2999 } else { 3000 for (i = 1; i < ps->performance_level_count; i++) { 3001 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3002 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3003 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3004 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3005 } 3006 } 3007 3008 for (i = 0; i < ps->performance_level_count; i++) 3009 btc_adjust_clock_combinations(rdev, max_limits, 3010 &ps->performance_levels[i]); 3011 3012 for (i = 0; i < ps->performance_level_count; i++) { 3013 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3014 ps->performance_levels[i].sclk, 3015 max_limits->vddc, &ps->performance_levels[i].vddc); 3016 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3017 ps->performance_levels[i].mclk, 3018 max_limits->vddci, &ps->performance_levels[i].vddci); 3019 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3020 ps->performance_levels[i].mclk, 3021 max_limits->vddc, &ps->performance_levels[i].vddc); 3022 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3023 rdev->clock.current_dispclk, 3024 max_limits->vddc, &ps->performance_levels[i].vddc); 3025 } 3026 3027 for (i = 0; i < ps->performance_level_count; i++) { 3028 btc_apply_voltage_delta_rules(rdev, 3029 max_limits->vddc, max_limits->vddci, 3030 &ps->performance_levels[i].vddc, 3031 &ps->performance_levels[i].vddci); 3032 } 3033 3034 ps->dc_compatible = true; 3035 for (i = 0; i < ps->performance_level_count; i++) { 3036 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3037 ps->dc_compatible = false; 3038 } 3039 3040 } 3041 3042 #if 0 3043 static int si_read_smc_soft_register(struct radeon_device *rdev, 3044 u16 reg_offset, u32 *value) 3045 { 3046 struct si_power_info *si_pi = si_get_pi(rdev); 3047 3048 return si_read_smc_sram_dword(rdev, 3049 si_pi->soft_regs_start + reg_offset, value, 3050 si_pi->sram_end); 3051 } 3052 #endif 3053 3054 static int si_write_smc_soft_register(struct radeon_device *rdev, 3055 u16 reg_offset, u32 value) 3056 { 3057 struct si_power_info *si_pi = si_get_pi(rdev); 3058 3059 return si_write_smc_sram_dword(rdev, 3060 si_pi->soft_regs_start + reg_offset, 3061 value, si_pi->sram_end); 3062 } 3063 3064 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3065 { 3066 bool ret = false; 3067 u32 tmp, width, row, column, bank, density; 3068 bool is_memory_gddr5, is_special; 3069 3070 tmp = RREG32(MC_SEQ_MISC0); 3071 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3072 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3073 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3074 3075 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3076 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3077 3078 tmp = RREG32(MC_ARB_RAMCFG); 3079 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3080 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3081 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3082 3083 density = (1 << (row + column - 20 + bank)) * width; 3084 3085 if ((rdev->pdev->device == 0x6819) && 3086 is_memory_gddr5 && is_special && (density == 0x400)) 3087 ret = true; 3088 3089 return ret; 3090 } 3091 3092 static void si_get_leakage_vddc(struct radeon_device *rdev) 3093 { 3094 struct si_power_info *si_pi = si_get_pi(rdev); 3095 u16 vddc, count = 0; 3096 int i, ret; 3097 3098 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3099 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3100 3101 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3102 si_pi->leakage_voltage.entries[count].voltage = vddc; 3103 si_pi->leakage_voltage.entries[count].leakage_index = 3104 SISLANDS_LEAKAGE_INDEX0 + i; 3105 count++; 3106 } 3107 } 3108 si_pi->leakage_voltage.count = count; 3109 } 3110 3111 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3112 u32 index, u16 *leakage_voltage) 3113 { 3114 struct si_power_info *si_pi = si_get_pi(rdev); 3115 int i; 3116 3117 if (leakage_voltage == NULL) 3118 return -EINVAL; 3119 3120 if ((index & 0xff00) != 0xff00) 3121 return -EINVAL; 3122 3123 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3124 return -EINVAL; 3125 3126 if (index < SISLANDS_LEAKAGE_INDEX0) 3127 return -EINVAL; 3128 3129 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3130 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3131 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3132 return 0; 3133 } 3134 } 3135 return -EAGAIN; 3136 } 3137 3138 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3139 { 3140 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3141 bool want_thermal_protection; 3142 enum radeon_dpm_event_src dpm_event_src; 3143 3144 switch (sources) { 3145 case 0: 3146 default: 3147 want_thermal_protection = false; 3148 break; 3149 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3150 want_thermal_protection = true; 3151 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3152 break; 3153 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3154 want_thermal_protection = true; 3155 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3156 break; 3157 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3158 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3159 want_thermal_protection = true; 3160 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3161 break; 3162 } 3163 3164 if (want_thermal_protection) { 3165 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3166 if (pi->thermal_protection) 3167 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3168 } else { 3169 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3170 } 3171 } 3172 3173 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3174 enum radeon_dpm_auto_throttle_src source, 3175 bool enable) 3176 { 3177 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3178 3179 if (enable) { 3180 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3181 pi->active_auto_throttle_sources |= 1 << source; 3182 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3183 } 3184 } else { 3185 if (pi->active_auto_throttle_sources & (1 << source)) { 3186 pi->active_auto_throttle_sources &= ~(1 << source); 3187 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3188 } 3189 } 3190 } 3191 3192 static void si_start_dpm(struct radeon_device *rdev) 3193 { 3194 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3195 } 3196 3197 static void si_stop_dpm(struct radeon_device *rdev) 3198 { 3199 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3200 } 3201 3202 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3203 { 3204 if (enable) 3205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3206 else 3207 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3208 3209 } 3210 3211 #if 0 3212 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3213 u32 thermal_level) 3214 { 3215 PPSMC_Result ret; 3216 3217 if (thermal_level == 0) { 3218 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3219 if (ret == PPSMC_Result_OK) 3220 return 0; 3221 else 3222 return -EINVAL; 3223 } 3224 return 0; 3225 } 3226 3227 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3228 { 3229 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3230 } 3231 #endif 3232 3233 #if 0 3234 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3235 { 3236 if (ac_power) 3237 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3238 0 : -EINVAL; 3239 3240 return 0; 3241 } 3242 #endif 3243 3244 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3245 PPSMC_Msg msg, u32 parameter) 3246 { 3247 WREG32(SMC_SCRATCH0, parameter); 3248 return si_send_msg_to_smc(rdev, msg); 3249 } 3250 3251 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3252 { 3253 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3254 return -EINVAL; 3255 3256 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3257 0 : -EINVAL; 3258 } 3259 3260 int si_dpm_force_performance_level(struct radeon_device *rdev, 3261 enum radeon_dpm_forced_level level) 3262 { 3263 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3264 struct ni_ps *ps = ni_get_ps(rps); 3265 u32 levels = ps->performance_level_count; 3266 3267 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3268 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3269 return -EINVAL; 3270 3271 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3272 return -EINVAL; 3273 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3274 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3275 return -EINVAL; 3276 3277 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3278 return -EINVAL; 3279 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3280 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3281 return -EINVAL; 3282 3283 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3284 return -EINVAL; 3285 } 3286 3287 rdev->pm.dpm.forced_level = level; 3288 3289 return 0; 3290 } 3291 3292 static int si_set_boot_state(struct radeon_device *rdev) 3293 { 3294 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3295 0 : -EINVAL; 3296 } 3297 3298 static int si_set_sw_state(struct radeon_device *rdev) 3299 { 3300 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3301 0 : -EINVAL; 3302 } 3303 3304 static int si_halt_smc(struct radeon_device *rdev) 3305 { 3306 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3307 return -EINVAL; 3308 3309 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3310 0 : -EINVAL; 3311 } 3312 3313 static int si_resume_smc(struct radeon_device *rdev) 3314 { 3315 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3316 return -EINVAL; 3317 3318 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3319 0 : -EINVAL; 3320 } 3321 3322 static void si_dpm_start_smc(struct radeon_device *rdev) 3323 { 3324 si_program_jump_on_start(rdev); 3325 si_start_smc(rdev); 3326 si_start_smc_clock(rdev); 3327 } 3328 3329 static void si_dpm_stop_smc(struct radeon_device *rdev) 3330 { 3331 si_reset_smc(rdev); 3332 si_stop_smc_clock(rdev); 3333 } 3334 3335 static int si_process_firmware_header(struct radeon_device *rdev) 3336 { 3337 struct si_power_info *si_pi = si_get_pi(rdev); 3338 u32 tmp; 3339 int ret; 3340 3341 ret = si_read_smc_sram_dword(rdev, 3342 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3343 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3344 &tmp, si_pi->sram_end); 3345 if (ret) 3346 return ret; 3347 3348 si_pi->state_table_start = tmp; 3349 3350 ret = si_read_smc_sram_dword(rdev, 3351 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3352 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3353 &tmp, si_pi->sram_end); 3354 if (ret) 3355 return ret; 3356 3357 si_pi->soft_regs_start = tmp; 3358 3359 ret = si_read_smc_sram_dword(rdev, 3360 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3361 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3362 &tmp, si_pi->sram_end); 3363 if (ret) 3364 return ret; 3365 3366 si_pi->mc_reg_table_start = tmp; 3367 3368 ret = si_read_smc_sram_dword(rdev, 3369 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3370 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3371 &tmp, si_pi->sram_end); 3372 if (ret) 3373 return ret; 3374 3375 si_pi->arb_table_start = tmp; 3376 3377 ret = si_read_smc_sram_dword(rdev, 3378 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3379 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3380 &tmp, si_pi->sram_end); 3381 if (ret) 3382 return ret; 3383 3384 si_pi->cac_table_start = tmp; 3385 3386 ret = si_read_smc_sram_dword(rdev, 3387 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3388 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3389 &tmp, si_pi->sram_end); 3390 if (ret) 3391 return ret; 3392 3393 si_pi->dte_table_start = tmp; 3394 3395 ret = si_read_smc_sram_dword(rdev, 3396 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3397 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3398 &tmp, si_pi->sram_end); 3399 if (ret) 3400 return ret; 3401 3402 si_pi->spll_table_start = tmp; 3403 3404 ret = si_read_smc_sram_dword(rdev, 3405 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3406 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3407 &tmp, si_pi->sram_end); 3408 if (ret) 3409 return ret; 3410 3411 si_pi->papm_cfg_table_start = tmp; 3412 3413 return ret; 3414 } 3415 3416 static void si_read_clock_registers(struct radeon_device *rdev) 3417 { 3418 struct si_power_info *si_pi = si_get_pi(rdev); 3419 3420 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3421 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3422 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3423 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3424 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3425 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3426 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3427 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3428 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3429 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3430 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3431 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3432 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3433 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3434 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3435 } 3436 3437 static void si_enable_thermal_protection(struct radeon_device *rdev, 3438 bool enable) 3439 { 3440 if (enable) 3441 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3442 else 3443 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3444 } 3445 3446 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3447 { 3448 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3449 } 3450 3451 #if 0 3452 static int si_enter_ulp_state(struct radeon_device *rdev) 3453 { 3454 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3455 3456 udelay(25000); 3457 3458 return 0; 3459 } 3460 3461 static int si_exit_ulp_state(struct radeon_device *rdev) 3462 { 3463 int i; 3464 3465 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3466 3467 udelay(7000); 3468 3469 for (i = 0; i < rdev->usec_timeout; i++) { 3470 if (RREG32(SMC_RESP_0) == 1) 3471 break; 3472 udelay(1000); 3473 } 3474 3475 return 0; 3476 } 3477 #endif 3478 3479 static int si_notify_smc_display_change(struct radeon_device *rdev, 3480 bool has_display) 3481 { 3482 PPSMC_Msg msg = has_display ? 3483 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3484 3485 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3486 0 : -EINVAL; 3487 } 3488 3489 static void si_program_response_times(struct radeon_device *rdev) 3490 { 3491 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3492 u32 vddc_dly, acpi_dly, vbi_dly; 3493 u32 reference_clock; 3494 3495 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3496 3497 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3498 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3499 3500 if (voltage_response_time == 0) 3501 voltage_response_time = 1000; 3502 3503 acpi_delay_time = 15000; 3504 vbi_time_out = 100000; 3505 3506 reference_clock = radeon_get_xclk(rdev); 3507 3508 vddc_dly = (voltage_response_time * reference_clock) / 100; 3509 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3510 vbi_dly = (vbi_time_out * reference_clock) / 100; 3511 3512 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3513 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3514 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3515 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3516 } 3517 3518 static void si_program_ds_registers(struct radeon_device *rdev) 3519 { 3520 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3521 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3522 3523 if (eg_pi->sclk_deep_sleep) { 3524 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3525 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3526 ~AUTOSCALE_ON_SS_CLEAR); 3527 } 3528 } 3529 3530 static void si_program_display_gap(struct radeon_device *rdev) 3531 { 3532 u32 tmp, pipe; 3533 int i; 3534 3535 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3536 if (rdev->pm.dpm.new_active_crtc_count > 0) 3537 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3538 else 3539 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3540 3541 if (rdev->pm.dpm.new_active_crtc_count > 1) 3542 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3543 else 3544 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3545 3546 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3547 3548 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3549 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3550 3551 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3552 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3553 /* find the first active crtc */ 3554 for (i = 0; i < rdev->num_crtc; i++) { 3555 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3556 break; 3557 } 3558 if (i == rdev->num_crtc) 3559 pipe = 0; 3560 else 3561 pipe = i; 3562 3563 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3564 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3565 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3566 } 3567 3568 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3569 } 3570 3571 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3572 { 3573 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3574 3575 if (enable) { 3576 if (pi->sclk_ss) 3577 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3578 } else { 3579 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3580 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3581 } 3582 } 3583 3584 static void si_setup_bsp(struct radeon_device *rdev) 3585 { 3586 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3587 u32 xclk = radeon_get_xclk(rdev); 3588 3589 r600_calculate_u_and_p(pi->asi, 3590 xclk, 3591 16, 3592 &pi->bsp, 3593 &pi->bsu); 3594 3595 r600_calculate_u_and_p(pi->pasi, 3596 xclk, 3597 16, 3598 &pi->pbsp, 3599 &pi->pbsu); 3600 3601 3602 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3603 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3604 3605 WREG32(CG_BSP, pi->dsp); 3606 } 3607 3608 static void si_program_git(struct radeon_device *rdev) 3609 { 3610 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3611 } 3612 3613 static void si_program_tp(struct radeon_device *rdev) 3614 { 3615 int i; 3616 enum r600_td td = R600_TD_DFLT; 3617 3618 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3619 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3620 3621 if (td == R600_TD_AUTO) 3622 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3623 else 3624 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3625 3626 if (td == R600_TD_UP) 3627 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3628 3629 if (td == R600_TD_DOWN) 3630 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3631 } 3632 3633 static void si_program_tpp(struct radeon_device *rdev) 3634 { 3635 WREG32(CG_TPC, R600_TPC_DFLT); 3636 } 3637 3638 static void si_program_sstp(struct radeon_device *rdev) 3639 { 3640 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3641 } 3642 3643 static void si_enable_display_gap(struct radeon_device *rdev) 3644 { 3645 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3646 3647 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3648 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3649 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3650 3651 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3652 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3653 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3654 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3655 } 3656 3657 static void si_program_vc(struct radeon_device *rdev) 3658 { 3659 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3660 3661 WREG32(CG_FTV, pi->vrc); 3662 } 3663 3664 static void si_clear_vc(struct radeon_device *rdev) 3665 { 3666 WREG32(CG_FTV, 0); 3667 } 3668 3669 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3670 { 3671 u8 mc_para_index; 3672 3673 if (memory_clock < 10000) 3674 mc_para_index = 0; 3675 else if (memory_clock >= 80000) 3676 mc_para_index = 0x0f; 3677 else 3678 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3679 return mc_para_index; 3680 } 3681 3682 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3683 { 3684 u8 mc_para_index; 3685 3686 if (strobe_mode) { 3687 if (memory_clock < 12500) 3688 mc_para_index = 0x00; 3689 else if (memory_clock > 47500) 3690 mc_para_index = 0x0f; 3691 else 3692 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3693 } else { 3694 if (memory_clock < 65000) 3695 mc_para_index = 0x00; 3696 else if (memory_clock > 135000) 3697 mc_para_index = 0x0f; 3698 else 3699 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3700 } 3701 return mc_para_index; 3702 } 3703 3704 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3705 { 3706 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3707 bool strobe_mode = false; 3708 u8 result = 0; 3709 3710 if (mclk <= pi->mclk_strobe_mode_threshold) 3711 strobe_mode = true; 3712 3713 if (pi->mem_gddr5) 3714 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3715 else 3716 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3717 3718 if (strobe_mode) 3719 result |= SISLANDS_SMC_STROBE_ENABLE; 3720 3721 return result; 3722 } 3723 3724 static int si_upload_firmware(struct radeon_device *rdev) 3725 { 3726 struct si_power_info *si_pi = si_get_pi(rdev); 3727 int ret; 3728 3729 si_reset_smc(rdev); 3730 si_stop_smc_clock(rdev); 3731 3732 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3733 3734 return ret; 3735 } 3736 3737 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3738 const struct atom_voltage_table *table, 3739 const struct radeon_phase_shedding_limits_table *limits) 3740 { 3741 u32 data, num_bits, num_levels; 3742 3743 if ((table == NULL) || (limits == NULL)) 3744 return false; 3745 3746 data = table->mask_low; 3747 3748 num_bits = hweight32(data); 3749 3750 if (num_bits == 0) 3751 return false; 3752 3753 num_levels = (1 << num_bits); 3754 3755 if (table->count != num_levels) 3756 return false; 3757 3758 if (limits->count != (num_levels - 1)) 3759 return false; 3760 3761 return true; 3762 } 3763 3764 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3765 u32 max_voltage_steps, 3766 struct atom_voltage_table *voltage_table) 3767 { 3768 unsigned int i, diff; 3769 3770 if (voltage_table->count <= max_voltage_steps) 3771 return; 3772 3773 diff = voltage_table->count - max_voltage_steps; 3774 3775 for (i= 0; i < max_voltage_steps; i++) 3776 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3777 3778 voltage_table->count = max_voltage_steps; 3779 } 3780 3781 static int si_construct_voltage_tables(struct radeon_device *rdev) 3782 { 3783 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3784 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3785 struct si_power_info *si_pi = si_get_pi(rdev); 3786 int ret; 3787 3788 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3789 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3790 if (ret) 3791 return ret; 3792 3793 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3794 si_trim_voltage_table_to_fit_state_table(rdev, 3795 SISLANDS_MAX_NO_VREG_STEPS, 3796 &eg_pi->vddc_voltage_table); 3797 3798 if (eg_pi->vddci_control) { 3799 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3800 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3801 if (ret) 3802 return ret; 3803 3804 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3805 si_trim_voltage_table_to_fit_state_table(rdev, 3806 SISLANDS_MAX_NO_VREG_STEPS, 3807 &eg_pi->vddci_voltage_table); 3808 } 3809 3810 if (pi->mvdd_control) { 3811 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3812 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3813 3814 if (ret) { 3815 pi->mvdd_control = false; 3816 return ret; 3817 } 3818 3819 if (si_pi->mvdd_voltage_table.count == 0) { 3820 pi->mvdd_control = false; 3821 return -EINVAL; 3822 } 3823 3824 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3825 si_trim_voltage_table_to_fit_state_table(rdev, 3826 SISLANDS_MAX_NO_VREG_STEPS, 3827 &si_pi->mvdd_voltage_table); 3828 } 3829 3830 if (si_pi->vddc_phase_shed_control) { 3831 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3832 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3833 if (ret) 3834 si_pi->vddc_phase_shed_control = false; 3835 3836 if ((si_pi->vddc_phase_shed_table.count == 0) || 3837 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3838 si_pi->vddc_phase_shed_control = false; 3839 } 3840 3841 return 0; 3842 } 3843 3844 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3845 const struct atom_voltage_table *voltage_table, 3846 SISLANDS_SMC_STATETABLE *table) 3847 { 3848 unsigned int i; 3849 3850 for (i = 0; i < voltage_table->count; i++) 3851 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3852 } 3853 3854 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3855 SISLANDS_SMC_STATETABLE *table) 3856 { 3857 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3858 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3859 struct si_power_info *si_pi = si_get_pi(rdev); 3860 u8 i; 3861 3862 if (eg_pi->vddc_voltage_table.count) { 3863 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3864 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3865 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3866 3867 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3868 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3869 table->maxVDDCIndexInPPTable = i; 3870 break; 3871 } 3872 } 3873 } 3874 3875 if (eg_pi->vddci_voltage_table.count) { 3876 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3877 3878 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3879 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3880 } 3881 3882 3883 if (si_pi->mvdd_voltage_table.count) { 3884 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3885 3886 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3887 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3888 } 3889 3890 if (si_pi->vddc_phase_shed_control) { 3891 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3892 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3893 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3894 3895 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3896 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3897 3898 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3899 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3900 } else { 3901 si_pi->vddc_phase_shed_control = false; 3902 } 3903 } 3904 3905 return 0; 3906 } 3907 3908 static int si_populate_voltage_value(struct radeon_device *rdev, 3909 const struct atom_voltage_table *table, 3910 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3911 { 3912 unsigned int i; 3913 3914 for (i = 0; i < table->count; i++) { 3915 if (value <= table->entries[i].value) { 3916 voltage->index = (u8)i; 3917 voltage->value = cpu_to_be16(table->entries[i].value); 3918 break; 3919 } 3920 } 3921 3922 if (i >= table->count) 3923 return -EINVAL; 3924 3925 return 0; 3926 } 3927 3928 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3929 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3930 { 3931 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3932 struct si_power_info *si_pi = si_get_pi(rdev); 3933 3934 if (pi->mvdd_control) { 3935 if (mclk <= pi->mvdd_split_frequency) 3936 voltage->index = 0; 3937 else 3938 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3939 3940 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3941 } 3942 return 0; 3943 } 3944 3945 static int si_get_std_voltage_value(struct radeon_device *rdev, 3946 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3947 u16 *std_voltage) 3948 { 3949 u16 v_index; 3950 bool voltage_found = false; 3951 *std_voltage = be16_to_cpu(voltage->value); 3952 3953 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3954 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3955 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3956 return -EINVAL; 3957 3958 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3959 if (be16_to_cpu(voltage->value) == 3960 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3961 voltage_found = true; 3962 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3963 *std_voltage = 3964 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3965 else 3966 *std_voltage = 3967 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3968 break; 3969 } 3970 } 3971 3972 if (!voltage_found) { 3973 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3974 if (be16_to_cpu(voltage->value) <= 3975 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3976 voltage_found = true; 3977 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3978 *std_voltage = 3979 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3980 else 3981 *std_voltage = 3982 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3983 break; 3984 } 3985 } 3986 } 3987 } else { 3988 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3989 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3990 } 3991 } 3992 3993 return 0; 3994 } 3995 3996 static int si_populate_std_voltage_value(struct radeon_device *rdev, 3997 u16 value, u8 index, 3998 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3999 { 4000 voltage->index = index; 4001 voltage->value = cpu_to_be16(value); 4002 4003 return 0; 4004 } 4005 4006 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4007 const struct radeon_phase_shedding_limits_table *limits, 4008 u16 voltage, u32 sclk, u32 mclk, 4009 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4010 { 4011 unsigned int i; 4012 4013 for (i = 0; i < limits->count; i++) { 4014 if ((voltage <= limits->entries[i].voltage) && 4015 (sclk <= limits->entries[i].sclk) && 4016 (mclk <= limits->entries[i].mclk)) 4017 break; 4018 } 4019 4020 smc_voltage->phase_settings = (u8)i; 4021 4022 return 0; 4023 } 4024 4025 static int si_init_arb_table_index(struct radeon_device *rdev) 4026 { 4027 struct si_power_info *si_pi = si_get_pi(rdev); 4028 u32 tmp; 4029 int ret; 4030 4031 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4032 if (ret) 4033 return ret; 4034 4035 tmp &= 0x00FFFFFF; 4036 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4037 4038 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4039 } 4040 4041 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4042 { 4043 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4044 } 4045 4046 static int si_reset_to_default(struct radeon_device *rdev) 4047 { 4048 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4049 0 : -EINVAL; 4050 } 4051 4052 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4053 { 4054 struct si_power_info *si_pi = si_get_pi(rdev); 4055 u32 tmp; 4056 int ret; 4057 4058 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4059 &tmp, si_pi->sram_end); 4060 if (ret) 4061 return ret; 4062 4063 tmp = (tmp >> 24) & 0xff; 4064 4065 if (tmp == MC_CG_ARB_FREQ_F0) 4066 return 0; 4067 4068 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4069 } 4070 4071 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4072 u32 engine_clock) 4073 { 4074 u32 dram_rows; 4075 u32 dram_refresh_rate; 4076 u32 mc_arb_rfsh_rate; 4077 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4078 4079 if (tmp >= 4) 4080 dram_rows = 16384; 4081 else 4082 dram_rows = 1 << (tmp + 10); 4083 4084 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4085 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4086 4087 return mc_arb_rfsh_rate; 4088 } 4089 4090 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4091 struct rv7xx_pl *pl, 4092 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4093 { 4094 u32 dram_timing; 4095 u32 dram_timing2; 4096 u32 burst_time; 4097 4098 arb_regs->mc_arb_rfsh_rate = 4099 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4100 4101 radeon_atom_set_engine_dram_timings(rdev, 4102 pl->sclk, 4103 pl->mclk); 4104 4105 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4106 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4107 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4108 4109 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4110 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4111 arb_regs->mc_arb_burst_time = (u8)burst_time; 4112 4113 return 0; 4114 } 4115 4116 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4117 struct radeon_ps *radeon_state, 4118 unsigned int first_arb_set) 4119 { 4120 struct si_power_info *si_pi = si_get_pi(rdev); 4121 struct ni_ps *state = ni_get_ps(radeon_state); 4122 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4123 int i, ret = 0; 4124 4125 for (i = 0; i < state->performance_level_count; i++) { 4126 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4127 if (ret) 4128 break; 4129 ret = si_copy_bytes_to_smc(rdev, 4130 si_pi->arb_table_start + 4131 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4132 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4133 (u8 *)&arb_regs, 4134 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4135 si_pi->sram_end); 4136 if (ret) 4137 break; 4138 } 4139 4140 return ret; 4141 } 4142 4143 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4144 struct radeon_ps *radeon_new_state) 4145 { 4146 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4147 SISLANDS_DRIVER_STATE_ARB_INDEX); 4148 } 4149 4150 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4151 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4152 { 4153 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4154 struct si_power_info *si_pi = si_get_pi(rdev); 4155 4156 if (pi->mvdd_control) 4157 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4158 si_pi->mvdd_bootup_value, voltage); 4159 4160 return 0; 4161 } 4162 4163 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4164 struct radeon_ps *radeon_initial_state, 4165 SISLANDS_SMC_STATETABLE *table) 4166 { 4167 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4168 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4169 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4170 struct si_power_info *si_pi = si_get_pi(rdev); 4171 u32 reg; 4172 int ret; 4173 4174 table->initialState.levels[0].mclk.vDLL_CNTL = 4175 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4176 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4177 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4178 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4179 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4180 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4181 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4182 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4183 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4184 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4185 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4186 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4187 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4188 table->initialState.levels[0].mclk.vMPLL_SS = 4189 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4190 table->initialState.levels[0].mclk.vMPLL_SS2 = 4191 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4192 4193 table->initialState.levels[0].mclk.mclk_value = 4194 cpu_to_be32(initial_state->performance_levels[0].mclk); 4195 4196 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4197 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4198 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4199 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4200 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4201 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4202 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4203 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4204 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4205 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4206 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4207 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4208 4209 table->initialState.levels[0].sclk.sclk_value = 4210 cpu_to_be32(initial_state->performance_levels[0].sclk); 4211 4212 table->initialState.levels[0].arbRefreshState = 4213 SISLANDS_INITIAL_STATE_ARB_INDEX; 4214 4215 table->initialState.levels[0].ACIndex = 0; 4216 4217 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4218 initial_state->performance_levels[0].vddc, 4219 &table->initialState.levels[0].vddc); 4220 4221 if (!ret) { 4222 u16 std_vddc; 4223 4224 ret = si_get_std_voltage_value(rdev, 4225 &table->initialState.levels[0].vddc, 4226 &std_vddc); 4227 if (!ret) 4228 si_populate_std_voltage_value(rdev, std_vddc, 4229 table->initialState.levels[0].vddc.index, 4230 &table->initialState.levels[0].std_vddc); 4231 } 4232 4233 if (eg_pi->vddci_control) 4234 si_populate_voltage_value(rdev, 4235 &eg_pi->vddci_voltage_table, 4236 initial_state->performance_levels[0].vddci, 4237 &table->initialState.levels[0].vddci); 4238 4239 if (si_pi->vddc_phase_shed_control) 4240 si_populate_phase_shedding_value(rdev, 4241 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4242 initial_state->performance_levels[0].vddc, 4243 initial_state->performance_levels[0].sclk, 4244 initial_state->performance_levels[0].mclk, 4245 &table->initialState.levels[0].vddc); 4246 4247 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4248 4249 reg = CG_R(0xffff) | CG_L(0); 4250 table->initialState.levels[0].aT = cpu_to_be32(reg); 4251 4252 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4253 4254 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4255 4256 if (pi->mem_gddr5) { 4257 table->initialState.levels[0].strobeMode = 4258 si_get_strobe_mode_settings(rdev, 4259 initial_state->performance_levels[0].mclk); 4260 4261 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4262 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4263 else 4264 table->initialState.levels[0].mcFlags = 0; 4265 } 4266 4267 table->initialState.levelCount = 1; 4268 4269 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4270 4271 table->initialState.levels[0].dpm2.MaxPS = 0; 4272 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4273 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4274 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4275 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4276 4277 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4278 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4279 4280 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4281 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4282 4283 return 0; 4284 } 4285 4286 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4287 SISLANDS_SMC_STATETABLE *table) 4288 { 4289 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4290 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4291 struct si_power_info *si_pi = si_get_pi(rdev); 4292 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4293 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4294 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4295 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4296 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4297 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4298 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4299 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4300 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4301 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4302 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4303 u32 reg; 4304 int ret; 4305 4306 table->ACPIState = table->initialState; 4307 4308 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4309 4310 if (pi->acpi_vddc) { 4311 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4312 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4313 if (!ret) { 4314 u16 std_vddc; 4315 4316 ret = si_get_std_voltage_value(rdev, 4317 &table->ACPIState.levels[0].vddc, &std_vddc); 4318 if (!ret) 4319 si_populate_std_voltage_value(rdev, std_vddc, 4320 table->ACPIState.levels[0].vddc.index, 4321 &table->ACPIState.levels[0].std_vddc); 4322 } 4323 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4324 4325 if (si_pi->vddc_phase_shed_control) { 4326 si_populate_phase_shedding_value(rdev, 4327 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4328 pi->acpi_vddc, 4329 0, 4330 0, 4331 &table->ACPIState.levels[0].vddc); 4332 } 4333 } else { 4334 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4335 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4336 if (!ret) { 4337 u16 std_vddc; 4338 4339 ret = si_get_std_voltage_value(rdev, 4340 &table->ACPIState.levels[0].vddc, &std_vddc); 4341 4342 if (!ret) 4343 si_populate_std_voltage_value(rdev, std_vddc, 4344 table->ACPIState.levels[0].vddc.index, 4345 &table->ACPIState.levels[0].std_vddc); 4346 } 4347 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4348 si_pi->sys_pcie_mask, 4349 si_pi->boot_pcie_gen, 4350 RADEON_PCIE_GEN1); 4351 4352 if (si_pi->vddc_phase_shed_control) 4353 si_populate_phase_shedding_value(rdev, 4354 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4355 pi->min_vddc_in_table, 4356 0, 4357 0, 4358 &table->ACPIState.levels[0].vddc); 4359 } 4360 4361 if (pi->acpi_vddc) { 4362 if (eg_pi->acpi_vddci) 4363 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4364 eg_pi->acpi_vddci, 4365 &table->ACPIState.levels[0].vddci); 4366 } 4367 4368 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4369 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4370 4371 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4372 4373 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4374 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4375 4376 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4377 cpu_to_be32(dll_cntl); 4378 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4379 cpu_to_be32(mclk_pwrmgt_cntl); 4380 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4381 cpu_to_be32(mpll_ad_func_cntl); 4382 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4383 cpu_to_be32(mpll_dq_func_cntl); 4384 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4385 cpu_to_be32(mpll_func_cntl); 4386 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4387 cpu_to_be32(mpll_func_cntl_1); 4388 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4389 cpu_to_be32(mpll_func_cntl_2); 4390 table->ACPIState.levels[0].mclk.vMPLL_SS = 4391 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4392 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4393 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4394 4395 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4396 cpu_to_be32(spll_func_cntl); 4397 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4398 cpu_to_be32(spll_func_cntl_2); 4399 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4400 cpu_to_be32(spll_func_cntl_3); 4401 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4402 cpu_to_be32(spll_func_cntl_4); 4403 4404 table->ACPIState.levels[0].mclk.mclk_value = 0; 4405 table->ACPIState.levels[0].sclk.sclk_value = 0; 4406 4407 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4408 4409 if (eg_pi->dynamic_ac_timing) 4410 table->ACPIState.levels[0].ACIndex = 0; 4411 4412 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4413 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4414 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4415 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4416 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4417 4418 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4419 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4420 4421 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4422 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4423 4424 return 0; 4425 } 4426 4427 static int si_populate_ulv_state(struct radeon_device *rdev, 4428 SISLANDS_SMC_SWSTATE *state) 4429 { 4430 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4431 struct si_power_info *si_pi = si_get_pi(rdev); 4432 struct si_ulv_param *ulv = &si_pi->ulv; 4433 u32 sclk_in_sr = 1350; /* ??? */ 4434 int ret; 4435 4436 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4437 &state->levels[0]); 4438 if (!ret) { 4439 if (eg_pi->sclk_deep_sleep) { 4440 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4441 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4442 else 4443 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4444 } 4445 if (ulv->one_pcie_lane_in_ulv) 4446 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4447 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4448 state->levels[0].ACIndex = 1; 4449 state->levels[0].std_vddc = state->levels[0].vddc; 4450 state->levelCount = 1; 4451 4452 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4453 } 4454 4455 return ret; 4456 } 4457 4458 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4459 { 4460 struct si_power_info *si_pi = si_get_pi(rdev); 4461 struct si_ulv_param *ulv = &si_pi->ulv; 4462 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4463 int ret; 4464 4465 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4466 &arb_regs); 4467 if (ret) 4468 return ret; 4469 4470 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4471 ulv->volt_change_delay); 4472 4473 ret = si_copy_bytes_to_smc(rdev, 4474 si_pi->arb_table_start + 4475 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4476 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4477 (u8 *)&arb_regs, 4478 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4479 si_pi->sram_end); 4480 4481 return ret; 4482 } 4483 4484 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4485 { 4486 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4487 4488 pi->mvdd_split_frequency = 30000; 4489 } 4490 4491 static int si_init_smc_table(struct radeon_device *rdev) 4492 { 4493 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4494 struct si_power_info *si_pi = si_get_pi(rdev); 4495 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4496 const struct si_ulv_param *ulv = &si_pi->ulv; 4497 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4498 int ret; 4499 u32 lane_width; 4500 u32 vr_hot_gpio; 4501 4502 si_populate_smc_voltage_tables(rdev, table); 4503 4504 switch (rdev->pm.int_thermal_type) { 4505 case THERMAL_TYPE_SI: 4506 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4507 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4508 break; 4509 case THERMAL_TYPE_NONE: 4510 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4511 break; 4512 default: 4513 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4514 break; 4515 } 4516 4517 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4518 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4519 4520 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4521 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4522 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4523 } 4524 4525 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4526 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4527 4528 if (pi->mem_gddr5) 4529 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4530 4531 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4532 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4533 4534 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4535 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4536 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4537 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4538 vr_hot_gpio); 4539 } 4540 4541 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4542 if (ret) 4543 return ret; 4544 4545 ret = si_populate_smc_acpi_state(rdev, table); 4546 if (ret) 4547 return ret; 4548 4549 table->driverState = table->initialState; 4550 4551 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4552 SISLANDS_INITIAL_STATE_ARB_INDEX); 4553 if (ret) 4554 return ret; 4555 4556 if (ulv->supported && ulv->pl.vddc) { 4557 ret = si_populate_ulv_state(rdev, &table->ULVState); 4558 if (ret) 4559 return ret; 4560 4561 ret = si_program_ulv_memory_timing_parameters(rdev); 4562 if (ret) 4563 return ret; 4564 4565 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4566 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4567 4568 lane_width = radeon_get_pcie_lanes(rdev); 4569 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4570 } else { 4571 table->ULVState = table->initialState; 4572 } 4573 4574 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4575 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4576 si_pi->sram_end); 4577 } 4578 4579 static int si_calculate_sclk_params(struct radeon_device *rdev, 4580 u32 engine_clock, 4581 SISLANDS_SMC_SCLK_VALUE *sclk) 4582 { 4583 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4584 struct si_power_info *si_pi = si_get_pi(rdev); 4585 struct atom_clock_dividers dividers; 4586 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4587 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4588 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4589 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4590 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4591 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4592 u64 tmp; 4593 u32 reference_clock = rdev->clock.spll.reference_freq; 4594 u32 reference_divider; 4595 u32 fbdiv; 4596 int ret; 4597 4598 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4599 engine_clock, false, ÷rs); 4600 if (ret) 4601 return ret; 4602 4603 reference_divider = 1 + dividers.ref_div; 4604 4605 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4606 do_div(tmp, reference_clock); 4607 fbdiv = (u32) tmp; 4608 4609 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4610 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4611 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4612 4613 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4614 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4615 4616 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4617 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4618 spll_func_cntl_3 |= SPLL_DITHEN; 4619 4620 if (pi->sclk_ss) { 4621 struct radeon_atom_ss ss; 4622 u32 vco_freq = engine_clock * dividers.post_div; 4623 4624 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4625 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4626 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4627 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4628 4629 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4630 cg_spll_spread_spectrum |= CLK_S(clk_s); 4631 cg_spll_spread_spectrum |= SSEN; 4632 4633 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4634 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4635 } 4636 } 4637 4638 sclk->sclk_value = engine_clock; 4639 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4640 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4641 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4642 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4643 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4644 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4645 4646 return 0; 4647 } 4648 4649 static int si_populate_sclk_value(struct radeon_device *rdev, 4650 u32 engine_clock, 4651 SISLANDS_SMC_SCLK_VALUE *sclk) 4652 { 4653 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4654 int ret; 4655 4656 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4657 if (!ret) { 4658 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4659 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4660 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4661 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4662 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4663 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4664 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4665 } 4666 4667 return ret; 4668 } 4669 4670 static int si_populate_mclk_value(struct radeon_device *rdev, 4671 u32 engine_clock, 4672 u32 memory_clock, 4673 SISLANDS_SMC_MCLK_VALUE *mclk, 4674 bool strobe_mode, 4675 bool dll_state_on) 4676 { 4677 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4678 struct si_power_info *si_pi = si_get_pi(rdev); 4679 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4680 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4681 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4682 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4683 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4684 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4685 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4686 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4687 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4688 struct atom_mpll_param mpll_param; 4689 int ret; 4690 4691 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4692 if (ret) 4693 return ret; 4694 4695 mpll_func_cntl &= ~BWCTRL_MASK; 4696 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4697 4698 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4699 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4700 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4701 4702 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4703 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4704 4705 if (pi->mem_gddr5) { 4706 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4707 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4708 YCLK_POST_DIV(mpll_param.post_div); 4709 } 4710 4711 if (pi->mclk_ss) { 4712 struct radeon_atom_ss ss; 4713 u32 freq_nom; 4714 u32 tmp; 4715 u32 reference_clock = rdev->clock.mpll.reference_freq; 4716 4717 if (pi->mem_gddr5) 4718 freq_nom = memory_clock * 4; 4719 else 4720 freq_nom = memory_clock * 2; 4721 4722 tmp = freq_nom / reference_clock; 4723 tmp = tmp * tmp; 4724 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4725 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4726 u32 clks = reference_clock * 5 / ss.rate; 4727 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4728 4729 mpll_ss1 &= ~CLKV_MASK; 4730 mpll_ss1 |= CLKV(clkv); 4731 4732 mpll_ss2 &= ~CLKS_MASK; 4733 mpll_ss2 |= CLKS(clks); 4734 } 4735 } 4736 4737 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4738 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4739 4740 if (dll_state_on) 4741 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4742 else 4743 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4744 4745 mclk->mclk_value = cpu_to_be32(memory_clock); 4746 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4747 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4748 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4749 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4750 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4751 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4752 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4753 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4754 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4755 4756 return 0; 4757 } 4758 4759 static void si_populate_smc_sp(struct radeon_device *rdev, 4760 struct radeon_ps *radeon_state, 4761 SISLANDS_SMC_SWSTATE *smc_state) 4762 { 4763 struct ni_ps *ps = ni_get_ps(radeon_state); 4764 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4765 int i; 4766 4767 for (i = 0; i < ps->performance_level_count - 1; i++) 4768 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4769 4770 smc_state->levels[ps->performance_level_count - 1].bSP = 4771 cpu_to_be32(pi->psp); 4772 } 4773 4774 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4775 struct rv7xx_pl *pl, 4776 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4777 { 4778 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4779 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4780 struct si_power_info *si_pi = si_get_pi(rdev); 4781 int ret; 4782 bool dll_state_on; 4783 u16 std_vddc; 4784 bool gmc_pg = false; 4785 4786 if (eg_pi->pcie_performance_request && 4787 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4788 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4789 else 4790 level->gen2PCIE = (u8)pl->pcie_gen; 4791 4792 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4793 if (ret) 4794 return ret; 4795 4796 level->mcFlags = 0; 4797 4798 if (pi->mclk_stutter_mode_threshold && 4799 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4800 !eg_pi->uvd_enabled && 4801 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4802 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4803 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4804 4805 if (gmc_pg) 4806 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4807 } 4808 4809 if (pi->mem_gddr5) { 4810 if (pl->mclk > pi->mclk_edc_enable_threshold) 4811 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4812 4813 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4814 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4815 4816 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4817 4818 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4819 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4820 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4821 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4822 else 4823 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4824 } else { 4825 dll_state_on = false; 4826 } 4827 } else { 4828 level->strobeMode = si_get_strobe_mode_settings(rdev, 4829 pl->mclk); 4830 4831 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4832 } 4833 4834 ret = si_populate_mclk_value(rdev, 4835 pl->sclk, 4836 pl->mclk, 4837 &level->mclk, 4838 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4839 if (ret) 4840 return ret; 4841 4842 ret = si_populate_voltage_value(rdev, 4843 &eg_pi->vddc_voltage_table, 4844 pl->vddc, &level->vddc); 4845 if (ret) 4846 return ret; 4847 4848 4849 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4850 if (ret) 4851 return ret; 4852 4853 ret = si_populate_std_voltage_value(rdev, std_vddc, 4854 level->vddc.index, &level->std_vddc); 4855 if (ret) 4856 return ret; 4857 4858 if (eg_pi->vddci_control) { 4859 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4860 pl->vddci, &level->vddci); 4861 if (ret) 4862 return ret; 4863 } 4864 4865 if (si_pi->vddc_phase_shed_control) { 4866 ret = si_populate_phase_shedding_value(rdev, 4867 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4868 pl->vddc, 4869 pl->sclk, 4870 pl->mclk, 4871 &level->vddc); 4872 if (ret) 4873 return ret; 4874 } 4875 4876 level->MaxPoweredUpCU = si_pi->max_cu; 4877 4878 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4879 4880 return ret; 4881 } 4882 4883 static int si_populate_smc_t(struct radeon_device *rdev, 4884 struct radeon_ps *radeon_state, 4885 SISLANDS_SMC_SWSTATE *smc_state) 4886 { 4887 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4888 struct ni_ps *state = ni_get_ps(radeon_state); 4889 u32 a_t; 4890 u32 t_l, t_h; 4891 u32 high_bsp; 4892 int i, ret; 4893 4894 if (state->performance_level_count >= 9) 4895 return -EINVAL; 4896 4897 if (state->performance_level_count < 2) { 4898 a_t = CG_R(0xffff) | CG_L(0); 4899 smc_state->levels[0].aT = cpu_to_be32(a_t); 4900 return 0; 4901 } 4902 4903 smc_state->levels[0].aT = cpu_to_be32(0); 4904 4905 for (i = 0; i <= state->performance_level_count - 2; i++) { 4906 ret = r600_calculate_at( 4907 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4908 100 * R600_AH_DFLT, 4909 state->performance_levels[i + 1].sclk, 4910 state->performance_levels[i].sclk, 4911 &t_l, 4912 &t_h); 4913 4914 if (ret) { 4915 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4916 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4917 } 4918 4919 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4920 a_t |= CG_R(t_l * pi->bsp / 20000); 4921 smc_state->levels[i].aT = cpu_to_be32(a_t); 4922 4923 high_bsp = (i == state->performance_level_count - 2) ? 4924 pi->pbsp : pi->bsp; 4925 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4926 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4927 } 4928 4929 return 0; 4930 } 4931 4932 static int si_disable_ulv(struct radeon_device *rdev) 4933 { 4934 struct si_power_info *si_pi = si_get_pi(rdev); 4935 struct si_ulv_param *ulv = &si_pi->ulv; 4936 4937 if (ulv->supported) 4938 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4939 0 : -EINVAL; 4940 4941 return 0; 4942 } 4943 4944 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4945 struct radeon_ps *radeon_state) 4946 { 4947 const struct si_power_info *si_pi = si_get_pi(rdev); 4948 const struct si_ulv_param *ulv = &si_pi->ulv; 4949 const struct ni_ps *state = ni_get_ps(radeon_state); 4950 int i; 4951 4952 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4953 return false; 4954 4955 /* XXX validate against display requirements! */ 4956 4957 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4958 if (rdev->clock.current_dispclk <= 4959 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4960 if (ulv->pl.vddc < 4961 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4962 return false; 4963 } 4964 } 4965 4966 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4967 return false; 4968 4969 return true; 4970 } 4971 4972 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4973 struct radeon_ps *radeon_new_state) 4974 { 4975 const struct si_power_info *si_pi = si_get_pi(rdev); 4976 const struct si_ulv_param *ulv = &si_pi->ulv; 4977 4978 if (ulv->supported) { 4979 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4980 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4981 0 : -EINVAL; 4982 } 4983 return 0; 4984 } 4985 4986 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4987 struct radeon_ps *radeon_state, 4988 SISLANDS_SMC_SWSTATE *smc_state) 4989 { 4990 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4991 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4992 struct si_power_info *si_pi = si_get_pi(rdev); 4993 struct ni_ps *state = ni_get_ps(radeon_state); 4994 int i, ret; 4995 u32 threshold; 4996 u32 sclk_in_sr = 1350; /* ??? */ 4997 4998 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4999 return -EINVAL; 5000 5001 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5002 5003 if (radeon_state->vclk && radeon_state->dclk) { 5004 eg_pi->uvd_enabled = true; 5005 if (eg_pi->smu_uvd_hs) 5006 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5007 } else { 5008 eg_pi->uvd_enabled = false; 5009 } 5010 5011 if (state->dc_compatible) 5012 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5013 5014 smc_state->levelCount = 0; 5015 for (i = 0; i < state->performance_level_count; i++) { 5016 if (eg_pi->sclk_deep_sleep) { 5017 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5018 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5019 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5020 else 5021 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5022 } 5023 } 5024 5025 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5026 &smc_state->levels[i]); 5027 smc_state->levels[i].arbRefreshState = 5028 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5029 5030 if (ret) 5031 return ret; 5032 5033 if (ni_pi->enable_power_containment) 5034 smc_state->levels[i].displayWatermark = 5035 (state->performance_levels[i].sclk < threshold) ? 5036 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5037 else 5038 smc_state->levels[i].displayWatermark = (i < 2) ? 5039 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5040 5041 if (eg_pi->dynamic_ac_timing) 5042 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5043 else 5044 smc_state->levels[i].ACIndex = 0; 5045 5046 smc_state->levelCount++; 5047 } 5048 5049 si_write_smc_soft_register(rdev, 5050 SI_SMC_SOFT_REGISTER_watermark_threshold, 5051 threshold / 512); 5052 5053 si_populate_smc_sp(rdev, radeon_state, smc_state); 5054 5055 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5056 if (ret) 5057 ni_pi->enable_power_containment = false; 5058 5059 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5060 if (ret) 5061 ni_pi->enable_sq_ramping = false; 5062 5063 return si_populate_smc_t(rdev, radeon_state, smc_state); 5064 } 5065 5066 static int si_upload_sw_state(struct radeon_device *rdev, 5067 struct radeon_ps *radeon_new_state) 5068 { 5069 struct si_power_info *si_pi = si_get_pi(rdev); 5070 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5071 int ret; 5072 u32 address = si_pi->state_table_start + 5073 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5074 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5075 ((new_state->performance_level_count - 1) * 5076 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5077 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5078 5079 memset(smc_state, 0, state_size); 5080 5081 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5082 if (ret) 5083 return ret; 5084 5085 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5086 state_size, si_pi->sram_end); 5087 5088 return ret; 5089 } 5090 5091 static int si_upload_ulv_state(struct radeon_device *rdev) 5092 { 5093 struct si_power_info *si_pi = si_get_pi(rdev); 5094 struct si_ulv_param *ulv = &si_pi->ulv; 5095 int ret = 0; 5096 5097 if (ulv->supported && ulv->pl.vddc) { 5098 u32 address = si_pi->state_table_start + 5099 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5100 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5101 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5102 5103 memset(smc_state, 0, state_size); 5104 5105 ret = si_populate_ulv_state(rdev, smc_state); 5106 if (!ret) 5107 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5108 state_size, si_pi->sram_end); 5109 } 5110 5111 return ret; 5112 } 5113 5114 static int si_upload_smc_data(struct radeon_device *rdev) 5115 { 5116 struct radeon_crtc *radeon_crtc = NULL; 5117 int i; 5118 5119 if (rdev->pm.dpm.new_active_crtc_count == 0) 5120 return 0; 5121 5122 for (i = 0; i < rdev->num_crtc; i++) { 5123 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5124 radeon_crtc = rdev->mode_info.crtcs[i]; 5125 break; 5126 } 5127 } 5128 5129 if (radeon_crtc == NULL) 5130 return 0; 5131 5132 if (radeon_crtc->line_time <= 0) 5133 return 0; 5134 5135 if (si_write_smc_soft_register(rdev, 5136 SI_SMC_SOFT_REGISTER_crtc_index, 5137 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5138 return 0; 5139 5140 if (si_write_smc_soft_register(rdev, 5141 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5142 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5143 return 0; 5144 5145 if (si_write_smc_soft_register(rdev, 5146 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5147 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5148 return 0; 5149 5150 return 0; 5151 } 5152 5153 static int si_set_mc_special_registers(struct radeon_device *rdev, 5154 struct si_mc_reg_table *table) 5155 { 5156 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5157 u8 i, j, k; 5158 u32 temp_reg; 5159 5160 for (i = 0, j = table->last; i < table->last; i++) { 5161 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5162 return -EINVAL; 5163 switch (table->mc_reg_address[i].s1 << 2) { 5164 case MC_SEQ_MISC1: 5165 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5166 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5167 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5168 for (k = 0; k < table->num_entries; k++) 5169 table->mc_reg_table_entry[k].mc_data[j] = 5170 ((temp_reg & 0xffff0000)) | 5171 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5172 j++; 5173 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5174 return -EINVAL; 5175 5176 temp_reg = RREG32(MC_PMG_CMD_MRS); 5177 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5178 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5179 for (k = 0; k < table->num_entries; k++) { 5180 table->mc_reg_table_entry[k].mc_data[j] = 5181 (temp_reg & 0xffff0000) | 5182 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5183 if (!pi->mem_gddr5) 5184 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5185 } 5186 j++; 5187 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5188 return -EINVAL; 5189 5190 if (!pi->mem_gddr5) { 5191 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5192 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5193 for (k = 0; k < table->num_entries; k++) 5194 table->mc_reg_table_entry[k].mc_data[j] = 5195 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5196 j++; 5197 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5198 return -EINVAL; 5199 } 5200 break; 5201 case MC_SEQ_RESERVE_M: 5202 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5203 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5204 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5205 for(k = 0; k < table->num_entries; k++) 5206 table->mc_reg_table_entry[k].mc_data[j] = 5207 (temp_reg & 0xffff0000) | 5208 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5209 j++; 5210 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5211 return -EINVAL; 5212 break; 5213 default: 5214 break; 5215 } 5216 } 5217 5218 table->last = j; 5219 5220 return 0; 5221 } 5222 5223 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5224 { 5225 bool result = true; 5226 5227 switch (in_reg) { 5228 case MC_SEQ_RAS_TIMING >> 2: 5229 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5230 break; 5231 case MC_SEQ_CAS_TIMING >> 2: 5232 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5233 break; 5234 case MC_SEQ_MISC_TIMING >> 2: 5235 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5236 break; 5237 case MC_SEQ_MISC_TIMING2 >> 2: 5238 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5239 break; 5240 case MC_SEQ_RD_CTL_D0 >> 2: 5241 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5242 break; 5243 case MC_SEQ_RD_CTL_D1 >> 2: 5244 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5245 break; 5246 case MC_SEQ_WR_CTL_D0 >> 2: 5247 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5248 break; 5249 case MC_SEQ_WR_CTL_D1 >> 2: 5250 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5251 break; 5252 case MC_PMG_CMD_EMRS >> 2: 5253 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5254 break; 5255 case MC_PMG_CMD_MRS >> 2: 5256 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5257 break; 5258 case MC_PMG_CMD_MRS1 >> 2: 5259 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5260 break; 5261 case MC_SEQ_PMG_TIMING >> 2: 5262 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5263 break; 5264 case MC_PMG_CMD_MRS2 >> 2: 5265 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5266 break; 5267 case MC_SEQ_WR_CTL_2 >> 2: 5268 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5269 break; 5270 default: 5271 result = false; 5272 break; 5273 } 5274 5275 return result; 5276 } 5277 5278 static void si_set_valid_flag(struct si_mc_reg_table *table) 5279 { 5280 u8 i, j; 5281 5282 for (i = 0; i < table->last; i++) { 5283 for (j = 1; j < table->num_entries; j++) { 5284 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5285 table->valid_flag |= 1 << i; 5286 break; 5287 } 5288 } 5289 } 5290 } 5291 5292 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5293 { 5294 u32 i; 5295 u16 address; 5296 5297 for (i = 0; i < table->last; i++) 5298 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5299 address : table->mc_reg_address[i].s1; 5300 5301 } 5302 5303 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5304 struct si_mc_reg_table *si_table) 5305 { 5306 u8 i, j; 5307 5308 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5309 return -EINVAL; 5310 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5311 return -EINVAL; 5312 5313 for (i = 0; i < table->last; i++) 5314 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5315 si_table->last = table->last; 5316 5317 for (i = 0; i < table->num_entries; i++) { 5318 si_table->mc_reg_table_entry[i].mclk_max = 5319 table->mc_reg_table_entry[i].mclk_max; 5320 for (j = 0; j < table->last; j++) { 5321 si_table->mc_reg_table_entry[i].mc_data[j] = 5322 table->mc_reg_table_entry[i].mc_data[j]; 5323 } 5324 } 5325 si_table->num_entries = table->num_entries; 5326 5327 return 0; 5328 } 5329 5330 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5331 { 5332 struct si_power_info *si_pi = si_get_pi(rdev); 5333 struct atom_mc_reg_table *table; 5334 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5335 u8 module_index = rv770_get_memory_module_index(rdev); 5336 int ret; 5337 5338 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5339 if (!table) 5340 return -ENOMEM; 5341 5342 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5343 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5344 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5345 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5346 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5347 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5348 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5349 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5350 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5351 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5352 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5353 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5354 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5355 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5356 5357 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5358 if (ret) 5359 goto init_mc_done; 5360 5361 ret = si_copy_vbios_mc_reg_table(table, si_table); 5362 if (ret) 5363 goto init_mc_done; 5364 5365 si_set_s0_mc_reg_index(si_table); 5366 5367 ret = si_set_mc_special_registers(rdev, si_table); 5368 if (ret) 5369 goto init_mc_done; 5370 5371 si_set_valid_flag(si_table); 5372 5373 init_mc_done: 5374 kfree(table); 5375 5376 return ret; 5377 5378 } 5379 5380 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5381 SMC_SIslands_MCRegisters *mc_reg_table) 5382 { 5383 struct si_power_info *si_pi = si_get_pi(rdev); 5384 u32 i, j; 5385 5386 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5387 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5388 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5389 break; 5390 mc_reg_table->address[i].s0 = 5391 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5392 mc_reg_table->address[i].s1 = 5393 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5394 i++; 5395 } 5396 } 5397 mc_reg_table->last = (u8)i; 5398 } 5399 5400 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5401 SMC_SIslands_MCRegisterSet *data, 5402 u32 num_entries, u32 valid_flag) 5403 { 5404 u32 i, j; 5405 5406 for(i = 0, j = 0; j < num_entries; j++) { 5407 if (valid_flag & (1 << j)) { 5408 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5409 i++; 5410 } 5411 } 5412 } 5413 5414 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5415 struct rv7xx_pl *pl, 5416 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5417 { 5418 struct si_power_info *si_pi = si_get_pi(rdev); 5419 u32 i = 0; 5420 5421 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5422 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5423 break; 5424 } 5425 5426 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5427 --i; 5428 5429 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5430 mc_reg_table_data, si_pi->mc_reg_table.last, 5431 si_pi->mc_reg_table.valid_flag); 5432 } 5433 5434 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5435 struct radeon_ps *radeon_state, 5436 SMC_SIslands_MCRegisters *mc_reg_table) 5437 { 5438 struct ni_ps *state = ni_get_ps(radeon_state); 5439 int i; 5440 5441 for (i = 0; i < state->performance_level_count; i++) { 5442 si_convert_mc_reg_table_entry_to_smc(rdev, 5443 &state->performance_levels[i], 5444 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5445 } 5446 } 5447 5448 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5449 struct radeon_ps *radeon_boot_state) 5450 { 5451 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5452 struct si_power_info *si_pi = si_get_pi(rdev); 5453 struct si_ulv_param *ulv = &si_pi->ulv; 5454 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5455 5456 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5457 5458 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5459 5460 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5461 5462 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5463 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5464 5465 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5466 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5467 si_pi->mc_reg_table.last, 5468 si_pi->mc_reg_table.valid_flag); 5469 5470 if (ulv->supported && ulv->pl.vddc != 0) 5471 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5472 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5473 else 5474 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5475 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5476 si_pi->mc_reg_table.last, 5477 si_pi->mc_reg_table.valid_flag); 5478 5479 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5480 5481 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5482 (u8 *)smc_mc_reg_table, 5483 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5484 } 5485 5486 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5487 struct radeon_ps *radeon_new_state) 5488 { 5489 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5490 struct si_power_info *si_pi = si_get_pi(rdev); 5491 u32 address = si_pi->mc_reg_table_start + 5492 offsetof(SMC_SIslands_MCRegisters, 5493 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5494 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5495 5496 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5497 5498 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5499 5500 5501 return si_copy_bytes_to_smc(rdev, address, 5502 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5503 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5504 si_pi->sram_end); 5505 5506 } 5507 5508 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5509 { 5510 if (enable) 5511 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5512 else 5513 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5514 } 5515 5516 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5517 struct radeon_ps *radeon_state) 5518 { 5519 struct ni_ps *state = ni_get_ps(radeon_state); 5520 int i; 5521 u16 pcie_speed, max_speed = 0; 5522 5523 for (i = 0; i < state->performance_level_count; i++) { 5524 pcie_speed = state->performance_levels[i].pcie_gen; 5525 if (max_speed < pcie_speed) 5526 max_speed = pcie_speed; 5527 } 5528 return max_speed; 5529 } 5530 5531 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5532 { 5533 u32 speed_cntl; 5534 5535 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5536 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5537 5538 return (u16)speed_cntl; 5539 } 5540 5541 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5542 struct radeon_ps *radeon_new_state, 5543 struct radeon_ps *radeon_current_state) 5544 { 5545 struct si_power_info *si_pi = si_get_pi(rdev); 5546 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5547 enum radeon_pcie_gen current_link_speed; 5548 5549 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5550 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5551 else 5552 current_link_speed = si_pi->force_pcie_gen; 5553 5554 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5555 si_pi->pspp_notify_required = false; 5556 if (target_link_speed > current_link_speed) { 5557 switch (target_link_speed) { 5558 #if defined(CONFIG_ACPI) 5559 case RADEON_PCIE_GEN3: 5560 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5561 break; 5562 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5563 if (current_link_speed == RADEON_PCIE_GEN2) 5564 break; 5565 case RADEON_PCIE_GEN2: 5566 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5567 break; 5568 #endif 5569 default: 5570 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5571 break; 5572 } 5573 } else { 5574 if (target_link_speed < current_link_speed) 5575 si_pi->pspp_notify_required = true; 5576 } 5577 } 5578 5579 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5580 struct radeon_ps *radeon_new_state, 5581 struct radeon_ps *radeon_current_state) 5582 { 5583 struct si_power_info *si_pi = si_get_pi(rdev); 5584 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5585 u8 request; 5586 5587 if (si_pi->pspp_notify_required) { 5588 if (target_link_speed == RADEON_PCIE_GEN3) 5589 request = PCIE_PERF_REQ_PECI_GEN3; 5590 else if (target_link_speed == RADEON_PCIE_GEN2) 5591 request = PCIE_PERF_REQ_PECI_GEN2; 5592 else 5593 request = PCIE_PERF_REQ_PECI_GEN1; 5594 5595 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5596 (si_get_current_pcie_speed(rdev) > 0)) 5597 return; 5598 5599 #if defined(CONFIG_ACPI) 5600 radeon_acpi_pcie_performance_request(rdev, request, false); 5601 #endif 5602 } 5603 } 5604 5605 #if 0 5606 static int si_ds_request(struct radeon_device *rdev, 5607 bool ds_status_on, u32 count_write) 5608 { 5609 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5610 5611 if (eg_pi->sclk_deep_sleep) { 5612 if (ds_status_on) 5613 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5614 PPSMC_Result_OK) ? 5615 0 : -EINVAL; 5616 else 5617 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5618 PPSMC_Result_OK) ? 0 : -EINVAL; 5619 } 5620 return 0; 5621 } 5622 #endif 5623 5624 static void si_set_max_cu_value(struct radeon_device *rdev) 5625 { 5626 struct si_power_info *si_pi = si_get_pi(rdev); 5627 5628 if (rdev->family == CHIP_VERDE) { 5629 switch (rdev->pdev->device) { 5630 case 0x6820: 5631 case 0x6825: 5632 case 0x6821: 5633 case 0x6823: 5634 case 0x6827: 5635 si_pi->max_cu = 10; 5636 break; 5637 case 0x682D: 5638 case 0x6824: 5639 case 0x682F: 5640 case 0x6826: 5641 si_pi->max_cu = 8; 5642 break; 5643 case 0x6828: 5644 case 0x6830: 5645 case 0x6831: 5646 case 0x6838: 5647 case 0x6839: 5648 case 0x683D: 5649 si_pi->max_cu = 10; 5650 break; 5651 case 0x683B: 5652 case 0x683F: 5653 case 0x6829: 5654 si_pi->max_cu = 8; 5655 break; 5656 default: 5657 si_pi->max_cu = 0; 5658 break; 5659 } 5660 } else { 5661 si_pi->max_cu = 0; 5662 } 5663 } 5664 5665 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5666 struct radeon_clock_voltage_dependency_table *table) 5667 { 5668 u32 i; 5669 int j; 5670 u16 leakage_voltage; 5671 5672 if (table) { 5673 for (i = 0; i < table->count; i++) { 5674 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5675 table->entries[i].v, 5676 &leakage_voltage)) { 5677 case 0: 5678 table->entries[i].v = leakage_voltage; 5679 break; 5680 case -EAGAIN: 5681 return -EINVAL; 5682 case -EINVAL: 5683 default: 5684 break; 5685 } 5686 } 5687 5688 for (j = (table->count - 2); j >= 0; j--) { 5689 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5690 table->entries[j].v : table->entries[j + 1].v; 5691 } 5692 } 5693 return 0; 5694 } 5695 5696 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5697 { 5698 int ret = 0; 5699 5700 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5701 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5702 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5703 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5704 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5705 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5706 return ret; 5707 } 5708 5709 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5710 struct radeon_ps *radeon_new_state, 5711 struct radeon_ps *radeon_current_state) 5712 { 5713 u32 lane_width; 5714 u32 new_lane_width = 5715 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5716 u32 current_lane_width = 5717 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5718 5719 if (new_lane_width != current_lane_width) { 5720 radeon_set_pcie_lanes(rdev, new_lane_width); 5721 lane_width = radeon_get_pcie_lanes(rdev); 5722 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5723 } 5724 } 5725 5726 void si_dpm_setup_asic(struct radeon_device *rdev) 5727 { 5728 rv770_get_memory_type(rdev); 5729 si_read_clock_registers(rdev); 5730 si_enable_acpi_power_management(rdev); 5731 } 5732 5733 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5734 int min_temp, int max_temp) 5735 { 5736 int low_temp = 0 * 1000; 5737 int high_temp = 255 * 1000; 5738 5739 if (low_temp < min_temp) 5740 low_temp = min_temp; 5741 if (high_temp > max_temp) 5742 high_temp = max_temp; 5743 if (high_temp < low_temp) { 5744 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5745 return -EINVAL; 5746 } 5747 5748 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5749 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5750 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5751 5752 rdev->pm.dpm.thermal.min_temp = low_temp; 5753 rdev->pm.dpm.thermal.max_temp = high_temp; 5754 5755 return 0; 5756 } 5757 5758 int si_dpm_enable(struct radeon_device *rdev) 5759 { 5760 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5761 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5762 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5763 int ret; 5764 5765 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 5766 RADEON_CG_BLOCK_MC | 5767 RADEON_CG_BLOCK_SDMA | 5768 RADEON_CG_BLOCK_BIF | 5769 RADEON_CG_BLOCK_UVD | 5770 RADEON_CG_BLOCK_HDP), false); 5771 5772 if (si_is_smc_running(rdev)) 5773 return -EINVAL; 5774 if (pi->voltage_control) 5775 si_enable_voltage_control(rdev, true); 5776 if (pi->mvdd_control) 5777 si_get_mvdd_configuration(rdev); 5778 if (pi->voltage_control) { 5779 ret = si_construct_voltage_tables(rdev); 5780 if (ret) { 5781 DRM_ERROR("si_construct_voltage_tables failed\n"); 5782 return ret; 5783 } 5784 } 5785 if (eg_pi->dynamic_ac_timing) { 5786 ret = si_initialize_mc_reg_table(rdev); 5787 if (ret) 5788 eg_pi->dynamic_ac_timing = false; 5789 } 5790 if (pi->dynamic_ss) 5791 si_enable_spread_spectrum(rdev, true); 5792 if (pi->thermal_protection) 5793 si_enable_thermal_protection(rdev, true); 5794 si_setup_bsp(rdev); 5795 si_program_git(rdev); 5796 si_program_tp(rdev); 5797 si_program_tpp(rdev); 5798 si_program_sstp(rdev); 5799 si_enable_display_gap(rdev); 5800 si_program_vc(rdev); 5801 ret = si_upload_firmware(rdev); 5802 if (ret) { 5803 DRM_ERROR("si_upload_firmware failed\n"); 5804 return ret; 5805 } 5806 ret = si_process_firmware_header(rdev); 5807 if (ret) { 5808 DRM_ERROR("si_process_firmware_header failed\n"); 5809 return ret; 5810 } 5811 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5812 if (ret) { 5813 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5814 return ret; 5815 } 5816 ret = si_init_smc_table(rdev); 5817 if (ret) { 5818 DRM_ERROR("si_init_smc_table failed\n"); 5819 return ret; 5820 } 5821 ret = si_init_smc_spll_table(rdev); 5822 if (ret) { 5823 DRM_ERROR("si_init_smc_spll_table failed\n"); 5824 return ret; 5825 } 5826 ret = si_init_arb_table_index(rdev); 5827 if (ret) { 5828 DRM_ERROR("si_init_arb_table_index failed\n"); 5829 return ret; 5830 } 5831 if (eg_pi->dynamic_ac_timing) { 5832 ret = si_populate_mc_reg_table(rdev, boot_ps); 5833 if (ret) { 5834 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5835 return ret; 5836 } 5837 } 5838 ret = si_initialize_smc_cac_tables(rdev); 5839 if (ret) { 5840 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5841 return ret; 5842 } 5843 ret = si_initialize_hardware_cac_manager(rdev); 5844 if (ret) { 5845 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5846 return ret; 5847 } 5848 ret = si_initialize_smc_dte_tables(rdev); 5849 if (ret) { 5850 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5851 return ret; 5852 } 5853 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5854 if (ret) { 5855 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5856 return ret; 5857 } 5858 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5859 if (ret) { 5860 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5861 return ret; 5862 } 5863 si_program_response_times(rdev); 5864 si_program_ds_registers(rdev); 5865 si_dpm_start_smc(rdev); 5866 ret = si_notify_smc_display_change(rdev, false); 5867 if (ret) { 5868 DRM_ERROR("si_notify_smc_display_change failed\n"); 5869 return ret; 5870 } 5871 si_enable_sclk_control(rdev, true); 5872 si_start_dpm(rdev); 5873 5874 if (rdev->irq.installed && 5875 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5876 PPSMC_Result result; 5877 5878 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5879 if (ret) 5880 return ret; 5881 rdev->irq.dpm_thermal = true; 5882 radeon_irq_set(rdev); 5883 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5884 5885 if (result != PPSMC_Result_OK) 5886 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5887 } 5888 5889 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5890 5891 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 5892 RADEON_CG_BLOCK_MC | 5893 RADEON_CG_BLOCK_SDMA | 5894 RADEON_CG_BLOCK_BIF | 5895 RADEON_CG_BLOCK_UVD | 5896 RADEON_CG_BLOCK_HDP), true); 5897 5898 ni_update_current_ps(rdev, boot_ps); 5899 5900 return 0; 5901 } 5902 5903 void si_dpm_disable(struct radeon_device *rdev) 5904 { 5905 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5906 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5907 5908 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 5909 RADEON_CG_BLOCK_MC | 5910 RADEON_CG_BLOCK_SDMA | 5911 RADEON_CG_BLOCK_BIF | 5912 RADEON_CG_BLOCK_UVD | 5913 RADEON_CG_BLOCK_HDP), false); 5914 5915 if (!si_is_smc_running(rdev)) 5916 return; 5917 si_disable_ulv(rdev); 5918 si_clear_vc(rdev); 5919 if (pi->thermal_protection) 5920 si_enable_thermal_protection(rdev, false); 5921 si_enable_power_containment(rdev, boot_ps, false); 5922 si_enable_smc_cac(rdev, boot_ps, false); 5923 si_enable_spread_spectrum(rdev, false); 5924 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5925 si_stop_dpm(rdev); 5926 si_reset_to_default(rdev); 5927 si_dpm_stop_smc(rdev); 5928 si_force_switch_to_arb_f0(rdev); 5929 5930 ni_update_current_ps(rdev, boot_ps); 5931 } 5932 5933 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5934 { 5935 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5936 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5937 struct radeon_ps *new_ps = &requested_ps; 5938 5939 ni_update_requested_ps(rdev, new_ps); 5940 5941 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5942 5943 return 0; 5944 } 5945 5946 static int si_power_control_set_level(struct radeon_device *rdev) 5947 { 5948 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5949 int ret; 5950 5951 ret = si_restrict_performance_levels_before_switch(rdev); 5952 if (ret) 5953 return ret; 5954 ret = si_halt_smc(rdev); 5955 if (ret) 5956 return ret; 5957 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5958 if (ret) 5959 return ret; 5960 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5961 if (ret) 5962 return ret; 5963 ret = si_resume_smc(rdev); 5964 if (ret) 5965 return ret; 5966 ret = si_set_sw_state(rdev); 5967 if (ret) 5968 return ret; 5969 return 0; 5970 } 5971 5972 int si_dpm_set_power_state(struct radeon_device *rdev) 5973 { 5974 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5975 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5976 struct radeon_ps *old_ps = &eg_pi->current_rps; 5977 int ret; 5978 5979 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 5980 RADEON_CG_BLOCK_MC | 5981 RADEON_CG_BLOCK_SDMA | 5982 RADEON_CG_BLOCK_BIF | 5983 RADEON_CG_BLOCK_UVD | 5984 RADEON_CG_BLOCK_HDP), false); 5985 5986 ret = si_disable_ulv(rdev); 5987 if (ret) { 5988 DRM_ERROR("si_disable_ulv failed\n"); 5989 return ret; 5990 } 5991 ret = si_restrict_performance_levels_before_switch(rdev); 5992 if (ret) { 5993 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5994 return ret; 5995 } 5996 if (eg_pi->pcie_performance_request) 5997 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5998 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5999 ret = si_enable_power_containment(rdev, new_ps, false); 6000 if (ret) { 6001 DRM_ERROR("si_enable_power_containment failed\n"); 6002 return ret; 6003 } 6004 ret = si_enable_smc_cac(rdev, new_ps, false); 6005 if (ret) { 6006 DRM_ERROR("si_enable_smc_cac failed\n"); 6007 return ret; 6008 } 6009 ret = si_halt_smc(rdev); 6010 if (ret) { 6011 DRM_ERROR("si_halt_smc failed\n"); 6012 return ret; 6013 } 6014 ret = si_upload_sw_state(rdev, new_ps); 6015 if (ret) { 6016 DRM_ERROR("si_upload_sw_state failed\n"); 6017 return ret; 6018 } 6019 ret = si_upload_smc_data(rdev); 6020 if (ret) { 6021 DRM_ERROR("si_upload_smc_data failed\n"); 6022 return ret; 6023 } 6024 ret = si_upload_ulv_state(rdev); 6025 if (ret) { 6026 DRM_ERROR("si_upload_ulv_state failed\n"); 6027 return ret; 6028 } 6029 if (eg_pi->dynamic_ac_timing) { 6030 ret = si_upload_mc_reg_table(rdev, new_ps); 6031 if (ret) { 6032 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6033 return ret; 6034 } 6035 } 6036 ret = si_program_memory_timing_parameters(rdev, new_ps); 6037 if (ret) { 6038 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6039 return ret; 6040 } 6041 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6042 6043 ret = si_resume_smc(rdev); 6044 if (ret) { 6045 DRM_ERROR("si_resume_smc failed\n"); 6046 return ret; 6047 } 6048 ret = si_set_sw_state(rdev); 6049 if (ret) { 6050 DRM_ERROR("si_set_sw_state failed\n"); 6051 return ret; 6052 } 6053 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6054 if (eg_pi->pcie_performance_request) 6055 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6056 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6057 if (ret) { 6058 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6059 return ret; 6060 } 6061 ret = si_enable_smc_cac(rdev, new_ps, true); 6062 if (ret) { 6063 DRM_ERROR("si_enable_smc_cac failed\n"); 6064 return ret; 6065 } 6066 ret = si_enable_power_containment(rdev, new_ps, true); 6067 if (ret) { 6068 DRM_ERROR("si_enable_power_containment failed\n"); 6069 return ret; 6070 } 6071 6072 ret = si_power_control_set_level(rdev); 6073 if (ret) { 6074 DRM_ERROR("si_power_control_set_level failed\n"); 6075 return ret; 6076 } 6077 6078 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX | 6079 RADEON_CG_BLOCK_MC | 6080 RADEON_CG_BLOCK_SDMA | 6081 RADEON_CG_BLOCK_BIF | 6082 RADEON_CG_BLOCK_UVD | 6083 RADEON_CG_BLOCK_HDP), true); 6084 6085 return 0; 6086 } 6087 6088 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6089 { 6090 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6091 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6092 6093 ni_update_current_ps(rdev, new_ps); 6094 } 6095 6096 6097 void si_dpm_reset_asic(struct radeon_device *rdev) 6098 { 6099 si_restrict_performance_levels_before_switch(rdev); 6100 si_disable_ulv(rdev); 6101 si_set_boot_state(rdev); 6102 } 6103 6104 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6105 { 6106 si_program_display_gap(rdev); 6107 } 6108 6109 union power_info { 6110 struct _ATOM_POWERPLAY_INFO info; 6111 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6112 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6113 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6114 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6115 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6116 }; 6117 6118 union pplib_clock_info { 6119 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6120 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6121 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6122 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6123 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6124 }; 6125 6126 union pplib_power_state { 6127 struct _ATOM_PPLIB_STATE v1; 6128 struct _ATOM_PPLIB_STATE_V2 v2; 6129 }; 6130 6131 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6132 struct radeon_ps *rps, 6133 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6134 u8 table_rev) 6135 { 6136 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6137 rps->class = le16_to_cpu(non_clock_info->usClassification); 6138 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6139 6140 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6141 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6142 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6143 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6144 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6145 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6146 } else { 6147 rps->vclk = 0; 6148 rps->dclk = 0; 6149 } 6150 6151 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6152 rdev->pm.dpm.boot_ps = rps; 6153 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6154 rdev->pm.dpm.uvd_ps = rps; 6155 } 6156 6157 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6158 struct radeon_ps *rps, int index, 6159 union pplib_clock_info *clock_info) 6160 { 6161 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6162 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6163 struct si_power_info *si_pi = si_get_pi(rdev); 6164 struct ni_ps *ps = ni_get_ps(rps); 6165 u16 leakage_voltage; 6166 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6167 int ret; 6168 6169 ps->performance_level_count = index + 1; 6170 6171 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6172 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6173 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6174 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6175 6176 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6177 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6178 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6179 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6180 si_pi->sys_pcie_mask, 6181 si_pi->boot_pcie_gen, 6182 clock_info->si.ucPCIEGen); 6183 6184 /* patch up vddc if necessary */ 6185 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6186 &leakage_voltage); 6187 if (ret == 0) 6188 pl->vddc = leakage_voltage; 6189 6190 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6191 pi->acpi_vddc = pl->vddc; 6192 eg_pi->acpi_vddci = pl->vddci; 6193 si_pi->acpi_pcie_gen = pl->pcie_gen; 6194 } 6195 6196 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6197 index == 0) { 6198 /* XXX disable for A0 tahiti */ 6199 si_pi->ulv.supported = true; 6200 si_pi->ulv.pl = *pl; 6201 si_pi->ulv.one_pcie_lane_in_ulv = false; 6202 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6203 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6204 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6205 } 6206 6207 if (pi->min_vddc_in_table > pl->vddc) 6208 pi->min_vddc_in_table = pl->vddc; 6209 6210 if (pi->max_vddc_in_table < pl->vddc) 6211 pi->max_vddc_in_table = pl->vddc; 6212 6213 /* patch up boot state */ 6214 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6215 u16 vddc, vddci, mvdd; 6216 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6217 pl->mclk = rdev->clock.default_mclk; 6218 pl->sclk = rdev->clock.default_sclk; 6219 pl->vddc = vddc; 6220 pl->vddci = vddci; 6221 si_pi->mvdd_bootup_value = mvdd; 6222 } 6223 6224 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6225 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6226 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6227 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6228 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6229 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6230 } 6231 } 6232 6233 static int si_parse_power_table(struct radeon_device *rdev) 6234 { 6235 struct radeon_mode_info *mode_info = &rdev->mode_info; 6236 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6237 union pplib_power_state *power_state; 6238 int i, j, k, non_clock_array_index, clock_array_index; 6239 union pplib_clock_info *clock_info; 6240 struct _StateArray *state_array; 6241 struct _ClockInfoArray *clock_info_array; 6242 struct _NonClockInfoArray *non_clock_info_array; 6243 union power_info *power_info; 6244 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6245 u16 data_offset; 6246 u8 frev, crev; 6247 u8 *power_state_offset; 6248 struct ni_ps *ps; 6249 6250 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6251 &frev, &crev, &data_offset)) 6252 return -EINVAL; 6253 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6254 6255 state_array = (struct _StateArray *) 6256 (mode_info->atom_context->bios + data_offset + 6257 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6258 clock_info_array = (struct _ClockInfoArray *) 6259 (mode_info->atom_context->bios + data_offset + 6260 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6261 non_clock_info_array = (struct _NonClockInfoArray *) 6262 (mode_info->atom_context->bios + data_offset + 6263 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6264 6265 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6266 state_array->ucNumEntries, GFP_KERNEL); 6267 if (!rdev->pm.dpm.ps) 6268 return -ENOMEM; 6269 power_state_offset = (u8 *)state_array->states; 6270 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6271 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6272 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6273 for (i = 0; i < state_array->ucNumEntries; i++) { 6274 u8 *idx; 6275 power_state = (union pplib_power_state *)power_state_offset; 6276 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6277 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6278 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6279 if (!rdev->pm.power_state[i].clock_info) 6280 return -EINVAL; 6281 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6282 if (ps == NULL) { 6283 kfree(rdev->pm.dpm.ps); 6284 return -ENOMEM; 6285 } 6286 rdev->pm.dpm.ps[i].ps_priv = ps; 6287 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6288 non_clock_info, 6289 non_clock_info_array->ucEntrySize); 6290 k = 0; 6291 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6292 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6293 clock_array_index = idx[j]; 6294 if (clock_array_index >= clock_info_array->ucNumEntries) 6295 continue; 6296 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6297 break; 6298 clock_info = (union pplib_clock_info *) 6299 ((u8 *)&clock_info_array->clockInfo[0] + 6300 (clock_array_index * clock_info_array->ucEntrySize)); 6301 si_parse_pplib_clock_info(rdev, 6302 &rdev->pm.dpm.ps[i], k, 6303 clock_info); 6304 k++; 6305 } 6306 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6307 } 6308 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6309 return 0; 6310 } 6311 6312 int si_dpm_init(struct radeon_device *rdev) 6313 { 6314 struct rv7xx_power_info *pi; 6315 struct evergreen_power_info *eg_pi; 6316 struct ni_power_info *ni_pi; 6317 struct si_power_info *si_pi; 6318 struct atom_clock_dividers dividers; 6319 int ret; 6320 u32 mask; 6321 6322 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6323 if (si_pi == NULL) 6324 return -ENOMEM; 6325 rdev->pm.dpm.priv = si_pi; 6326 ni_pi = &si_pi->ni; 6327 eg_pi = &ni_pi->eg; 6328 pi = &eg_pi->rv7xx; 6329 6330 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6331 if (ret) 6332 si_pi->sys_pcie_mask = 0; 6333 else 6334 si_pi->sys_pcie_mask = mask; 6335 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6336 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6337 6338 si_set_max_cu_value(rdev); 6339 6340 rv770_get_max_vddc(rdev); 6341 si_get_leakage_vddc(rdev); 6342 si_patch_dependency_tables_based_on_leakage(rdev); 6343 6344 pi->acpi_vddc = 0; 6345 eg_pi->acpi_vddci = 0; 6346 pi->min_vddc_in_table = 0; 6347 pi->max_vddc_in_table = 0; 6348 6349 ret = si_parse_power_table(rdev); 6350 if (ret) 6351 return ret; 6352 ret = r600_parse_extended_power_table(rdev); 6353 if (ret) 6354 return ret; 6355 6356 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6357 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6358 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6359 r600_free_extended_power_table(rdev); 6360 return -ENOMEM; 6361 } 6362 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6363 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6364 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6365 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6366 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6367 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6368 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6369 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6370 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6371 6372 if (rdev->pm.dpm.voltage_response_time == 0) 6373 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6374 if (rdev->pm.dpm.backbias_response_time == 0) 6375 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6376 6377 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6378 0, false, ÷rs); 6379 if (ret) 6380 pi->ref_div = dividers.ref_div + 1; 6381 else 6382 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6383 6384 eg_pi->smu_uvd_hs = false; 6385 6386 pi->mclk_strobe_mode_threshold = 40000; 6387 if (si_is_special_1gb_platform(rdev)) 6388 pi->mclk_stutter_mode_threshold = 0; 6389 else 6390 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6391 pi->mclk_edc_enable_threshold = 40000; 6392 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6393 6394 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6395 6396 pi->voltage_control = 6397 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6398 6399 pi->mvdd_control = 6400 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6401 6402 eg_pi->vddci_control = 6403 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6404 6405 si_pi->vddc_phase_shed_control = 6406 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6407 6408 rv770_get_engine_memory_ss(rdev); 6409 6410 pi->asi = RV770_ASI_DFLT; 6411 pi->pasi = CYPRESS_HASI_DFLT; 6412 pi->vrc = SISLANDS_VRC_DFLT; 6413 6414 pi->gfx_clock_gating = true; 6415 6416 eg_pi->sclk_deep_sleep = true; 6417 si_pi->sclk_deep_sleep_above_low = false; 6418 6419 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6420 pi->thermal_protection = true; 6421 else 6422 pi->thermal_protection = false; 6423 6424 eg_pi->dynamic_ac_timing = true; 6425 6426 eg_pi->light_sleep = true; 6427 #if defined(CONFIG_ACPI) 6428 eg_pi->pcie_performance_request = 6429 radeon_acpi_is_pcie_performance_request_supported(rdev); 6430 #else 6431 eg_pi->pcie_performance_request = false; 6432 #endif 6433 6434 si_pi->sram_end = SMC_RAM_END; 6435 6436 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6437 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6438 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6439 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6440 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6441 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6442 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6443 6444 si_initialize_powertune_defaults(rdev); 6445 6446 /* make sure dc limits are valid */ 6447 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6448 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6449 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6450 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6451 6452 return 0; 6453 } 6454 6455 void si_dpm_fini(struct radeon_device *rdev) 6456 { 6457 int i; 6458 6459 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6460 kfree(rdev->pm.dpm.ps[i].ps_priv); 6461 } 6462 kfree(rdev->pm.dpm.ps); 6463 kfree(rdev->pm.dpm.priv); 6464 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6465 r600_free_extended_power_table(rdev); 6466 } 6467 6468 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6469 struct seq_file *m) 6470 { 6471 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6472 struct ni_ps *ps = ni_get_ps(rps); 6473 struct rv7xx_pl *pl; 6474 u32 current_index = 6475 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6476 CURRENT_STATE_INDEX_SHIFT; 6477 6478 if (current_index >= ps->performance_level_count) { 6479 seq_printf(m, "invalid dpm profile %d\n", current_index); 6480 } else { 6481 pl = &ps->performance_levels[current_index]; 6482 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6483 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6484 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6485 } 6486 } 6487