1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/math64.h> 25 #include <linux/pci.h> 26 #include <linux/seq_file.h> 27 28 #include "atom.h" 29 #include "evergreen.h" 30 #include "r600_dpm.h" 31 #include "rv770.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "ni_dpm.h" 35 #include "si_dpm.h" 36 #include "si.h" 37 #include "sid.h" 38 #include "vce.h" 39 40 #define MC_CG_ARB_FREQ_F0 0x0a 41 #define MC_CG_ARB_FREQ_F1 0x0b 42 #define MC_CG_ARB_FREQ_F2 0x0c 43 #define MC_CG_ARB_FREQ_F3 0x0d 44 45 #define SMC_RAM_END 0x20000 46 47 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 48 49 static const struct si_cac_config_reg cac_weights_tahiti[] = 50 { 51 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 52 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 54 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 59 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 61 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 63 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 64 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 65 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 66 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 69 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 71 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 72 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 73 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 82 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 86 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 89 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 91 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 107 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 108 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 109 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 110 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 111 { 0xFFFFFFFF } 112 }; 113 114 static const struct si_cac_config_reg lcac_tahiti[] = 115 { 116 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 121 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 123 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 137 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 139 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 161 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 163 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 173 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 175 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 185 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 187 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 189 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 199 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 200 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 201 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 202 { 0xFFFFFFFF } 203 204 }; 205 206 static const struct si_cac_config_reg cac_override_tahiti[] = 207 { 208 { 0xFFFFFFFF } 209 }; 210 211 static const struct si_powertune_data powertune_data_tahiti = 212 { 213 ((1 << 16) | 27027), 214 6, 215 0, 216 4, 217 95, 218 { 219 0UL, 220 0UL, 221 4521550UL, 222 309631529UL, 223 -1270850L, 224 4513710L, 225 40 226 }, 227 595000000UL, 228 12, 229 { 230 0, 231 0, 232 0, 233 0, 234 0, 235 0, 236 0, 237 0 238 }, 239 true 240 }; 241 242 static const struct si_dte_data dte_data_tahiti = 243 { 244 { 1159409, 0, 0, 0, 0 }, 245 { 777, 0, 0, 0, 0 }, 246 2, 247 54000, 248 127000, 249 25, 250 2, 251 10, 252 13, 253 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 254 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 255 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 256 85, 257 false 258 }; 259 260 static const struct si_dte_data dte_data_tahiti_pro = 261 { 262 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 263 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 264 5, 265 45000, 266 100, 267 0xA, 268 1, 269 0, 270 0x10, 271 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 272 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 273 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 274 90, 275 true 276 }; 277 278 static const struct si_dte_data dte_data_new_zealand = 279 { 280 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 281 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 282 0x5, 283 0xAFC8, 284 0x69, 285 0x32, 286 1, 287 0, 288 0x10, 289 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 290 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 291 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 292 85, 293 true 294 }; 295 296 static const struct si_dte_data dte_data_aruba_pro = 297 { 298 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 299 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 300 5, 301 45000, 302 100, 303 0xA, 304 1, 305 0, 306 0x10, 307 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 308 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 309 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 310 90, 311 true 312 }; 313 314 static const struct si_dte_data dte_data_malta = 315 { 316 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 317 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 318 5, 319 45000, 320 100, 321 0xA, 322 1, 323 0, 324 0x10, 325 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 326 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 327 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 328 90, 329 true 330 }; 331 332 struct si_cac_config_reg cac_weights_pitcairn[] = 333 { 334 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 335 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 336 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 337 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 338 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 339 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 340 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 341 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 342 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 343 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 344 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 345 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 346 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 347 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 348 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 351 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 352 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 353 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 354 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 355 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 356 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 357 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 358 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 359 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 360 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 361 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 365 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 366 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 367 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 368 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 369 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 370 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 371 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 373 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 394 { 0xFFFFFFFF } 395 }; 396 397 static const struct si_cac_config_reg lcac_pitcairn[] = 398 { 399 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 400 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 401 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 402 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 403 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 404 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 405 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 406 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 407 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 408 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 409 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 410 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 411 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 454 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 456 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 460 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 462 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 464 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 466 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 468 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 470 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 474 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 476 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 478 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 480 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 482 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 484 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0xFFFFFFFF } 486 }; 487 488 static const struct si_cac_config_reg cac_override_pitcairn[] = 489 { 490 { 0xFFFFFFFF } 491 }; 492 493 static const struct si_powertune_data powertune_data_pitcairn = 494 { 495 ((1 << 16) | 27027), 496 5, 497 0, 498 6, 499 100, 500 { 501 51600000UL, 502 1800000UL, 503 7194395UL, 504 309631529UL, 505 -1270850L, 506 4513710L, 507 100 508 }, 509 117830498UL, 510 12, 511 { 512 0, 513 0, 514 0, 515 0, 516 0, 517 0, 518 0, 519 0 520 }, 521 true 522 }; 523 524 static const struct si_dte_data dte_data_pitcairn = 525 { 526 { 0, 0, 0, 0, 0 }, 527 { 0, 0, 0, 0, 0 }, 528 0, 529 0, 530 0, 531 0, 532 0, 533 0, 534 0, 535 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 536 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 537 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 538 0, 539 false 540 }; 541 542 static const struct si_dte_data dte_data_curacao_xt = 543 { 544 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 545 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 546 5, 547 45000, 548 100, 549 0xA, 550 1, 551 0, 552 0x10, 553 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 554 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 555 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 556 90, 557 true 558 }; 559 560 static const struct si_dte_data dte_data_curacao_pro = 561 { 562 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 563 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 564 5, 565 45000, 566 100, 567 0xA, 568 1, 569 0, 570 0x10, 571 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 572 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 573 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 574 90, 575 true 576 }; 577 578 static const struct si_dte_data dte_data_neptune_xt = 579 { 580 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 581 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 582 5, 583 45000, 584 100, 585 0xA, 586 1, 587 0, 588 0x10, 589 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 590 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 591 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 592 90, 593 true 594 }; 595 596 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 597 { 598 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 599 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 600 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 601 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 602 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 603 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 604 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 605 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 606 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 607 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 608 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 609 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 610 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 611 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 612 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 613 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 614 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 615 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 616 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 617 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 618 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 619 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 620 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 621 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 622 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 623 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 624 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 625 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 626 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 627 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 628 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 629 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 630 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 631 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 632 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 633 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 634 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 635 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 636 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 638 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 639 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 641 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 642 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 643 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 644 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 645 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 650 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 658 { 0xFFFFFFFF } 659 }; 660 661 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 662 { 663 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 664 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 667 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 669 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 670 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 671 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 672 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 673 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 674 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 675 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 676 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 677 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 678 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 679 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 680 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 681 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 682 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 683 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 684 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 685 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 686 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 687 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 688 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 689 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 690 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 691 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 692 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 693 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 694 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 695 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 696 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 697 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 698 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 699 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 700 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 701 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 703 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 704 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 706 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 707 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 708 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 709 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 710 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 715 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 723 { 0xFFFFFFFF } 724 }; 725 726 static const struct si_cac_config_reg cac_weights_heathrow[] = 727 { 728 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 729 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 732 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 734 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 735 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 736 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 737 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 738 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 739 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 740 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 741 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 742 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 743 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 744 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 745 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 746 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 747 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 748 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 749 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 750 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 751 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 752 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 753 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 754 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 755 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 757 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 758 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 759 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 760 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 761 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 762 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 763 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 764 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 766 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 768 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 769 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 780 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 788 { 0xFFFFFFFF } 789 }; 790 791 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 792 { 793 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 794 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 797 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 799 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 800 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 801 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 802 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 803 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 804 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 805 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 806 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 807 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 808 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 809 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 810 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 811 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 812 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 813 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 814 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 815 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 816 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 817 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 818 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 819 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 820 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 822 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 823 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 824 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 825 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 826 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 827 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 828 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 829 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 831 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 833 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 834 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 845 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 853 { 0xFFFFFFFF } 854 }; 855 856 static const struct si_cac_config_reg cac_weights_cape_verde[] = 857 { 858 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 859 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 862 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 864 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 865 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 866 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 867 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 868 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 869 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 870 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 871 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 872 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 873 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 874 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 875 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 876 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 877 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 878 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 879 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 880 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 881 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 882 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 883 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 884 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 885 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 887 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 888 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 889 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 890 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 891 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 892 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 893 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 894 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 896 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 898 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 899 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 910 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 918 { 0xFFFFFFFF } 919 }; 920 921 static const struct si_cac_config_reg lcac_cape_verde[] = 922 { 923 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 924 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 925 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 926 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 927 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 928 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 929 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 930 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 931 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 932 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 933 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 934 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 935 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 952 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 954 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 956 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 958 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0xFFFFFFFF } 978 }; 979 980 static const struct si_cac_config_reg cac_override_cape_verde[] = 981 { 982 { 0xFFFFFFFF } 983 }; 984 985 static const struct si_powertune_data powertune_data_cape_verde = 986 { 987 ((1 << 16) | 0x6993), 988 5, 989 0, 990 7, 991 105, 992 { 993 0UL, 994 0UL, 995 7194395UL, 996 309631529UL, 997 -1270850L, 998 4513710L, 999 100 1000 }, 1001 117830498UL, 1002 12, 1003 { 1004 0, 1005 0, 1006 0, 1007 0, 1008 0, 1009 0, 1010 0, 1011 0 1012 }, 1013 true 1014 }; 1015 1016 static const struct si_dte_data dte_data_cape_verde = 1017 { 1018 { 0, 0, 0, 0, 0 }, 1019 { 0, 0, 0, 0, 0 }, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0, 1025 0, 1026 0, 1027 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1028 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1029 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1030 0, 1031 false 1032 }; 1033 1034 static const struct si_dte_data dte_data_venus_xtx = 1035 { 1036 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1037 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1038 5, 1039 55000, 1040 0x69, 1041 0xA, 1042 1, 1043 0, 1044 0x3, 1045 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1046 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1047 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1048 90, 1049 true 1050 }; 1051 1052 static const struct si_dte_data dte_data_venus_xt = 1053 { 1054 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1055 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1056 5, 1057 55000, 1058 0x69, 1059 0xA, 1060 1, 1061 0, 1062 0x3, 1063 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1064 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1065 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1066 90, 1067 true 1068 }; 1069 1070 static const struct si_dte_data dte_data_venus_pro = 1071 { 1072 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1073 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1074 5, 1075 55000, 1076 0x69, 1077 0xA, 1078 1, 1079 0, 1080 0x3, 1081 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1082 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1083 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1084 90, 1085 true 1086 }; 1087 1088 struct si_cac_config_reg cac_weights_oland[] = 1089 { 1090 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1096 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1097 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1098 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1099 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1100 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1101 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1109 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1110 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1111 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1112 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1113 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1114 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1115 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1116 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1117 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1123 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1124 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1125 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1127 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1128 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1150 { 0xFFFFFFFF } 1151 }; 1152 1153 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1154 { 1155 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1164 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1165 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1166 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1174 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1175 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1176 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1177 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1178 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1179 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1180 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1181 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1182 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1188 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1189 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1190 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1191 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1192 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1193 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1215 { 0xFFFFFFFF } 1216 }; 1217 1218 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1219 { 1220 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1239 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1240 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1241 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1242 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1243 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1244 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1245 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1246 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1247 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1280 { 0xFFFFFFFF } 1281 }; 1282 1283 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1284 { 1285 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1304 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1305 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1306 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1307 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1308 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1309 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1310 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1311 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1312 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1345 { 0xFFFFFFFF } 1346 }; 1347 1348 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1349 { 1350 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1369 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1370 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1371 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1372 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1373 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1374 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1375 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1376 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1377 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1410 { 0xFFFFFFFF } 1411 }; 1412 1413 static const struct si_cac_config_reg lcac_oland[] = 1414 { 1415 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1424 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1425 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1426 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0xFFFFFFFF } 1458 }; 1459 1460 static const struct si_cac_config_reg lcac_mars_pro[] = 1461 { 1462 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0xFFFFFFFF } 1505 }; 1506 1507 static const struct si_cac_config_reg cac_override_oland[] = 1508 { 1509 { 0xFFFFFFFF } 1510 }; 1511 1512 static const struct si_powertune_data powertune_data_oland = 1513 { 1514 ((1 << 16) | 0x6993), 1515 5, 1516 0, 1517 7, 1518 105, 1519 { 1520 0UL, 1521 0UL, 1522 7194395UL, 1523 309631529UL, 1524 -1270850L, 1525 4513710L, 1526 100 1527 }, 1528 117830498UL, 1529 12, 1530 { 1531 0, 1532 0, 1533 0, 1534 0, 1535 0, 1536 0, 1537 0, 1538 0 1539 }, 1540 true 1541 }; 1542 1543 static const struct si_powertune_data powertune_data_mars_pro = 1544 { 1545 ((1 << 16) | 0x6993), 1546 5, 1547 0, 1548 7, 1549 105, 1550 { 1551 0UL, 1552 0UL, 1553 7194395UL, 1554 309631529UL, 1555 -1270850L, 1556 4513710L, 1557 100 1558 }, 1559 117830498UL, 1560 12, 1561 { 1562 0, 1563 0, 1564 0, 1565 0, 1566 0, 1567 0, 1568 0, 1569 0 1570 }, 1571 true 1572 }; 1573 1574 static const struct si_dte_data dte_data_oland = 1575 { 1576 { 0, 0, 0, 0, 0 }, 1577 { 0, 0, 0, 0, 0 }, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0, 1583 0, 1584 0, 1585 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1586 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1587 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1588 0, 1589 false 1590 }; 1591 1592 static const struct si_dte_data dte_data_mars_pro = 1593 { 1594 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1595 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1596 5, 1597 55000, 1598 105, 1599 0xA, 1600 1, 1601 0, 1602 0x10, 1603 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1604 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1605 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1606 90, 1607 true 1608 }; 1609 1610 static const struct si_dte_data dte_data_sun_xt = 1611 { 1612 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1613 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1614 5, 1615 55000, 1616 105, 1617 0xA, 1618 1, 1619 0, 1620 0x10, 1621 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1622 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1623 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1624 90, 1625 true 1626 }; 1627 1628 1629 static const struct si_cac_config_reg cac_weights_hainan[] = 1630 { 1631 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1632 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1633 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1634 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1635 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1636 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1637 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1638 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1639 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1640 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1641 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1642 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1650 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1651 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1652 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1654 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1655 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1657 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1658 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1664 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1665 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1666 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1667 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1668 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1669 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1691 { 0xFFFFFFFF } 1692 }; 1693 1694 static const struct si_powertune_data powertune_data_hainan = 1695 { 1696 ((1 << 16) | 0x6993), 1697 5, 1698 0, 1699 9, 1700 105, 1701 { 1702 0UL, 1703 0UL, 1704 7194395UL, 1705 309631529UL, 1706 -1270850L, 1707 4513710L, 1708 100 1709 }, 1710 117830498UL, 1711 12, 1712 { 1713 0, 1714 0, 1715 0, 1716 0, 1717 0, 1718 0, 1719 0, 1720 0 1721 }, 1722 true 1723 }; 1724 1725 static int si_populate_voltage_value(struct radeon_device *rdev, 1726 const struct atom_voltage_table *table, 1727 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1728 static int si_get_std_voltage_value(struct radeon_device *rdev, 1729 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1730 u16 *std_voltage); 1731 static int si_write_smc_soft_register(struct radeon_device *rdev, 1732 u16 reg_offset, u32 value); 1733 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1734 struct rv7xx_pl *pl, 1735 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1736 static int si_calculate_sclk_params(struct radeon_device *rdev, 1737 u32 engine_clock, 1738 SISLANDS_SMC_SCLK_VALUE *sclk); 1739 1740 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1741 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1742 1743 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1744 { 1745 struct si_power_info *pi = rdev->pm.dpm.priv; 1746 1747 return pi; 1748 } 1749 1750 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1751 u16 v, s32 t, u32 ileakage, u32 *leakage) 1752 { 1753 s64 kt, kv, leakage_w, i_leakage, vddc; 1754 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1755 s64 tmp; 1756 1757 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1758 vddc = div64_s64(drm_int2fixp(v), 1000); 1759 temperature = div64_s64(drm_int2fixp(t), 1000); 1760 1761 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1762 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1763 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1764 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1765 t_ref = drm_int2fixp(coeff->t_ref); 1766 1767 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1768 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1769 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1770 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1771 1772 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1773 1774 *leakage = drm_fixp2int(leakage_w * 1000); 1775 } 1776 1777 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1778 const struct ni_leakage_coeffients *coeff, 1779 u16 v, 1780 s32 t, 1781 u32 i_leakage, 1782 u32 *leakage) 1783 { 1784 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1785 } 1786 1787 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1788 const u32 fixed_kt, u16 v, 1789 u32 ileakage, u32 *leakage) 1790 { 1791 s64 kt, kv, leakage_w, i_leakage, vddc; 1792 1793 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1794 vddc = div64_s64(drm_int2fixp(v), 1000); 1795 1796 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1797 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1798 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1799 1800 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1801 1802 *leakage = drm_fixp2int(leakage_w * 1000); 1803 } 1804 1805 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1806 const struct ni_leakage_coeffients *coeff, 1807 const u32 fixed_kt, 1808 u16 v, 1809 u32 i_leakage, 1810 u32 *leakage) 1811 { 1812 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1813 } 1814 1815 1816 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1817 struct si_dte_data *dte_data) 1818 { 1819 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1820 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1821 u32 k = dte_data->k; 1822 u32 t_max = dte_data->max_t; 1823 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1824 u32 t_0 = dte_data->t0; 1825 u32 i; 1826 1827 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1828 dte_data->tdep_count = 3; 1829 1830 for (i = 0; i < k; i++) { 1831 dte_data->r[i] = 1832 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1833 (p_limit2 * (u32)100); 1834 } 1835 1836 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1837 1838 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1839 dte_data->tdep_r[i] = dte_data->r[4]; 1840 } 1841 } else { 1842 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1843 } 1844 } 1845 1846 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1847 { 1848 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1849 struct si_power_info *si_pi = si_get_pi(rdev); 1850 bool update_dte_from_pl2 = false; 1851 1852 if (rdev->family == CHIP_TAHITI) { 1853 si_pi->cac_weights = cac_weights_tahiti; 1854 si_pi->lcac_config = lcac_tahiti; 1855 si_pi->cac_override = cac_override_tahiti; 1856 si_pi->powertune_data = &powertune_data_tahiti; 1857 si_pi->dte_data = dte_data_tahiti; 1858 1859 switch (rdev->pdev->device) { 1860 case 0x6798: 1861 si_pi->dte_data.enable_dte_by_default = true; 1862 break; 1863 case 0x6799: 1864 si_pi->dte_data = dte_data_new_zealand; 1865 break; 1866 case 0x6790: 1867 case 0x6791: 1868 case 0x6792: 1869 case 0x679E: 1870 si_pi->dte_data = dte_data_aruba_pro; 1871 update_dte_from_pl2 = true; 1872 break; 1873 case 0x679B: 1874 si_pi->dte_data = dte_data_malta; 1875 update_dte_from_pl2 = true; 1876 break; 1877 case 0x679A: 1878 si_pi->dte_data = dte_data_tahiti_pro; 1879 update_dte_from_pl2 = true; 1880 break; 1881 default: 1882 if (si_pi->dte_data.enable_dte_by_default == true) 1883 DRM_ERROR("DTE is not enabled!\n"); 1884 break; 1885 } 1886 } else if (rdev->family == CHIP_PITCAIRN) { 1887 switch (rdev->pdev->device) { 1888 case 0x6810: 1889 case 0x6818: 1890 si_pi->cac_weights = cac_weights_pitcairn; 1891 si_pi->lcac_config = lcac_pitcairn; 1892 si_pi->cac_override = cac_override_pitcairn; 1893 si_pi->powertune_data = &powertune_data_pitcairn; 1894 si_pi->dte_data = dte_data_curacao_xt; 1895 update_dte_from_pl2 = true; 1896 break; 1897 case 0x6819: 1898 case 0x6811: 1899 si_pi->cac_weights = cac_weights_pitcairn; 1900 si_pi->lcac_config = lcac_pitcairn; 1901 si_pi->cac_override = cac_override_pitcairn; 1902 si_pi->powertune_data = &powertune_data_pitcairn; 1903 si_pi->dte_data = dte_data_curacao_pro; 1904 update_dte_from_pl2 = true; 1905 break; 1906 case 0x6800: 1907 case 0x6806: 1908 si_pi->cac_weights = cac_weights_pitcairn; 1909 si_pi->lcac_config = lcac_pitcairn; 1910 si_pi->cac_override = cac_override_pitcairn; 1911 si_pi->powertune_data = &powertune_data_pitcairn; 1912 si_pi->dte_data = dte_data_neptune_xt; 1913 update_dte_from_pl2 = true; 1914 break; 1915 default: 1916 si_pi->cac_weights = cac_weights_pitcairn; 1917 si_pi->lcac_config = lcac_pitcairn; 1918 si_pi->cac_override = cac_override_pitcairn; 1919 si_pi->powertune_data = &powertune_data_pitcairn; 1920 si_pi->dte_data = dte_data_pitcairn; 1921 break; 1922 } 1923 } else if (rdev->family == CHIP_VERDE) { 1924 si_pi->lcac_config = lcac_cape_verde; 1925 si_pi->cac_override = cac_override_cape_verde; 1926 si_pi->powertune_data = &powertune_data_cape_verde; 1927 1928 switch (rdev->pdev->device) { 1929 case 0x683B: 1930 case 0x683F: 1931 case 0x6829: 1932 case 0x6835: 1933 si_pi->cac_weights = cac_weights_cape_verde_pro; 1934 si_pi->dte_data = dte_data_cape_verde; 1935 break; 1936 case 0x682C: 1937 si_pi->cac_weights = cac_weights_cape_verde_pro; 1938 si_pi->dte_data = dte_data_sun_xt; 1939 update_dte_from_pl2 = true; 1940 break; 1941 case 0x6825: 1942 case 0x6827: 1943 si_pi->cac_weights = cac_weights_heathrow; 1944 si_pi->dte_data = dte_data_cape_verde; 1945 break; 1946 case 0x6824: 1947 case 0x682D: 1948 si_pi->cac_weights = cac_weights_chelsea_xt; 1949 si_pi->dte_data = dte_data_cape_verde; 1950 break; 1951 case 0x682F: 1952 si_pi->cac_weights = cac_weights_chelsea_pro; 1953 si_pi->dte_data = dte_data_cape_verde; 1954 break; 1955 case 0x6820: 1956 si_pi->cac_weights = cac_weights_heathrow; 1957 si_pi->dte_data = dte_data_venus_xtx; 1958 break; 1959 case 0x6821: 1960 si_pi->cac_weights = cac_weights_heathrow; 1961 si_pi->dte_data = dte_data_venus_xt; 1962 break; 1963 case 0x6823: 1964 case 0x682B: 1965 case 0x6822: 1966 case 0x682A: 1967 si_pi->cac_weights = cac_weights_chelsea_pro; 1968 si_pi->dte_data = dte_data_venus_pro; 1969 break; 1970 default: 1971 si_pi->cac_weights = cac_weights_cape_verde; 1972 si_pi->dte_data = dte_data_cape_verde; 1973 break; 1974 } 1975 } else if (rdev->family == CHIP_OLAND) { 1976 switch (rdev->pdev->device) { 1977 case 0x6601: 1978 case 0x6621: 1979 case 0x6603: 1980 case 0x6605: 1981 si_pi->cac_weights = cac_weights_mars_pro; 1982 si_pi->lcac_config = lcac_mars_pro; 1983 si_pi->cac_override = cac_override_oland; 1984 si_pi->powertune_data = &powertune_data_mars_pro; 1985 si_pi->dte_data = dte_data_mars_pro; 1986 update_dte_from_pl2 = true; 1987 break; 1988 case 0x6600: 1989 case 0x6606: 1990 case 0x6620: 1991 case 0x6604: 1992 si_pi->cac_weights = cac_weights_mars_xt; 1993 si_pi->lcac_config = lcac_mars_pro; 1994 si_pi->cac_override = cac_override_oland; 1995 si_pi->powertune_data = &powertune_data_mars_pro; 1996 si_pi->dte_data = dte_data_mars_pro; 1997 update_dte_from_pl2 = true; 1998 break; 1999 case 0x6611: 2000 case 0x6613: 2001 case 0x6608: 2002 si_pi->cac_weights = cac_weights_oland_pro; 2003 si_pi->lcac_config = lcac_mars_pro; 2004 si_pi->cac_override = cac_override_oland; 2005 si_pi->powertune_data = &powertune_data_mars_pro; 2006 si_pi->dte_data = dte_data_mars_pro; 2007 update_dte_from_pl2 = true; 2008 break; 2009 case 0x6610: 2010 si_pi->cac_weights = cac_weights_oland_xt; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 default: 2018 si_pi->cac_weights = cac_weights_oland; 2019 si_pi->lcac_config = lcac_oland; 2020 si_pi->cac_override = cac_override_oland; 2021 si_pi->powertune_data = &powertune_data_oland; 2022 si_pi->dte_data = dte_data_oland; 2023 break; 2024 } 2025 } else if (rdev->family == CHIP_HAINAN) { 2026 si_pi->cac_weights = cac_weights_hainan; 2027 si_pi->lcac_config = lcac_oland; 2028 si_pi->cac_override = cac_override_oland; 2029 si_pi->powertune_data = &powertune_data_hainan; 2030 si_pi->dte_data = dte_data_sun_xt; 2031 update_dte_from_pl2 = true; 2032 } else { 2033 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2034 return; 2035 } 2036 2037 ni_pi->enable_power_containment = false; 2038 ni_pi->enable_cac = false; 2039 ni_pi->enable_sq_ramping = false; 2040 si_pi->enable_dte = false; 2041 2042 if (si_pi->powertune_data->enable_powertune_by_default) { 2043 ni_pi->enable_power_containment= true; 2044 ni_pi->enable_cac = true; 2045 if (si_pi->dte_data.enable_dte_by_default) { 2046 si_pi->enable_dte = true; 2047 if (update_dte_from_pl2) 2048 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2049 2050 } 2051 ni_pi->enable_sq_ramping = true; 2052 } 2053 2054 ni_pi->driver_calculate_cac_leakage = true; 2055 ni_pi->cac_configuration_required = true; 2056 2057 if (ni_pi->cac_configuration_required) { 2058 ni_pi->support_cac_long_term_average = true; 2059 si_pi->dyn_powertune_data.l2_lta_window_size = 2060 si_pi->powertune_data->l2_lta_window_size_default; 2061 si_pi->dyn_powertune_data.lts_truncate = 2062 si_pi->powertune_data->lts_truncate_default; 2063 } else { 2064 ni_pi->support_cac_long_term_average = false; 2065 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2066 si_pi->dyn_powertune_data.lts_truncate = 0; 2067 } 2068 2069 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2070 } 2071 2072 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2073 { 2074 return 1; 2075 } 2076 2077 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2078 { 2079 u32 xclk; 2080 u32 wintime; 2081 u32 cac_window; 2082 u32 cac_window_size; 2083 2084 xclk = radeon_get_xclk(rdev); 2085 2086 if (xclk == 0) 2087 return 0; 2088 2089 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2090 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2091 2092 wintime = (cac_window_size * 100) / xclk; 2093 2094 return wintime; 2095 } 2096 2097 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2098 { 2099 return power_in_watts; 2100 } 2101 2102 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2103 bool adjust_polarity, 2104 u32 tdp_adjustment, 2105 u32 *tdp_limit, 2106 u32 *near_tdp_limit) 2107 { 2108 u32 adjustment_delta, max_tdp_limit; 2109 2110 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2111 return -EINVAL; 2112 2113 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2114 2115 if (adjust_polarity) { 2116 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2117 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2118 } else { 2119 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2120 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2121 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2122 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2123 else 2124 *near_tdp_limit = 0; 2125 } 2126 2127 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2128 return -EINVAL; 2129 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2130 return -EINVAL; 2131 2132 return 0; 2133 } 2134 2135 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2136 struct radeon_ps *radeon_state) 2137 { 2138 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2139 struct si_power_info *si_pi = si_get_pi(rdev); 2140 2141 if (ni_pi->enable_power_containment) { 2142 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2143 PP_SIslands_PAPMParameters *papm_parm; 2144 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2145 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2146 u32 tdp_limit; 2147 u32 near_tdp_limit; 2148 int ret; 2149 2150 if (scaling_factor == 0) 2151 return -EINVAL; 2152 2153 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2154 2155 ret = si_calculate_adjusted_tdp_limits(rdev, 2156 false, /* ??? */ 2157 rdev->pm.dpm.tdp_adjustment, 2158 &tdp_limit, 2159 &near_tdp_limit); 2160 if (ret) 2161 return ret; 2162 2163 smc_table->dpm2Params.TDPLimit = 2164 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2165 smc_table->dpm2Params.NearTDPLimit = 2166 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2167 smc_table->dpm2Params.SafePowerLimit = 2168 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2169 2170 ret = si_copy_bytes_to_smc(rdev, 2171 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2172 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2173 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2174 sizeof(u32) * 3, 2175 si_pi->sram_end); 2176 if (ret) 2177 return ret; 2178 2179 if (si_pi->enable_ppm) { 2180 papm_parm = &si_pi->papm_parm; 2181 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2182 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2183 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2184 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2185 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2186 papm_parm->PlatformPowerLimit = 0xffffffff; 2187 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2188 2189 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2190 (u8 *)papm_parm, 2191 sizeof(PP_SIslands_PAPMParameters), 2192 si_pi->sram_end); 2193 if (ret) 2194 return ret; 2195 } 2196 } 2197 return 0; 2198 } 2199 2200 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2201 struct radeon_ps *radeon_state) 2202 { 2203 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2204 struct si_power_info *si_pi = si_get_pi(rdev); 2205 2206 if (ni_pi->enable_power_containment) { 2207 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2208 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2209 int ret; 2210 2211 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2212 2213 smc_table->dpm2Params.NearTDPLimit = 2214 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2215 smc_table->dpm2Params.SafePowerLimit = 2216 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2217 2218 ret = si_copy_bytes_to_smc(rdev, 2219 (si_pi->state_table_start + 2220 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2221 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2222 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2223 sizeof(u32) * 2, 2224 si_pi->sram_end); 2225 if (ret) 2226 return ret; 2227 } 2228 2229 return 0; 2230 } 2231 2232 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2233 const u16 prev_std_vddc, 2234 const u16 curr_std_vddc) 2235 { 2236 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2237 u64 prev_vddc = (u64)prev_std_vddc; 2238 u64 curr_vddc = (u64)curr_std_vddc; 2239 u64 pwr_efficiency_ratio, n, d; 2240 2241 if ((prev_vddc == 0) || (curr_vddc == 0)) 2242 return 0; 2243 2244 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2245 d = prev_vddc * prev_vddc; 2246 pwr_efficiency_ratio = div64_u64(n, d); 2247 2248 if (pwr_efficiency_ratio > (u64)0xFFFF) 2249 return 0; 2250 2251 return (u16)pwr_efficiency_ratio; 2252 } 2253 2254 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2255 struct radeon_ps *radeon_state) 2256 { 2257 struct si_power_info *si_pi = si_get_pi(rdev); 2258 2259 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2260 radeon_state->vclk && radeon_state->dclk) 2261 return true; 2262 2263 return false; 2264 } 2265 2266 static int si_populate_power_containment_values(struct radeon_device *rdev, 2267 struct radeon_ps *radeon_state, 2268 SISLANDS_SMC_SWSTATE *smc_state) 2269 { 2270 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2271 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2272 struct ni_ps *state = ni_get_ps(radeon_state); 2273 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2274 u32 prev_sclk; 2275 u32 max_sclk; 2276 u32 min_sclk; 2277 u16 prev_std_vddc; 2278 u16 curr_std_vddc; 2279 int i; 2280 u16 pwr_efficiency_ratio; 2281 u8 max_ps_percent; 2282 bool disable_uvd_power_tune; 2283 int ret; 2284 2285 if (ni_pi->enable_power_containment == false) 2286 return 0; 2287 2288 if (state->performance_level_count == 0) 2289 return -EINVAL; 2290 2291 if (smc_state->levelCount != state->performance_level_count) 2292 return -EINVAL; 2293 2294 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2295 2296 smc_state->levels[0].dpm2.MaxPS = 0; 2297 smc_state->levels[0].dpm2.NearTDPDec = 0; 2298 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2299 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2300 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2301 2302 for (i = 1; i < state->performance_level_count; i++) { 2303 prev_sclk = state->performance_levels[i-1].sclk; 2304 max_sclk = state->performance_levels[i].sclk; 2305 if (i == 1) 2306 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2307 else 2308 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2309 2310 if (prev_sclk > max_sclk) 2311 return -EINVAL; 2312 2313 if ((max_ps_percent == 0) || 2314 (prev_sclk == max_sclk) || 2315 disable_uvd_power_tune) { 2316 min_sclk = max_sclk; 2317 } else if (i == 1) { 2318 min_sclk = prev_sclk; 2319 } else { 2320 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2321 } 2322 2323 if (min_sclk < state->performance_levels[0].sclk) 2324 min_sclk = state->performance_levels[0].sclk; 2325 2326 if (min_sclk == 0) 2327 return -EINVAL; 2328 2329 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2330 state->performance_levels[i-1].vddc, &vddc); 2331 if (ret) 2332 return ret; 2333 2334 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2335 if (ret) 2336 return ret; 2337 2338 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2339 state->performance_levels[i].vddc, &vddc); 2340 if (ret) 2341 return ret; 2342 2343 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2344 if (ret) 2345 return ret; 2346 2347 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2348 prev_std_vddc, curr_std_vddc); 2349 2350 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2351 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2352 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2353 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2354 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2361 struct radeon_ps *radeon_state, 2362 SISLANDS_SMC_SWSTATE *smc_state) 2363 { 2364 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2365 struct ni_ps *state = ni_get_ps(radeon_state); 2366 u32 sq_power_throttle, sq_power_throttle2; 2367 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2368 int i; 2369 2370 if (state->performance_level_count == 0) 2371 return -EINVAL; 2372 2373 if (smc_state->levelCount != state->performance_level_count) 2374 return -EINVAL; 2375 2376 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2377 return -EINVAL; 2378 2379 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2380 enable_sq_ramping = false; 2381 2382 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2383 enable_sq_ramping = false; 2384 2385 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2386 enable_sq_ramping = false; 2387 2388 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2389 enable_sq_ramping = false; 2390 2391 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2392 enable_sq_ramping = false; 2393 2394 for (i = 0; i < state->performance_level_count; i++) { 2395 sq_power_throttle = 0; 2396 sq_power_throttle2 = 0; 2397 2398 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2399 enable_sq_ramping) { 2400 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2401 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2402 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2403 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2404 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2405 } else { 2406 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2407 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2408 } 2409 2410 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2411 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2412 } 2413 2414 return 0; 2415 } 2416 2417 static int si_enable_power_containment(struct radeon_device *rdev, 2418 struct radeon_ps *radeon_new_state, 2419 bool enable) 2420 { 2421 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2422 PPSMC_Result smc_result; 2423 int ret = 0; 2424 2425 if (ni_pi->enable_power_containment) { 2426 if (enable) { 2427 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2428 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2429 if (smc_result != PPSMC_Result_OK) { 2430 ret = -EINVAL; 2431 ni_pi->pc_enabled = false; 2432 } else { 2433 ni_pi->pc_enabled = true; 2434 } 2435 } 2436 } else { 2437 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2438 if (smc_result != PPSMC_Result_OK) 2439 ret = -EINVAL; 2440 ni_pi->pc_enabled = false; 2441 } 2442 } 2443 2444 return ret; 2445 } 2446 2447 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2448 { 2449 struct si_power_info *si_pi = si_get_pi(rdev); 2450 int ret = 0; 2451 struct si_dte_data *dte_data = &si_pi->dte_data; 2452 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2453 u32 table_size; 2454 u8 tdep_count; 2455 u32 i; 2456 2457 if (dte_data == NULL) 2458 si_pi->enable_dte = false; 2459 2460 if (si_pi->enable_dte == false) 2461 return 0; 2462 2463 if (dte_data->k <= 0) 2464 return -EINVAL; 2465 2466 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2467 if (dte_tables == NULL) { 2468 si_pi->enable_dte = false; 2469 return -ENOMEM; 2470 } 2471 2472 table_size = dte_data->k; 2473 2474 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2475 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2476 2477 tdep_count = dte_data->tdep_count; 2478 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2479 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2480 2481 dte_tables->K = cpu_to_be32(table_size); 2482 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2483 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2484 dte_tables->WindowSize = dte_data->window_size; 2485 dte_tables->temp_select = dte_data->temp_select; 2486 dte_tables->DTE_mode = dte_data->dte_mode; 2487 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2488 2489 if (tdep_count > 0) 2490 table_size--; 2491 2492 for (i = 0; i < table_size; i++) { 2493 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2494 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2495 } 2496 2497 dte_tables->Tdep_count = tdep_count; 2498 2499 for (i = 0; i < (u32)tdep_count; i++) { 2500 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2501 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2502 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2503 } 2504 2505 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2506 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2507 kfree(dte_tables); 2508 2509 return ret; 2510 } 2511 2512 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2513 u16 *max, u16 *min) 2514 { 2515 struct si_power_info *si_pi = si_get_pi(rdev); 2516 struct radeon_cac_leakage_table *table = 2517 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2518 u32 i; 2519 u32 v0_loadline; 2520 2521 2522 if (table == NULL) 2523 return -EINVAL; 2524 2525 *max = 0; 2526 *min = 0xFFFF; 2527 2528 for (i = 0; i < table->count; i++) { 2529 if (table->entries[i].vddc > *max) 2530 *max = table->entries[i].vddc; 2531 if (table->entries[i].vddc < *min) 2532 *min = table->entries[i].vddc; 2533 } 2534 2535 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2536 return -EINVAL; 2537 2538 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2539 2540 if (v0_loadline > 0xFFFFUL) 2541 return -EINVAL; 2542 2543 *min = (u16)v0_loadline; 2544 2545 if ((*min > *max) || (*max == 0) || (*min == 0)) 2546 return -EINVAL; 2547 2548 return 0; 2549 } 2550 2551 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2552 { 2553 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2554 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2555 } 2556 2557 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2558 PP_SIslands_CacConfig *cac_tables, 2559 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2560 u16 t0, u16 t_step) 2561 { 2562 struct si_power_info *si_pi = si_get_pi(rdev); 2563 u32 leakage; 2564 unsigned int i, j; 2565 s32 t; 2566 u32 smc_leakage; 2567 u32 scaling_factor; 2568 u16 voltage; 2569 2570 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2571 2572 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2573 t = (1000 * (i * t_step + t0)); 2574 2575 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2576 voltage = vddc_max - (vddc_step * j); 2577 2578 si_calculate_leakage_for_v_and_t(rdev, 2579 &si_pi->powertune_data->leakage_coefficients, 2580 voltage, 2581 t, 2582 si_pi->dyn_powertune_data.cac_leakage, 2583 &leakage); 2584 2585 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2586 2587 if (smc_leakage > 0xFFFF) 2588 smc_leakage = 0xFFFF; 2589 2590 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2591 cpu_to_be16((u16)smc_leakage); 2592 } 2593 } 2594 return 0; 2595 } 2596 2597 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2598 PP_SIslands_CacConfig *cac_tables, 2599 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2600 { 2601 struct si_power_info *si_pi = si_get_pi(rdev); 2602 u32 leakage; 2603 unsigned int i, j; 2604 u32 smc_leakage; 2605 u32 scaling_factor; 2606 u16 voltage; 2607 2608 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2609 2610 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2611 voltage = vddc_max - (vddc_step * j); 2612 2613 si_calculate_leakage_for_v(rdev, 2614 &si_pi->powertune_data->leakage_coefficients, 2615 si_pi->powertune_data->fixed_kt, 2616 voltage, 2617 si_pi->dyn_powertune_data.cac_leakage, 2618 &leakage); 2619 2620 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2621 2622 if (smc_leakage > 0xFFFF) 2623 smc_leakage = 0xFFFF; 2624 2625 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2626 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2627 cpu_to_be16((u16)smc_leakage); 2628 } 2629 return 0; 2630 } 2631 2632 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2633 { 2634 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2635 struct si_power_info *si_pi = si_get_pi(rdev); 2636 PP_SIslands_CacConfig *cac_tables = NULL; 2637 u16 vddc_max, vddc_min, vddc_step; 2638 u16 t0, t_step; 2639 u32 load_line_slope, reg; 2640 int ret = 0; 2641 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2642 2643 if (ni_pi->enable_cac == false) 2644 return 0; 2645 2646 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2647 if (!cac_tables) 2648 return -ENOMEM; 2649 2650 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2651 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2652 WREG32(CG_CAC_CTRL, reg); 2653 2654 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2655 si_pi->dyn_powertune_data.dc_pwr_value = 2656 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2657 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2658 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2659 2660 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2661 2662 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2663 if (ret) 2664 goto done_free; 2665 2666 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2667 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2668 t_step = 4; 2669 t0 = 60; 2670 2671 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2672 ret = si_init_dte_leakage_table(rdev, cac_tables, 2673 vddc_max, vddc_min, vddc_step, 2674 t0, t_step); 2675 else 2676 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2677 vddc_max, vddc_min, vddc_step); 2678 if (ret) 2679 goto done_free; 2680 2681 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2682 2683 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2684 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2685 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2686 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2687 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2688 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2689 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2690 cac_tables->calculation_repeats = cpu_to_be32(2); 2691 cac_tables->dc_cac = cpu_to_be32(0); 2692 cac_tables->log2_PG_LKG_SCALE = 12; 2693 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2694 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2695 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2696 2697 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2698 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2699 2700 if (ret) 2701 goto done_free; 2702 2703 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2704 2705 done_free: 2706 if (ret) { 2707 ni_pi->enable_cac = false; 2708 ni_pi->enable_power_containment = false; 2709 } 2710 2711 kfree(cac_tables); 2712 2713 return 0; 2714 } 2715 2716 static int si_program_cac_config_registers(struct radeon_device *rdev, 2717 const struct si_cac_config_reg *cac_config_regs) 2718 { 2719 const struct si_cac_config_reg *config_regs = cac_config_regs; 2720 u32 data = 0, offset; 2721 2722 if (!config_regs) 2723 return -EINVAL; 2724 2725 while (config_regs->offset != 0xFFFFFFFF) { 2726 switch (config_regs->type) { 2727 case SISLANDS_CACCONFIG_CGIND: 2728 offset = SMC_CG_IND_START + config_regs->offset; 2729 if (offset < SMC_CG_IND_END) 2730 data = RREG32_SMC(offset); 2731 break; 2732 default: 2733 data = RREG32(config_regs->offset << 2); 2734 break; 2735 } 2736 2737 data &= ~config_regs->mask; 2738 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2739 2740 switch (config_regs->type) { 2741 case SISLANDS_CACCONFIG_CGIND: 2742 offset = SMC_CG_IND_START + config_regs->offset; 2743 if (offset < SMC_CG_IND_END) 2744 WREG32_SMC(offset, data); 2745 break; 2746 default: 2747 WREG32(config_regs->offset << 2, data); 2748 break; 2749 } 2750 config_regs++; 2751 } 2752 return 0; 2753 } 2754 2755 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2756 { 2757 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2758 struct si_power_info *si_pi = si_get_pi(rdev); 2759 int ret; 2760 2761 if ((ni_pi->enable_cac == false) || 2762 (ni_pi->cac_configuration_required == false)) 2763 return 0; 2764 2765 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2766 if (ret) 2767 return ret; 2768 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2769 if (ret) 2770 return ret; 2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2772 if (ret) 2773 return ret; 2774 2775 return 0; 2776 } 2777 2778 static int si_enable_smc_cac(struct radeon_device *rdev, 2779 struct radeon_ps *radeon_new_state, 2780 bool enable) 2781 { 2782 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2783 struct si_power_info *si_pi = si_get_pi(rdev); 2784 PPSMC_Result smc_result; 2785 int ret = 0; 2786 2787 if (ni_pi->enable_cac) { 2788 if (enable) { 2789 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2790 if (ni_pi->support_cac_long_term_average) { 2791 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2792 if (smc_result != PPSMC_Result_OK) 2793 ni_pi->support_cac_long_term_average = false; 2794 } 2795 2796 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2797 if (smc_result != PPSMC_Result_OK) { 2798 ret = -EINVAL; 2799 ni_pi->cac_enabled = false; 2800 } else { 2801 ni_pi->cac_enabled = true; 2802 } 2803 2804 if (si_pi->enable_dte) { 2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2806 if (smc_result != PPSMC_Result_OK) 2807 ret = -EINVAL; 2808 } 2809 } 2810 } else if (ni_pi->cac_enabled) { 2811 if (si_pi->enable_dte) 2812 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2813 2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2815 2816 ni_pi->cac_enabled = false; 2817 2818 if (ni_pi->support_cac_long_term_average) 2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2820 } 2821 } 2822 return ret; 2823 } 2824 2825 static int si_init_smc_spll_table(struct radeon_device *rdev) 2826 { 2827 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2828 struct si_power_info *si_pi = si_get_pi(rdev); 2829 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2830 SISLANDS_SMC_SCLK_VALUE sclk_params; 2831 u32 fb_div, p_div; 2832 u32 clk_s, clk_v; 2833 u32 sclk = 0; 2834 int ret = 0; 2835 u32 tmp; 2836 int i; 2837 2838 if (si_pi->spll_table_start == 0) 2839 return -EINVAL; 2840 2841 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2842 if (spll_table == NULL) 2843 return -ENOMEM; 2844 2845 for (i = 0; i < 256; i++) { 2846 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2847 if (ret) 2848 break; 2849 2850 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2851 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2852 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2853 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2854 2855 fb_div &= ~0x00001FFF; 2856 fb_div >>= 1; 2857 clk_v >>= 6; 2858 2859 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2860 ret = -EINVAL; 2861 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2862 ret = -EINVAL; 2863 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2864 ret = -EINVAL; 2865 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2866 ret = -EINVAL; 2867 2868 if (ret) 2869 break; 2870 2871 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2872 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2873 spll_table->freq[i] = cpu_to_be32(tmp); 2874 2875 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2876 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2877 spll_table->ss[i] = cpu_to_be32(tmp); 2878 2879 sclk += 512; 2880 } 2881 2882 2883 if (!ret) 2884 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2885 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2886 si_pi->sram_end); 2887 2888 if (ret) 2889 ni_pi->enable_power_containment = false; 2890 2891 kfree(spll_table); 2892 2893 return ret; 2894 } 2895 2896 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2897 u16 vce_voltage) 2898 { 2899 u16 highest_leakage = 0; 2900 struct si_power_info *si_pi = si_get_pi(rdev); 2901 int i; 2902 2903 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2904 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2905 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2906 } 2907 2908 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2909 return highest_leakage; 2910 2911 return vce_voltage; 2912 } 2913 2914 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2915 u32 evclk, u32 ecclk, u16 *voltage) 2916 { 2917 u32 i; 2918 int ret = -EINVAL; 2919 struct radeon_vce_clock_voltage_dependency_table *table = 2920 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2921 2922 if (((evclk == 0) && (ecclk == 0)) || 2923 (table && (table->count == 0))) { 2924 *voltage = 0; 2925 return 0; 2926 } 2927 2928 for (i = 0; i < table->count; i++) { 2929 if ((evclk <= table->entries[i].evclk) && 2930 (ecclk <= table->entries[i].ecclk)) { 2931 *voltage = table->entries[i].v; 2932 ret = 0; 2933 break; 2934 } 2935 } 2936 2937 /* if no match return the highest voltage */ 2938 if (ret) 2939 *voltage = table->entries[table->count - 1].v; 2940 2941 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2942 2943 return ret; 2944 } 2945 2946 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2947 struct radeon_ps *rps) 2948 { 2949 struct ni_ps *ps = ni_get_ps(rps); 2950 struct radeon_clock_and_voltage_limits *max_limits; 2951 bool disable_mclk_switching = false; 2952 bool disable_sclk_switching = false; 2953 u32 mclk, sclk; 2954 u16 vddc, vddci, min_vce_voltage = 0; 2955 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2956 u32 max_sclk = 0, max_mclk = 0; 2957 int i; 2958 2959 if (rdev->family == CHIP_HAINAN) { 2960 if ((rdev->pdev->revision == 0x81) || 2961 (rdev->pdev->revision == 0xC3) || 2962 (rdev->pdev->device == 0x6664) || 2963 (rdev->pdev->device == 0x6665) || 2964 (rdev->pdev->device == 0x6667)) { 2965 max_sclk = 75000; 2966 } 2967 if ((rdev->pdev->revision == 0xC3) || 2968 (rdev->pdev->device == 0x6665)) { 2969 max_sclk = 60000; 2970 max_mclk = 80000; 2971 } 2972 } else if (rdev->family == CHIP_OLAND) { 2973 if ((rdev->pdev->revision == 0xC7) || 2974 (rdev->pdev->revision == 0x80) || 2975 (rdev->pdev->revision == 0x81) || 2976 (rdev->pdev->revision == 0x83) || 2977 (rdev->pdev->revision == 0x87) || 2978 (rdev->pdev->device == 0x6604) || 2979 (rdev->pdev->device == 0x6605)) { 2980 max_sclk = 75000; 2981 } 2982 } 2983 2984 if (rps->vce_active) { 2985 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2986 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2987 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 2988 &min_vce_voltage); 2989 } else { 2990 rps->evclk = 0; 2991 rps->ecclk = 0; 2992 } 2993 2994 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2995 ni_dpm_vblank_too_short(rdev)) 2996 disable_mclk_switching = true; 2997 2998 if (rps->vclk || rps->dclk) { 2999 disable_mclk_switching = true; 3000 disable_sclk_switching = true; 3001 } 3002 3003 if (rdev->pm.dpm.ac_power) 3004 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3005 else 3006 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3007 3008 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3009 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3010 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3011 } 3012 if (rdev->pm.dpm.ac_power == false) { 3013 for (i = 0; i < ps->performance_level_count; i++) { 3014 if (ps->performance_levels[i].mclk > max_limits->mclk) 3015 ps->performance_levels[i].mclk = max_limits->mclk; 3016 if (ps->performance_levels[i].sclk > max_limits->sclk) 3017 ps->performance_levels[i].sclk = max_limits->sclk; 3018 if (ps->performance_levels[i].vddc > max_limits->vddc) 3019 ps->performance_levels[i].vddc = max_limits->vddc; 3020 if (ps->performance_levels[i].vddci > max_limits->vddci) 3021 ps->performance_levels[i].vddci = max_limits->vddci; 3022 } 3023 } 3024 3025 /* limit clocks to max supported clocks based on voltage dependency tables */ 3026 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3027 &max_sclk_vddc); 3028 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3029 &max_mclk_vddci); 3030 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3031 &max_mclk_vddc); 3032 3033 for (i = 0; i < ps->performance_level_count; i++) { 3034 if (max_sclk_vddc) { 3035 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3036 ps->performance_levels[i].sclk = max_sclk_vddc; 3037 } 3038 if (max_mclk_vddci) { 3039 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3040 ps->performance_levels[i].mclk = max_mclk_vddci; 3041 } 3042 if (max_mclk_vddc) { 3043 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3044 ps->performance_levels[i].mclk = max_mclk_vddc; 3045 } 3046 if (max_mclk) { 3047 if (ps->performance_levels[i].mclk > max_mclk) 3048 ps->performance_levels[i].mclk = max_mclk; 3049 } 3050 if (max_sclk) { 3051 if (ps->performance_levels[i].sclk > max_sclk) 3052 ps->performance_levels[i].sclk = max_sclk; 3053 } 3054 } 3055 3056 /* XXX validate the min clocks required for display */ 3057 3058 if (disable_mclk_switching) { 3059 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3060 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3061 } else { 3062 mclk = ps->performance_levels[0].mclk; 3063 vddci = ps->performance_levels[0].vddci; 3064 } 3065 3066 if (disable_sclk_switching) { 3067 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3068 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3069 } else { 3070 sclk = ps->performance_levels[0].sclk; 3071 vddc = ps->performance_levels[0].vddc; 3072 } 3073 3074 if (rps->vce_active) { 3075 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3076 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3077 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3078 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3079 } 3080 3081 /* adjusted low state */ 3082 ps->performance_levels[0].sclk = sclk; 3083 ps->performance_levels[0].mclk = mclk; 3084 ps->performance_levels[0].vddc = vddc; 3085 ps->performance_levels[0].vddci = vddci; 3086 3087 if (disable_sclk_switching) { 3088 sclk = ps->performance_levels[0].sclk; 3089 for (i = 1; i < ps->performance_level_count; i++) { 3090 if (sclk < ps->performance_levels[i].sclk) 3091 sclk = ps->performance_levels[i].sclk; 3092 } 3093 for (i = 0; i < ps->performance_level_count; i++) { 3094 ps->performance_levels[i].sclk = sclk; 3095 ps->performance_levels[i].vddc = vddc; 3096 } 3097 } else { 3098 for (i = 1; i < ps->performance_level_count; i++) { 3099 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3100 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3101 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3102 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3103 } 3104 } 3105 3106 if (disable_mclk_switching) { 3107 mclk = ps->performance_levels[0].mclk; 3108 for (i = 1; i < ps->performance_level_count; i++) { 3109 if (mclk < ps->performance_levels[i].mclk) 3110 mclk = ps->performance_levels[i].mclk; 3111 } 3112 for (i = 0; i < ps->performance_level_count; i++) { 3113 ps->performance_levels[i].mclk = mclk; 3114 ps->performance_levels[i].vddci = vddci; 3115 } 3116 } else { 3117 for (i = 1; i < ps->performance_level_count; i++) { 3118 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3119 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3120 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3121 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3122 } 3123 } 3124 3125 for (i = 0; i < ps->performance_level_count; i++) 3126 btc_adjust_clock_combinations(rdev, max_limits, 3127 &ps->performance_levels[i]); 3128 3129 for (i = 0; i < ps->performance_level_count; i++) { 3130 if (ps->performance_levels[i].vddc < min_vce_voltage) 3131 ps->performance_levels[i].vddc = min_vce_voltage; 3132 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3133 ps->performance_levels[i].sclk, 3134 max_limits->vddc, &ps->performance_levels[i].vddc); 3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3136 ps->performance_levels[i].mclk, 3137 max_limits->vddci, &ps->performance_levels[i].vddci); 3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3139 ps->performance_levels[i].mclk, 3140 max_limits->vddc, &ps->performance_levels[i].vddc); 3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3142 rdev->clock.current_dispclk, 3143 max_limits->vddc, &ps->performance_levels[i].vddc); 3144 } 3145 3146 for (i = 0; i < ps->performance_level_count; i++) { 3147 btc_apply_voltage_delta_rules(rdev, 3148 max_limits->vddc, max_limits->vddci, 3149 &ps->performance_levels[i].vddc, 3150 &ps->performance_levels[i].vddci); 3151 } 3152 3153 ps->dc_compatible = true; 3154 for (i = 0; i < ps->performance_level_count; i++) { 3155 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3156 ps->dc_compatible = false; 3157 } 3158 } 3159 3160 #if 0 3161 static int si_read_smc_soft_register(struct radeon_device *rdev, 3162 u16 reg_offset, u32 *value) 3163 { 3164 struct si_power_info *si_pi = si_get_pi(rdev); 3165 3166 return si_read_smc_sram_dword(rdev, 3167 si_pi->soft_regs_start + reg_offset, value, 3168 si_pi->sram_end); 3169 } 3170 #endif 3171 3172 static int si_write_smc_soft_register(struct radeon_device *rdev, 3173 u16 reg_offset, u32 value) 3174 { 3175 struct si_power_info *si_pi = si_get_pi(rdev); 3176 3177 return si_write_smc_sram_dword(rdev, 3178 si_pi->soft_regs_start + reg_offset, 3179 value, si_pi->sram_end); 3180 } 3181 3182 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3183 { 3184 bool ret = false; 3185 u32 tmp, width, row, column, bank, density; 3186 bool is_memory_gddr5, is_special; 3187 3188 tmp = RREG32(MC_SEQ_MISC0); 3189 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3190 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3191 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3192 3193 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3194 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3195 3196 tmp = RREG32(MC_ARB_RAMCFG); 3197 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3198 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3199 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3200 3201 density = (1 << (row + column - 20 + bank)) * width; 3202 3203 if ((rdev->pdev->device == 0x6819) && 3204 is_memory_gddr5 && is_special && (density == 0x400)) 3205 ret = true; 3206 3207 return ret; 3208 } 3209 3210 static void si_get_leakage_vddc(struct radeon_device *rdev) 3211 { 3212 struct si_power_info *si_pi = si_get_pi(rdev); 3213 u16 vddc, count = 0; 3214 int i, ret; 3215 3216 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3217 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3218 3219 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3220 si_pi->leakage_voltage.entries[count].voltage = vddc; 3221 si_pi->leakage_voltage.entries[count].leakage_index = 3222 SISLANDS_LEAKAGE_INDEX0 + i; 3223 count++; 3224 } 3225 } 3226 si_pi->leakage_voltage.count = count; 3227 } 3228 3229 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3230 u32 index, u16 *leakage_voltage) 3231 { 3232 struct si_power_info *si_pi = si_get_pi(rdev); 3233 int i; 3234 3235 if (leakage_voltage == NULL) 3236 return -EINVAL; 3237 3238 if ((index & 0xff00) != 0xff00) 3239 return -EINVAL; 3240 3241 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3242 return -EINVAL; 3243 3244 if (index < SISLANDS_LEAKAGE_INDEX0) 3245 return -EINVAL; 3246 3247 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3248 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3249 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3250 return 0; 3251 } 3252 } 3253 return -EAGAIN; 3254 } 3255 3256 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3257 { 3258 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3259 bool want_thermal_protection; 3260 enum radeon_dpm_event_src dpm_event_src; 3261 3262 switch (sources) { 3263 case 0: 3264 default: 3265 want_thermal_protection = false; 3266 break; 3267 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3268 want_thermal_protection = true; 3269 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3270 break; 3271 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3272 want_thermal_protection = true; 3273 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3274 break; 3275 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3276 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3277 want_thermal_protection = true; 3278 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3279 break; 3280 } 3281 3282 if (want_thermal_protection) { 3283 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3284 if (pi->thermal_protection) 3285 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3286 } else { 3287 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3288 } 3289 } 3290 3291 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3292 enum radeon_dpm_auto_throttle_src source, 3293 bool enable) 3294 { 3295 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3296 3297 if (enable) { 3298 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3299 pi->active_auto_throttle_sources |= 1 << source; 3300 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3301 } 3302 } else { 3303 if (pi->active_auto_throttle_sources & (1 << source)) { 3304 pi->active_auto_throttle_sources &= ~(1 << source); 3305 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3306 } 3307 } 3308 } 3309 3310 static void si_start_dpm(struct radeon_device *rdev) 3311 { 3312 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3313 } 3314 3315 static void si_stop_dpm(struct radeon_device *rdev) 3316 { 3317 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3318 } 3319 3320 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3321 { 3322 if (enable) 3323 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3324 else 3325 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3326 3327 } 3328 3329 #if 0 3330 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3331 u32 thermal_level) 3332 { 3333 PPSMC_Result ret; 3334 3335 if (thermal_level == 0) { 3336 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3337 if (ret == PPSMC_Result_OK) 3338 return 0; 3339 else 3340 return -EINVAL; 3341 } 3342 return 0; 3343 } 3344 3345 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3346 { 3347 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3348 } 3349 #endif 3350 3351 #if 0 3352 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3353 { 3354 if (ac_power) 3355 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3356 0 : -EINVAL; 3357 3358 return 0; 3359 } 3360 #endif 3361 3362 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3363 PPSMC_Msg msg, u32 parameter) 3364 { 3365 WREG32(SMC_SCRATCH0, parameter); 3366 return si_send_msg_to_smc(rdev, msg); 3367 } 3368 3369 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3370 { 3371 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3372 return -EINVAL; 3373 3374 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3375 0 : -EINVAL; 3376 } 3377 3378 int si_dpm_force_performance_level(struct radeon_device *rdev, 3379 enum radeon_dpm_forced_level level) 3380 { 3381 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3382 struct ni_ps *ps = ni_get_ps(rps); 3383 u32 levels = ps->performance_level_count; 3384 3385 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3386 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3387 return -EINVAL; 3388 3389 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3390 return -EINVAL; 3391 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3393 return -EINVAL; 3394 3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3396 return -EINVAL; 3397 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3399 return -EINVAL; 3400 3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3402 return -EINVAL; 3403 } 3404 3405 rdev->pm.dpm.forced_level = level; 3406 3407 return 0; 3408 } 3409 3410 #if 0 3411 static int si_set_boot_state(struct radeon_device *rdev) 3412 { 3413 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3414 0 : -EINVAL; 3415 } 3416 #endif 3417 3418 static int si_set_sw_state(struct radeon_device *rdev) 3419 { 3420 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3421 0 : -EINVAL; 3422 } 3423 3424 static int si_halt_smc(struct radeon_device *rdev) 3425 { 3426 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3427 return -EINVAL; 3428 3429 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3430 0 : -EINVAL; 3431 } 3432 3433 static int si_resume_smc(struct radeon_device *rdev) 3434 { 3435 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3436 return -EINVAL; 3437 3438 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3439 0 : -EINVAL; 3440 } 3441 3442 static void si_dpm_start_smc(struct radeon_device *rdev) 3443 { 3444 si_program_jump_on_start(rdev); 3445 si_start_smc(rdev); 3446 si_start_smc_clock(rdev); 3447 } 3448 3449 static void si_dpm_stop_smc(struct radeon_device *rdev) 3450 { 3451 si_reset_smc(rdev); 3452 si_stop_smc_clock(rdev); 3453 } 3454 3455 static int si_process_firmware_header(struct radeon_device *rdev) 3456 { 3457 struct si_power_info *si_pi = si_get_pi(rdev); 3458 u32 tmp; 3459 int ret; 3460 3461 ret = si_read_smc_sram_dword(rdev, 3462 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3463 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3464 &tmp, si_pi->sram_end); 3465 if (ret) 3466 return ret; 3467 3468 si_pi->state_table_start = tmp; 3469 3470 ret = si_read_smc_sram_dword(rdev, 3471 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3472 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3473 &tmp, si_pi->sram_end); 3474 if (ret) 3475 return ret; 3476 3477 si_pi->soft_regs_start = tmp; 3478 3479 ret = si_read_smc_sram_dword(rdev, 3480 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3481 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3482 &tmp, si_pi->sram_end); 3483 if (ret) 3484 return ret; 3485 3486 si_pi->mc_reg_table_start = tmp; 3487 3488 ret = si_read_smc_sram_dword(rdev, 3489 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3490 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3491 &tmp, si_pi->sram_end); 3492 if (ret) 3493 return ret; 3494 3495 si_pi->fan_table_start = tmp; 3496 3497 ret = si_read_smc_sram_dword(rdev, 3498 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3499 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3500 &tmp, si_pi->sram_end); 3501 if (ret) 3502 return ret; 3503 3504 si_pi->arb_table_start = tmp; 3505 3506 ret = si_read_smc_sram_dword(rdev, 3507 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3508 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3509 &tmp, si_pi->sram_end); 3510 if (ret) 3511 return ret; 3512 3513 si_pi->cac_table_start = tmp; 3514 3515 ret = si_read_smc_sram_dword(rdev, 3516 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3517 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3518 &tmp, si_pi->sram_end); 3519 if (ret) 3520 return ret; 3521 3522 si_pi->dte_table_start = tmp; 3523 3524 ret = si_read_smc_sram_dword(rdev, 3525 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3526 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3527 &tmp, si_pi->sram_end); 3528 if (ret) 3529 return ret; 3530 3531 si_pi->spll_table_start = tmp; 3532 3533 ret = si_read_smc_sram_dword(rdev, 3534 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3535 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3536 &tmp, si_pi->sram_end); 3537 if (ret) 3538 return ret; 3539 3540 si_pi->papm_cfg_table_start = tmp; 3541 3542 return ret; 3543 } 3544 3545 static void si_read_clock_registers(struct radeon_device *rdev) 3546 { 3547 struct si_power_info *si_pi = si_get_pi(rdev); 3548 3549 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3550 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3551 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3552 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3553 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3554 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3555 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3556 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3557 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3558 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3559 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3560 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3561 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3562 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3563 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3564 } 3565 3566 static void si_enable_thermal_protection(struct radeon_device *rdev, 3567 bool enable) 3568 { 3569 if (enable) 3570 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3571 else 3572 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3573 } 3574 3575 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3576 { 3577 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3578 } 3579 3580 #if 0 3581 static int si_enter_ulp_state(struct radeon_device *rdev) 3582 { 3583 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3584 3585 udelay(25000); 3586 3587 return 0; 3588 } 3589 3590 static int si_exit_ulp_state(struct radeon_device *rdev) 3591 { 3592 int i; 3593 3594 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3595 3596 udelay(7000); 3597 3598 for (i = 0; i < rdev->usec_timeout; i++) { 3599 if (RREG32(SMC_RESP_0) == 1) 3600 break; 3601 udelay(1000); 3602 } 3603 3604 return 0; 3605 } 3606 #endif 3607 3608 static int si_notify_smc_display_change(struct radeon_device *rdev, 3609 bool has_display) 3610 { 3611 PPSMC_Msg msg = has_display ? 3612 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3613 3614 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3615 0 : -EINVAL; 3616 } 3617 3618 static void si_program_response_times(struct radeon_device *rdev) 3619 { 3620 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 3621 u32 vddc_dly, acpi_dly, vbi_dly; 3622 u32 reference_clock; 3623 3624 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3625 3626 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3627 3628 if (voltage_response_time == 0) 3629 voltage_response_time = 1000; 3630 3631 acpi_delay_time = 15000; 3632 vbi_time_out = 100000; 3633 3634 reference_clock = radeon_get_xclk(rdev); 3635 3636 vddc_dly = (voltage_response_time * reference_clock) / 100; 3637 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3638 vbi_dly = (vbi_time_out * reference_clock) / 100; 3639 3640 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3641 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3642 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3644 } 3645 3646 static void si_program_ds_registers(struct radeon_device *rdev) 3647 { 3648 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3649 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3650 3651 if (eg_pi->sclk_deep_sleep) { 3652 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3653 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3654 ~AUTOSCALE_ON_SS_CLEAR); 3655 } 3656 } 3657 3658 static void si_program_display_gap(struct radeon_device *rdev) 3659 { 3660 u32 tmp, pipe; 3661 int i; 3662 3663 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3664 if (rdev->pm.dpm.new_active_crtc_count > 0) 3665 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3666 else 3667 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3668 3669 if (rdev->pm.dpm.new_active_crtc_count > 1) 3670 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3671 else 3672 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3673 3674 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3675 3676 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3677 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3678 3679 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3680 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3681 /* find the first active crtc */ 3682 for (i = 0; i < rdev->num_crtc; i++) { 3683 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3684 break; 3685 } 3686 if (i == rdev->num_crtc) 3687 pipe = 0; 3688 else 3689 pipe = i; 3690 3691 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3692 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3693 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3694 } 3695 3696 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3697 * This can be a problem on PowerXpress systems or if you want to use the card 3698 * for offscreen rendering or compute if there are no crtcs enabled. 3699 */ 3700 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3701 } 3702 3703 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3704 { 3705 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3706 3707 if (enable) { 3708 if (pi->sclk_ss) 3709 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3710 } else { 3711 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3712 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3713 } 3714 } 3715 3716 static void si_setup_bsp(struct radeon_device *rdev) 3717 { 3718 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3719 u32 xclk = radeon_get_xclk(rdev); 3720 3721 r600_calculate_u_and_p(pi->asi, 3722 xclk, 3723 16, 3724 &pi->bsp, 3725 &pi->bsu); 3726 3727 r600_calculate_u_and_p(pi->pasi, 3728 xclk, 3729 16, 3730 &pi->pbsp, 3731 &pi->pbsu); 3732 3733 3734 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3735 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3736 3737 WREG32(CG_BSP, pi->dsp); 3738 } 3739 3740 static void si_program_git(struct radeon_device *rdev) 3741 { 3742 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3743 } 3744 3745 static void si_program_tp(struct radeon_device *rdev) 3746 { 3747 int i; 3748 enum r600_td td = R600_TD_DFLT; 3749 3750 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3751 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3752 3753 if (td == R600_TD_AUTO) 3754 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3755 else 3756 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3757 3758 if (td == R600_TD_UP) 3759 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3760 3761 if (td == R600_TD_DOWN) 3762 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3763 } 3764 3765 static void si_program_tpp(struct radeon_device *rdev) 3766 { 3767 WREG32(CG_TPC, R600_TPC_DFLT); 3768 } 3769 3770 static void si_program_sstp(struct radeon_device *rdev) 3771 { 3772 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3773 } 3774 3775 static void si_enable_display_gap(struct radeon_device *rdev) 3776 { 3777 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3778 3779 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3780 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3781 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3782 3783 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3784 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3785 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3786 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3787 } 3788 3789 static void si_program_vc(struct radeon_device *rdev) 3790 { 3791 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3792 3793 WREG32(CG_FTV, pi->vrc); 3794 } 3795 3796 static void si_clear_vc(struct radeon_device *rdev) 3797 { 3798 WREG32(CG_FTV, 0); 3799 } 3800 3801 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3802 { 3803 u8 mc_para_index; 3804 3805 if (memory_clock < 10000) 3806 mc_para_index = 0; 3807 else if (memory_clock >= 80000) 3808 mc_para_index = 0x0f; 3809 else 3810 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3811 return mc_para_index; 3812 } 3813 3814 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3815 { 3816 u8 mc_para_index; 3817 3818 if (strobe_mode) { 3819 if (memory_clock < 12500) 3820 mc_para_index = 0x00; 3821 else if (memory_clock > 47500) 3822 mc_para_index = 0x0f; 3823 else 3824 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3825 } else { 3826 if (memory_clock < 65000) 3827 mc_para_index = 0x00; 3828 else if (memory_clock > 135000) 3829 mc_para_index = 0x0f; 3830 else 3831 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3832 } 3833 return mc_para_index; 3834 } 3835 3836 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3837 { 3838 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3839 bool strobe_mode = false; 3840 u8 result = 0; 3841 3842 if (mclk <= pi->mclk_strobe_mode_threshold) 3843 strobe_mode = true; 3844 3845 if (pi->mem_gddr5) 3846 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3847 else 3848 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3849 3850 if (strobe_mode) 3851 result |= SISLANDS_SMC_STROBE_ENABLE; 3852 3853 return result; 3854 } 3855 3856 static int si_upload_firmware(struct radeon_device *rdev) 3857 { 3858 struct si_power_info *si_pi = si_get_pi(rdev); 3859 int ret; 3860 3861 si_reset_smc(rdev); 3862 si_stop_smc_clock(rdev); 3863 3864 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3865 3866 return ret; 3867 } 3868 3869 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3870 const struct atom_voltage_table *table, 3871 const struct radeon_phase_shedding_limits_table *limits) 3872 { 3873 u32 data, num_bits, num_levels; 3874 3875 if ((table == NULL) || (limits == NULL)) 3876 return false; 3877 3878 data = table->mask_low; 3879 3880 num_bits = hweight32(data); 3881 3882 if (num_bits == 0) 3883 return false; 3884 3885 num_levels = (1 << num_bits); 3886 3887 if (table->count != num_levels) 3888 return false; 3889 3890 if (limits->count != (num_levels - 1)) 3891 return false; 3892 3893 return true; 3894 } 3895 3896 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3897 u32 max_voltage_steps, 3898 struct atom_voltage_table *voltage_table) 3899 { 3900 unsigned int i, diff; 3901 3902 if (voltage_table->count <= max_voltage_steps) 3903 return; 3904 3905 diff = voltage_table->count - max_voltage_steps; 3906 3907 for (i= 0; i < max_voltage_steps; i++) 3908 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3909 3910 voltage_table->count = max_voltage_steps; 3911 } 3912 3913 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3914 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3915 struct atom_voltage_table *voltage_table) 3916 { 3917 u32 i; 3918 3919 if (voltage_dependency_table == NULL) 3920 return -EINVAL; 3921 3922 voltage_table->mask_low = 0; 3923 voltage_table->phase_delay = 0; 3924 3925 voltage_table->count = voltage_dependency_table->count; 3926 for (i = 0; i < voltage_table->count; i++) { 3927 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3928 voltage_table->entries[i].smio_low = 0; 3929 } 3930 3931 return 0; 3932 } 3933 3934 static int si_construct_voltage_tables(struct radeon_device *rdev) 3935 { 3936 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3937 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3938 struct si_power_info *si_pi = si_get_pi(rdev); 3939 int ret; 3940 3941 if (pi->voltage_control) { 3942 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3943 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3944 if (ret) 3945 return ret; 3946 3947 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3948 si_trim_voltage_table_to_fit_state_table(rdev, 3949 SISLANDS_MAX_NO_VREG_STEPS, 3950 &eg_pi->vddc_voltage_table); 3951 } else if (si_pi->voltage_control_svi2) { 3952 ret = si_get_svi2_voltage_table(rdev, 3953 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3954 &eg_pi->vddc_voltage_table); 3955 if (ret) 3956 return ret; 3957 } else { 3958 return -EINVAL; 3959 } 3960 3961 if (eg_pi->vddci_control) { 3962 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3963 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3964 if (ret) 3965 return ret; 3966 3967 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3968 si_trim_voltage_table_to_fit_state_table(rdev, 3969 SISLANDS_MAX_NO_VREG_STEPS, 3970 &eg_pi->vddci_voltage_table); 3971 } 3972 if (si_pi->vddci_control_svi2) { 3973 ret = si_get_svi2_voltage_table(rdev, 3974 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3975 &eg_pi->vddci_voltage_table); 3976 if (ret) 3977 return ret; 3978 } 3979 3980 if (pi->mvdd_control) { 3981 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3982 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3983 3984 if (ret) { 3985 pi->mvdd_control = false; 3986 return ret; 3987 } 3988 3989 if (si_pi->mvdd_voltage_table.count == 0) { 3990 pi->mvdd_control = false; 3991 return -EINVAL; 3992 } 3993 3994 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3995 si_trim_voltage_table_to_fit_state_table(rdev, 3996 SISLANDS_MAX_NO_VREG_STEPS, 3997 &si_pi->mvdd_voltage_table); 3998 } 3999 4000 if (si_pi->vddc_phase_shed_control) { 4001 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4002 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4003 if (ret) 4004 si_pi->vddc_phase_shed_control = false; 4005 4006 if ((si_pi->vddc_phase_shed_table.count == 0) || 4007 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4008 si_pi->vddc_phase_shed_control = false; 4009 } 4010 4011 return 0; 4012 } 4013 4014 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4015 const struct atom_voltage_table *voltage_table, 4016 SISLANDS_SMC_STATETABLE *table) 4017 { 4018 unsigned int i; 4019 4020 for (i = 0; i < voltage_table->count; i++) 4021 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4022 } 4023 4024 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4025 SISLANDS_SMC_STATETABLE *table) 4026 { 4027 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4028 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4029 struct si_power_info *si_pi = si_get_pi(rdev); 4030 u8 i; 4031 4032 if (si_pi->voltage_control_svi2) { 4033 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4034 si_pi->svc_gpio_id); 4035 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4036 si_pi->svd_gpio_id); 4037 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4038 2); 4039 } else { 4040 if (eg_pi->vddc_voltage_table.count) { 4041 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4042 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4043 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4044 4045 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4046 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4047 table->maxVDDCIndexInPPTable = i; 4048 break; 4049 } 4050 } 4051 } 4052 4053 if (eg_pi->vddci_voltage_table.count) { 4054 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4055 4056 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4057 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4058 } 4059 4060 4061 if (si_pi->mvdd_voltage_table.count) { 4062 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4063 4064 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4065 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4066 } 4067 4068 if (si_pi->vddc_phase_shed_control) { 4069 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4070 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4071 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4072 4073 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4074 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4075 4076 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4077 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4078 } else { 4079 si_pi->vddc_phase_shed_control = false; 4080 } 4081 } 4082 } 4083 4084 return 0; 4085 } 4086 4087 static int si_populate_voltage_value(struct radeon_device *rdev, 4088 const struct atom_voltage_table *table, 4089 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4090 { 4091 unsigned int i; 4092 4093 for (i = 0; i < table->count; i++) { 4094 if (value <= table->entries[i].value) { 4095 voltage->index = (u8)i; 4096 voltage->value = cpu_to_be16(table->entries[i].value); 4097 break; 4098 } 4099 } 4100 4101 if (i >= table->count) 4102 return -EINVAL; 4103 4104 return 0; 4105 } 4106 4107 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4108 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4109 { 4110 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4111 struct si_power_info *si_pi = si_get_pi(rdev); 4112 4113 if (pi->mvdd_control) { 4114 if (mclk <= pi->mvdd_split_frequency) 4115 voltage->index = 0; 4116 else 4117 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4118 4119 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4120 } 4121 return 0; 4122 } 4123 4124 static int si_get_std_voltage_value(struct radeon_device *rdev, 4125 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4126 u16 *std_voltage) 4127 { 4128 u16 v_index; 4129 bool voltage_found = false; 4130 *std_voltage = be16_to_cpu(voltage->value); 4131 4132 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4133 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4134 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4135 return -EINVAL; 4136 4137 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4138 if (be16_to_cpu(voltage->value) == 4139 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4140 voltage_found = true; 4141 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4142 *std_voltage = 4143 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4144 else 4145 *std_voltage = 4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4147 break; 4148 } 4149 } 4150 4151 if (!voltage_found) { 4152 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4153 if (be16_to_cpu(voltage->value) <= 4154 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4155 voltage_found = true; 4156 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4157 *std_voltage = 4158 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4159 else 4160 *std_voltage = 4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4162 break; 4163 } 4164 } 4165 } 4166 } else { 4167 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4168 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4169 } 4170 } 4171 4172 return 0; 4173 } 4174 4175 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4176 u16 value, u8 index, 4177 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4178 { 4179 voltage->index = index; 4180 voltage->value = cpu_to_be16(value); 4181 4182 return 0; 4183 } 4184 4185 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4186 const struct radeon_phase_shedding_limits_table *limits, 4187 u16 voltage, u32 sclk, u32 mclk, 4188 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4189 { 4190 unsigned int i; 4191 4192 for (i = 0; i < limits->count; i++) { 4193 if ((voltage <= limits->entries[i].voltage) && 4194 (sclk <= limits->entries[i].sclk) && 4195 (mclk <= limits->entries[i].mclk)) 4196 break; 4197 } 4198 4199 smc_voltage->phase_settings = (u8)i; 4200 4201 return 0; 4202 } 4203 4204 static int si_init_arb_table_index(struct radeon_device *rdev) 4205 { 4206 struct si_power_info *si_pi = si_get_pi(rdev); 4207 u32 tmp; 4208 int ret; 4209 4210 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4211 if (ret) 4212 return ret; 4213 4214 tmp &= 0x00FFFFFF; 4215 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4216 4217 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4218 } 4219 4220 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4221 { 4222 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4223 } 4224 4225 static int si_reset_to_default(struct radeon_device *rdev) 4226 { 4227 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4228 0 : -EINVAL; 4229 } 4230 4231 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4232 { 4233 struct si_power_info *si_pi = si_get_pi(rdev); 4234 u32 tmp; 4235 int ret; 4236 4237 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4238 &tmp, si_pi->sram_end); 4239 if (ret) 4240 return ret; 4241 4242 tmp = (tmp >> 24) & 0xff; 4243 4244 if (tmp == MC_CG_ARB_FREQ_F0) 4245 return 0; 4246 4247 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4248 } 4249 4250 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4251 u32 engine_clock) 4252 { 4253 u32 dram_rows; 4254 u32 dram_refresh_rate; 4255 u32 mc_arb_rfsh_rate; 4256 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4257 4258 if (tmp >= 4) 4259 dram_rows = 16384; 4260 else 4261 dram_rows = 1 << (tmp + 10); 4262 4263 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4264 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4265 4266 return mc_arb_rfsh_rate; 4267 } 4268 4269 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4270 struct rv7xx_pl *pl, 4271 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4272 { 4273 u32 dram_timing; 4274 u32 dram_timing2; 4275 u32 burst_time; 4276 4277 arb_regs->mc_arb_rfsh_rate = 4278 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4279 4280 radeon_atom_set_engine_dram_timings(rdev, 4281 pl->sclk, 4282 pl->mclk); 4283 4284 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4285 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4286 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4287 4288 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4289 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4290 arb_regs->mc_arb_burst_time = (u8)burst_time; 4291 4292 return 0; 4293 } 4294 4295 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4296 struct radeon_ps *radeon_state, 4297 unsigned int first_arb_set) 4298 { 4299 struct si_power_info *si_pi = si_get_pi(rdev); 4300 struct ni_ps *state = ni_get_ps(radeon_state); 4301 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4302 int i, ret = 0; 4303 4304 for (i = 0; i < state->performance_level_count; i++) { 4305 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4306 if (ret) 4307 break; 4308 ret = si_copy_bytes_to_smc(rdev, 4309 si_pi->arb_table_start + 4310 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4311 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4312 (u8 *)&arb_regs, 4313 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4314 si_pi->sram_end); 4315 if (ret) 4316 break; 4317 } 4318 4319 return ret; 4320 } 4321 4322 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4323 struct radeon_ps *radeon_new_state) 4324 { 4325 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4326 SISLANDS_DRIVER_STATE_ARB_INDEX); 4327 } 4328 4329 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4330 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4331 { 4332 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4333 struct si_power_info *si_pi = si_get_pi(rdev); 4334 4335 if (pi->mvdd_control) 4336 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4337 si_pi->mvdd_bootup_value, voltage); 4338 4339 return 0; 4340 } 4341 4342 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4343 struct radeon_ps *radeon_initial_state, 4344 SISLANDS_SMC_STATETABLE *table) 4345 { 4346 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4347 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4348 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4349 struct si_power_info *si_pi = si_get_pi(rdev); 4350 u32 reg; 4351 int ret; 4352 4353 table->initialState.levels[0].mclk.vDLL_CNTL = 4354 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4355 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4356 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4357 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4358 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4359 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4360 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4361 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4362 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4363 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4364 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4365 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4366 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4367 table->initialState.levels[0].mclk.vMPLL_SS = 4368 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4369 table->initialState.levels[0].mclk.vMPLL_SS2 = 4370 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4371 4372 table->initialState.levels[0].mclk.mclk_value = 4373 cpu_to_be32(initial_state->performance_levels[0].mclk); 4374 4375 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4376 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4377 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4378 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4379 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4380 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4381 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4382 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4383 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4384 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4385 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4386 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4387 4388 table->initialState.levels[0].sclk.sclk_value = 4389 cpu_to_be32(initial_state->performance_levels[0].sclk); 4390 4391 table->initialState.levels[0].arbRefreshState = 4392 SISLANDS_INITIAL_STATE_ARB_INDEX; 4393 4394 table->initialState.levels[0].ACIndex = 0; 4395 4396 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4397 initial_state->performance_levels[0].vddc, 4398 &table->initialState.levels[0].vddc); 4399 4400 if (!ret) { 4401 u16 std_vddc; 4402 4403 ret = si_get_std_voltage_value(rdev, 4404 &table->initialState.levels[0].vddc, 4405 &std_vddc); 4406 if (!ret) 4407 si_populate_std_voltage_value(rdev, std_vddc, 4408 table->initialState.levels[0].vddc.index, 4409 &table->initialState.levels[0].std_vddc); 4410 } 4411 4412 if (eg_pi->vddci_control) 4413 si_populate_voltage_value(rdev, 4414 &eg_pi->vddci_voltage_table, 4415 initial_state->performance_levels[0].vddci, 4416 &table->initialState.levels[0].vddci); 4417 4418 if (si_pi->vddc_phase_shed_control) 4419 si_populate_phase_shedding_value(rdev, 4420 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4421 initial_state->performance_levels[0].vddc, 4422 initial_state->performance_levels[0].sclk, 4423 initial_state->performance_levels[0].mclk, 4424 &table->initialState.levels[0].vddc); 4425 4426 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4427 4428 reg = CG_R(0xffff) | CG_L(0); 4429 table->initialState.levels[0].aT = cpu_to_be32(reg); 4430 4431 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4432 4433 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4434 4435 if (pi->mem_gddr5) { 4436 table->initialState.levels[0].strobeMode = 4437 si_get_strobe_mode_settings(rdev, 4438 initial_state->performance_levels[0].mclk); 4439 4440 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4441 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4442 else 4443 table->initialState.levels[0].mcFlags = 0; 4444 } 4445 4446 table->initialState.levelCount = 1; 4447 4448 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4449 4450 table->initialState.levels[0].dpm2.MaxPS = 0; 4451 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4452 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4453 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4454 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4455 4456 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4457 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4458 4459 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4460 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4461 4462 return 0; 4463 } 4464 4465 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4466 SISLANDS_SMC_STATETABLE *table) 4467 { 4468 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4469 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4470 struct si_power_info *si_pi = si_get_pi(rdev); 4471 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4472 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4473 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4474 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4475 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4476 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4477 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4478 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4479 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4480 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4481 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4482 u32 reg; 4483 int ret; 4484 4485 table->ACPIState = table->initialState; 4486 4487 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4488 4489 if (pi->acpi_vddc) { 4490 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4491 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4492 if (!ret) { 4493 u16 std_vddc; 4494 4495 ret = si_get_std_voltage_value(rdev, 4496 &table->ACPIState.levels[0].vddc, &std_vddc); 4497 if (!ret) 4498 si_populate_std_voltage_value(rdev, std_vddc, 4499 table->ACPIState.levels[0].vddc.index, 4500 &table->ACPIState.levels[0].std_vddc); 4501 } 4502 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4503 4504 if (si_pi->vddc_phase_shed_control) { 4505 si_populate_phase_shedding_value(rdev, 4506 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4507 pi->acpi_vddc, 4508 0, 4509 0, 4510 &table->ACPIState.levels[0].vddc); 4511 } 4512 } else { 4513 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4514 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4515 if (!ret) { 4516 u16 std_vddc; 4517 4518 ret = si_get_std_voltage_value(rdev, 4519 &table->ACPIState.levels[0].vddc, &std_vddc); 4520 4521 if (!ret) 4522 si_populate_std_voltage_value(rdev, std_vddc, 4523 table->ACPIState.levels[0].vddc.index, 4524 &table->ACPIState.levels[0].std_vddc); 4525 } 4526 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4527 si_pi->sys_pcie_mask, 4528 si_pi->boot_pcie_gen, 4529 RADEON_PCIE_GEN1); 4530 4531 if (si_pi->vddc_phase_shed_control) 4532 si_populate_phase_shedding_value(rdev, 4533 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4534 pi->min_vddc_in_table, 4535 0, 4536 0, 4537 &table->ACPIState.levels[0].vddc); 4538 } 4539 4540 if (pi->acpi_vddc) { 4541 if (eg_pi->acpi_vddci) 4542 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4543 eg_pi->acpi_vddci, 4544 &table->ACPIState.levels[0].vddci); 4545 } 4546 4547 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4548 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4549 4550 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4551 4552 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4553 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4554 4555 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4556 cpu_to_be32(dll_cntl); 4557 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4558 cpu_to_be32(mclk_pwrmgt_cntl); 4559 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4560 cpu_to_be32(mpll_ad_func_cntl); 4561 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4562 cpu_to_be32(mpll_dq_func_cntl); 4563 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4564 cpu_to_be32(mpll_func_cntl); 4565 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4566 cpu_to_be32(mpll_func_cntl_1); 4567 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4568 cpu_to_be32(mpll_func_cntl_2); 4569 table->ACPIState.levels[0].mclk.vMPLL_SS = 4570 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4571 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4572 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4573 4574 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4575 cpu_to_be32(spll_func_cntl); 4576 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4577 cpu_to_be32(spll_func_cntl_2); 4578 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4579 cpu_to_be32(spll_func_cntl_3); 4580 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4581 cpu_to_be32(spll_func_cntl_4); 4582 4583 table->ACPIState.levels[0].mclk.mclk_value = 0; 4584 table->ACPIState.levels[0].sclk.sclk_value = 0; 4585 4586 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4587 4588 if (eg_pi->dynamic_ac_timing) 4589 table->ACPIState.levels[0].ACIndex = 0; 4590 4591 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4592 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4593 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4594 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4595 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4596 4597 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4598 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4599 4600 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4601 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4602 4603 return 0; 4604 } 4605 4606 static int si_populate_ulv_state(struct radeon_device *rdev, 4607 SISLANDS_SMC_SWSTATE *state) 4608 { 4609 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4610 struct si_power_info *si_pi = si_get_pi(rdev); 4611 struct si_ulv_param *ulv = &si_pi->ulv; 4612 u32 sclk_in_sr = 1350; /* ??? */ 4613 int ret; 4614 4615 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4616 &state->levels[0]); 4617 if (!ret) { 4618 if (eg_pi->sclk_deep_sleep) { 4619 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4620 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4621 else 4622 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4623 } 4624 if (ulv->one_pcie_lane_in_ulv) 4625 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4626 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4627 state->levels[0].ACIndex = 1; 4628 state->levels[0].std_vddc = state->levels[0].vddc; 4629 state->levelCount = 1; 4630 4631 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4632 } 4633 4634 return ret; 4635 } 4636 4637 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4638 { 4639 struct si_power_info *si_pi = si_get_pi(rdev); 4640 struct si_ulv_param *ulv = &si_pi->ulv; 4641 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4642 int ret; 4643 4644 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4645 &arb_regs); 4646 if (ret) 4647 return ret; 4648 4649 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4650 ulv->volt_change_delay); 4651 4652 ret = si_copy_bytes_to_smc(rdev, 4653 si_pi->arb_table_start + 4654 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4655 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4656 (u8 *)&arb_regs, 4657 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4658 si_pi->sram_end); 4659 4660 return ret; 4661 } 4662 4663 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4664 { 4665 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4666 4667 pi->mvdd_split_frequency = 30000; 4668 } 4669 4670 static int si_init_smc_table(struct radeon_device *rdev) 4671 { 4672 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4673 struct si_power_info *si_pi = si_get_pi(rdev); 4674 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4675 const struct si_ulv_param *ulv = &si_pi->ulv; 4676 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4677 int ret; 4678 u32 lane_width; 4679 u32 vr_hot_gpio; 4680 4681 si_populate_smc_voltage_tables(rdev, table); 4682 4683 switch (rdev->pm.int_thermal_type) { 4684 case THERMAL_TYPE_SI: 4685 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4686 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4687 break; 4688 case THERMAL_TYPE_NONE: 4689 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4690 break; 4691 default: 4692 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4693 break; 4694 } 4695 4696 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4697 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4698 4699 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4700 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4701 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4702 } 4703 4704 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4705 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4706 4707 if (pi->mem_gddr5) 4708 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4709 4710 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4711 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4712 4713 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4714 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4715 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4716 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4717 vr_hot_gpio); 4718 } 4719 4720 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4721 if (ret) 4722 return ret; 4723 4724 ret = si_populate_smc_acpi_state(rdev, table); 4725 if (ret) 4726 return ret; 4727 4728 table->driverState = table->initialState; 4729 4730 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4731 SISLANDS_INITIAL_STATE_ARB_INDEX); 4732 if (ret) 4733 return ret; 4734 4735 if (ulv->supported && ulv->pl.vddc) { 4736 ret = si_populate_ulv_state(rdev, &table->ULVState); 4737 if (ret) 4738 return ret; 4739 4740 ret = si_program_ulv_memory_timing_parameters(rdev); 4741 if (ret) 4742 return ret; 4743 4744 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4745 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4746 4747 lane_width = radeon_get_pcie_lanes(rdev); 4748 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4749 } else { 4750 table->ULVState = table->initialState; 4751 } 4752 4753 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4754 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4755 si_pi->sram_end); 4756 } 4757 4758 static int si_calculate_sclk_params(struct radeon_device *rdev, 4759 u32 engine_clock, 4760 SISLANDS_SMC_SCLK_VALUE *sclk) 4761 { 4762 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4763 struct si_power_info *si_pi = si_get_pi(rdev); 4764 struct atom_clock_dividers dividers; 4765 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4766 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4767 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4768 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4769 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4770 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4771 u64 tmp; 4772 u32 reference_clock = rdev->clock.spll.reference_freq; 4773 u32 reference_divider; 4774 u32 fbdiv; 4775 int ret; 4776 4777 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4778 engine_clock, false, ÷rs); 4779 if (ret) 4780 return ret; 4781 4782 reference_divider = 1 + dividers.ref_div; 4783 4784 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4785 do_div(tmp, reference_clock); 4786 fbdiv = (u32) tmp; 4787 4788 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4789 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4790 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4791 4792 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4793 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4794 4795 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4796 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4797 spll_func_cntl_3 |= SPLL_DITHEN; 4798 4799 if (pi->sclk_ss) { 4800 struct radeon_atom_ss ss; 4801 u32 vco_freq = engine_clock * dividers.post_div; 4802 4803 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4804 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4805 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4806 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4807 4808 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4809 cg_spll_spread_spectrum |= CLK_S(clk_s); 4810 cg_spll_spread_spectrum |= SSEN; 4811 4812 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4813 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4814 } 4815 } 4816 4817 sclk->sclk_value = engine_clock; 4818 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4819 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4820 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4821 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4822 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4823 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4824 4825 return 0; 4826 } 4827 4828 static int si_populate_sclk_value(struct radeon_device *rdev, 4829 u32 engine_clock, 4830 SISLANDS_SMC_SCLK_VALUE *sclk) 4831 { 4832 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4833 int ret; 4834 4835 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4836 if (!ret) { 4837 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4838 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4839 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4840 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4841 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4842 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4843 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4844 } 4845 4846 return ret; 4847 } 4848 4849 static int si_populate_mclk_value(struct radeon_device *rdev, 4850 u32 engine_clock, 4851 u32 memory_clock, 4852 SISLANDS_SMC_MCLK_VALUE *mclk, 4853 bool strobe_mode, 4854 bool dll_state_on) 4855 { 4856 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4857 struct si_power_info *si_pi = si_get_pi(rdev); 4858 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4859 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4860 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4861 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4862 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4863 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4864 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4865 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4866 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4867 struct atom_mpll_param mpll_param; 4868 int ret; 4869 4870 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4871 if (ret) 4872 return ret; 4873 4874 mpll_func_cntl &= ~BWCTRL_MASK; 4875 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4876 4877 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4878 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4879 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4880 4881 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4882 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4883 4884 if (pi->mem_gddr5) { 4885 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4886 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4887 YCLK_POST_DIV(mpll_param.post_div); 4888 } 4889 4890 if (pi->mclk_ss) { 4891 struct radeon_atom_ss ss; 4892 u32 freq_nom; 4893 u32 tmp; 4894 u32 reference_clock = rdev->clock.mpll.reference_freq; 4895 4896 if (pi->mem_gddr5) 4897 freq_nom = memory_clock * 4; 4898 else 4899 freq_nom = memory_clock * 2; 4900 4901 tmp = freq_nom / reference_clock; 4902 tmp = tmp * tmp; 4903 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4904 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4905 u32 clks = reference_clock * 5 / ss.rate; 4906 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4907 4908 mpll_ss1 &= ~CLKV_MASK; 4909 mpll_ss1 |= CLKV(clkv); 4910 4911 mpll_ss2 &= ~CLKS_MASK; 4912 mpll_ss2 |= CLKS(clks); 4913 } 4914 } 4915 4916 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4917 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4918 4919 if (dll_state_on) 4920 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4921 else 4922 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4923 4924 mclk->mclk_value = cpu_to_be32(memory_clock); 4925 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4926 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4927 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4928 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4929 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4930 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4931 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4932 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4933 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4934 4935 return 0; 4936 } 4937 4938 static void si_populate_smc_sp(struct radeon_device *rdev, 4939 struct radeon_ps *radeon_state, 4940 SISLANDS_SMC_SWSTATE *smc_state) 4941 { 4942 struct ni_ps *ps = ni_get_ps(radeon_state); 4943 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4944 int i; 4945 4946 for (i = 0; i < ps->performance_level_count - 1; i++) 4947 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4948 4949 smc_state->levels[ps->performance_level_count - 1].bSP = 4950 cpu_to_be32(pi->psp); 4951 } 4952 4953 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4954 struct rv7xx_pl *pl, 4955 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4956 { 4957 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4958 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4959 struct si_power_info *si_pi = si_get_pi(rdev); 4960 int ret; 4961 bool dll_state_on; 4962 u16 std_vddc; 4963 bool gmc_pg = false; 4964 4965 if (eg_pi->pcie_performance_request && 4966 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4967 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4968 else 4969 level->gen2PCIE = (u8)pl->pcie_gen; 4970 4971 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4972 if (ret) 4973 return ret; 4974 4975 level->mcFlags = 0; 4976 4977 if (pi->mclk_stutter_mode_threshold && 4978 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4979 !eg_pi->uvd_enabled && 4980 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4981 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4982 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4983 4984 if (gmc_pg) 4985 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4986 } 4987 4988 if (pi->mem_gddr5) { 4989 if (pl->mclk > pi->mclk_edc_enable_threshold) 4990 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4991 4992 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4993 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4994 4995 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4996 4997 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4998 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4999 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5000 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5001 else 5002 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5003 } else { 5004 dll_state_on = false; 5005 } 5006 } else { 5007 level->strobeMode = si_get_strobe_mode_settings(rdev, 5008 pl->mclk); 5009 5010 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5011 } 5012 5013 ret = si_populate_mclk_value(rdev, 5014 pl->sclk, 5015 pl->mclk, 5016 &level->mclk, 5017 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5018 if (ret) 5019 return ret; 5020 5021 ret = si_populate_voltage_value(rdev, 5022 &eg_pi->vddc_voltage_table, 5023 pl->vddc, &level->vddc); 5024 if (ret) 5025 return ret; 5026 5027 5028 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5029 if (ret) 5030 return ret; 5031 5032 ret = si_populate_std_voltage_value(rdev, std_vddc, 5033 level->vddc.index, &level->std_vddc); 5034 if (ret) 5035 return ret; 5036 5037 if (eg_pi->vddci_control) { 5038 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5039 pl->vddci, &level->vddci); 5040 if (ret) 5041 return ret; 5042 } 5043 5044 if (si_pi->vddc_phase_shed_control) { 5045 ret = si_populate_phase_shedding_value(rdev, 5046 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5047 pl->vddc, 5048 pl->sclk, 5049 pl->mclk, 5050 &level->vddc); 5051 if (ret) 5052 return ret; 5053 } 5054 5055 level->MaxPoweredUpCU = si_pi->max_cu; 5056 5057 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5058 5059 return ret; 5060 } 5061 5062 static int si_populate_smc_t(struct radeon_device *rdev, 5063 struct radeon_ps *radeon_state, 5064 SISLANDS_SMC_SWSTATE *smc_state) 5065 { 5066 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5067 struct ni_ps *state = ni_get_ps(radeon_state); 5068 u32 a_t; 5069 u32 t_l, t_h; 5070 u32 high_bsp; 5071 int i, ret; 5072 5073 if (state->performance_level_count >= 9) 5074 return -EINVAL; 5075 5076 if (state->performance_level_count < 2) { 5077 a_t = CG_R(0xffff) | CG_L(0); 5078 smc_state->levels[0].aT = cpu_to_be32(a_t); 5079 return 0; 5080 } 5081 5082 smc_state->levels[0].aT = cpu_to_be32(0); 5083 5084 for (i = 0; i <= state->performance_level_count - 2; i++) { 5085 ret = r600_calculate_at( 5086 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5087 100 * R600_AH_DFLT, 5088 state->performance_levels[i + 1].sclk, 5089 state->performance_levels[i].sclk, 5090 &t_l, 5091 &t_h); 5092 5093 if (ret) { 5094 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5095 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5096 } 5097 5098 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5099 a_t |= CG_R(t_l * pi->bsp / 20000); 5100 smc_state->levels[i].aT = cpu_to_be32(a_t); 5101 5102 high_bsp = (i == state->performance_level_count - 2) ? 5103 pi->pbsp : pi->bsp; 5104 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5105 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5106 } 5107 5108 return 0; 5109 } 5110 5111 static int si_disable_ulv(struct radeon_device *rdev) 5112 { 5113 struct si_power_info *si_pi = si_get_pi(rdev); 5114 struct si_ulv_param *ulv = &si_pi->ulv; 5115 5116 if (ulv->supported) 5117 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5118 0 : -EINVAL; 5119 5120 return 0; 5121 } 5122 5123 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5124 struct radeon_ps *radeon_state) 5125 { 5126 const struct si_power_info *si_pi = si_get_pi(rdev); 5127 const struct si_ulv_param *ulv = &si_pi->ulv; 5128 const struct ni_ps *state = ni_get_ps(radeon_state); 5129 int i; 5130 5131 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5132 return false; 5133 5134 /* XXX validate against display requirements! */ 5135 5136 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5137 if (rdev->clock.current_dispclk <= 5138 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5139 if (ulv->pl.vddc < 5140 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5141 return false; 5142 } 5143 } 5144 5145 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5146 return false; 5147 5148 return true; 5149 } 5150 5151 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5152 struct radeon_ps *radeon_new_state) 5153 { 5154 const struct si_power_info *si_pi = si_get_pi(rdev); 5155 const struct si_ulv_param *ulv = &si_pi->ulv; 5156 5157 if (ulv->supported) { 5158 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5159 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5160 0 : -EINVAL; 5161 } 5162 return 0; 5163 } 5164 5165 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5166 struct radeon_ps *radeon_state, 5167 SISLANDS_SMC_SWSTATE *smc_state) 5168 { 5169 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5170 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5171 struct si_power_info *si_pi = si_get_pi(rdev); 5172 struct ni_ps *state = ni_get_ps(radeon_state); 5173 int i, ret; 5174 u32 threshold; 5175 u32 sclk_in_sr = 1350; /* ??? */ 5176 5177 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5178 return -EINVAL; 5179 5180 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5181 5182 if (radeon_state->vclk && radeon_state->dclk) { 5183 eg_pi->uvd_enabled = true; 5184 if (eg_pi->smu_uvd_hs) 5185 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5186 } else { 5187 eg_pi->uvd_enabled = false; 5188 } 5189 5190 if (state->dc_compatible) 5191 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5192 5193 smc_state->levelCount = 0; 5194 for (i = 0; i < state->performance_level_count; i++) { 5195 if (eg_pi->sclk_deep_sleep) { 5196 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5197 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5198 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5199 else 5200 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5201 } 5202 } 5203 5204 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5205 &smc_state->levels[i]); 5206 smc_state->levels[i].arbRefreshState = 5207 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5208 5209 if (ret) 5210 return ret; 5211 5212 if (ni_pi->enable_power_containment) 5213 smc_state->levels[i].displayWatermark = 5214 (state->performance_levels[i].sclk < threshold) ? 5215 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5216 else 5217 smc_state->levels[i].displayWatermark = (i < 2) ? 5218 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5219 5220 if (eg_pi->dynamic_ac_timing) 5221 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5222 else 5223 smc_state->levels[i].ACIndex = 0; 5224 5225 smc_state->levelCount++; 5226 } 5227 5228 si_write_smc_soft_register(rdev, 5229 SI_SMC_SOFT_REGISTER_watermark_threshold, 5230 threshold / 512); 5231 5232 si_populate_smc_sp(rdev, radeon_state, smc_state); 5233 5234 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5235 if (ret) 5236 ni_pi->enable_power_containment = false; 5237 5238 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5239 if (ret) 5240 ni_pi->enable_sq_ramping = false; 5241 5242 return si_populate_smc_t(rdev, radeon_state, smc_state); 5243 } 5244 5245 static int si_upload_sw_state(struct radeon_device *rdev, 5246 struct radeon_ps *radeon_new_state) 5247 { 5248 struct si_power_info *si_pi = si_get_pi(rdev); 5249 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5250 int ret; 5251 u32 address = si_pi->state_table_start + 5252 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5253 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5254 size_t state_size = struct_size(smc_state, levels, 5255 new_state->performance_level_count); 5256 5257 memset(smc_state, 0, state_size); 5258 5259 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5260 if (ret) 5261 return ret; 5262 5263 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5264 state_size, si_pi->sram_end); 5265 5266 return ret; 5267 } 5268 5269 static int si_upload_ulv_state(struct radeon_device *rdev) 5270 { 5271 struct si_power_info *si_pi = si_get_pi(rdev); 5272 struct si_ulv_param *ulv = &si_pi->ulv; 5273 int ret = 0; 5274 5275 if (ulv->supported && ulv->pl.vddc) { 5276 u32 address = si_pi->state_table_start + 5277 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5278 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5279 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5280 5281 memset(smc_state, 0, state_size); 5282 5283 ret = si_populate_ulv_state(rdev, smc_state); 5284 if (!ret) 5285 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5286 state_size, si_pi->sram_end); 5287 } 5288 5289 return ret; 5290 } 5291 5292 static int si_upload_smc_data(struct radeon_device *rdev) 5293 { 5294 struct radeon_crtc *radeon_crtc = NULL; 5295 int i; 5296 5297 if (rdev->pm.dpm.new_active_crtc_count == 0) 5298 return 0; 5299 5300 for (i = 0; i < rdev->num_crtc; i++) { 5301 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5302 radeon_crtc = rdev->mode_info.crtcs[i]; 5303 break; 5304 } 5305 } 5306 5307 if (radeon_crtc == NULL) 5308 return 0; 5309 5310 if (radeon_crtc->line_time <= 0) 5311 return 0; 5312 5313 if (si_write_smc_soft_register(rdev, 5314 SI_SMC_SOFT_REGISTER_crtc_index, 5315 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5316 return 0; 5317 5318 if (si_write_smc_soft_register(rdev, 5319 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5320 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5321 return 0; 5322 5323 if (si_write_smc_soft_register(rdev, 5324 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5325 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5326 return 0; 5327 5328 return 0; 5329 } 5330 5331 static int si_set_mc_special_registers(struct radeon_device *rdev, 5332 struct si_mc_reg_table *table) 5333 { 5334 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5335 u8 i, j, k; 5336 u32 temp_reg; 5337 5338 for (i = 0, j = table->last; i < table->last; i++) { 5339 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5340 return -EINVAL; 5341 switch (table->mc_reg_address[i].s1 << 2) { 5342 case MC_SEQ_MISC1: 5343 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5344 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5345 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5346 for (k = 0; k < table->num_entries; k++) 5347 table->mc_reg_table_entry[k].mc_data[j] = 5348 ((temp_reg & 0xffff0000)) | 5349 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5350 j++; 5351 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5352 return -EINVAL; 5353 5354 temp_reg = RREG32(MC_PMG_CMD_MRS); 5355 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5356 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5357 for (k = 0; k < table->num_entries; k++) { 5358 table->mc_reg_table_entry[k].mc_data[j] = 5359 (temp_reg & 0xffff0000) | 5360 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5361 if (!pi->mem_gddr5) 5362 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5363 } 5364 j++; 5365 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5366 return -EINVAL; 5367 5368 if (!pi->mem_gddr5) { 5369 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5370 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5371 for (k = 0; k < table->num_entries; k++) 5372 table->mc_reg_table_entry[k].mc_data[j] = 5373 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5374 j++; 5375 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5376 return -EINVAL; 5377 } 5378 break; 5379 case MC_SEQ_RESERVE_M: 5380 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5381 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5382 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5383 for(k = 0; k < table->num_entries; k++) 5384 table->mc_reg_table_entry[k].mc_data[j] = 5385 (temp_reg & 0xffff0000) | 5386 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5387 j++; 5388 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5389 return -EINVAL; 5390 break; 5391 default: 5392 break; 5393 } 5394 } 5395 5396 table->last = j; 5397 5398 return 0; 5399 } 5400 5401 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5402 { 5403 bool result = true; 5404 5405 switch (in_reg) { 5406 case MC_SEQ_RAS_TIMING >> 2: 5407 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5408 break; 5409 case MC_SEQ_CAS_TIMING >> 2: 5410 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5411 break; 5412 case MC_SEQ_MISC_TIMING >> 2: 5413 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5414 break; 5415 case MC_SEQ_MISC_TIMING2 >> 2: 5416 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5417 break; 5418 case MC_SEQ_RD_CTL_D0 >> 2: 5419 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5420 break; 5421 case MC_SEQ_RD_CTL_D1 >> 2: 5422 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5423 break; 5424 case MC_SEQ_WR_CTL_D0 >> 2: 5425 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5426 break; 5427 case MC_SEQ_WR_CTL_D1 >> 2: 5428 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5429 break; 5430 case MC_PMG_CMD_EMRS >> 2: 5431 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5432 break; 5433 case MC_PMG_CMD_MRS >> 2: 5434 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5435 break; 5436 case MC_PMG_CMD_MRS1 >> 2: 5437 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5438 break; 5439 case MC_SEQ_PMG_TIMING >> 2: 5440 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5441 break; 5442 case MC_PMG_CMD_MRS2 >> 2: 5443 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5444 break; 5445 case MC_SEQ_WR_CTL_2 >> 2: 5446 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5447 break; 5448 default: 5449 result = false; 5450 break; 5451 } 5452 5453 return result; 5454 } 5455 5456 static void si_set_valid_flag(struct si_mc_reg_table *table) 5457 { 5458 u8 i, j; 5459 5460 for (i = 0; i < table->last; i++) { 5461 for (j = 1; j < table->num_entries; j++) { 5462 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5463 table->valid_flag |= 1 << i; 5464 break; 5465 } 5466 } 5467 } 5468 } 5469 5470 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5471 { 5472 u32 i; 5473 u16 address; 5474 5475 for (i = 0; i < table->last; i++) 5476 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5477 address : table->mc_reg_address[i].s1; 5478 5479 } 5480 5481 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5482 struct si_mc_reg_table *si_table) 5483 { 5484 u8 i, j; 5485 5486 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5487 return -EINVAL; 5488 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5489 return -EINVAL; 5490 5491 for (i = 0; i < table->last; i++) 5492 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5493 si_table->last = table->last; 5494 5495 for (i = 0; i < table->num_entries; i++) { 5496 si_table->mc_reg_table_entry[i].mclk_max = 5497 table->mc_reg_table_entry[i].mclk_max; 5498 for (j = 0; j < table->last; j++) { 5499 si_table->mc_reg_table_entry[i].mc_data[j] = 5500 table->mc_reg_table_entry[i].mc_data[j]; 5501 } 5502 } 5503 si_table->num_entries = table->num_entries; 5504 5505 return 0; 5506 } 5507 5508 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5509 { 5510 struct si_power_info *si_pi = si_get_pi(rdev); 5511 struct atom_mc_reg_table *table; 5512 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5513 u8 module_index = rv770_get_memory_module_index(rdev); 5514 int ret; 5515 5516 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5517 if (!table) 5518 return -ENOMEM; 5519 5520 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5521 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5522 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5523 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5524 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5525 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5526 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5527 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5528 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5529 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5530 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5531 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5532 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5533 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5534 5535 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5536 if (ret) 5537 goto init_mc_done; 5538 5539 ret = si_copy_vbios_mc_reg_table(table, si_table); 5540 if (ret) 5541 goto init_mc_done; 5542 5543 si_set_s0_mc_reg_index(si_table); 5544 5545 ret = si_set_mc_special_registers(rdev, si_table); 5546 if (ret) 5547 goto init_mc_done; 5548 5549 si_set_valid_flag(si_table); 5550 5551 init_mc_done: 5552 kfree(table); 5553 5554 return ret; 5555 5556 } 5557 5558 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5559 SMC_SIslands_MCRegisters *mc_reg_table) 5560 { 5561 struct si_power_info *si_pi = si_get_pi(rdev); 5562 u32 i, j; 5563 5564 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5565 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5566 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5567 break; 5568 mc_reg_table->address[i].s0 = 5569 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5570 mc_reg_table->address[i].s1 = 5571 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5572 i++; 5573 } 5574 } 5575 mc_reg_table->last = (u8)i; 5576 } 5577 5578 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5579 SMC_SIslands_MCRegisterSet *data, 5580 u32 num_entries, u32 valid_flag) 5581 { 5582 u32 i, j; 5583 5584 for(i = 0, j = 0; j < num_entries; j++) { 5585 if (valid_flag & (1 << j)) { 5586 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5587 i++; 5588 } 5589 } 5590 } 5591 5592 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5593 struct rv7xx_pl *pl, 5594 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5595 { 5596 struct si_power_info *si_pi = si_get_pi(rdev); 5597 u32 i = 0; 5598 5599 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5600 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5601 break; 5602 } 5603 5604 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5605 --i; 5606 5607 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5608 mc_reg_table_data, si_pi->mc_reg_table.last, 5609 si_pi->mc_reg_table.valid_flag); 5610 } 5611 5612 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5613 struct radeon_ps *radeon_state, 5614 SMC_SIslands_MCRegisters *mc_reg_table) 5615 { 5616 struct ni_ps *state = ni_get_ps(radeon_state); 5617 int i; 5618 5619 for (i = 0; i < state->performance_level_count; i++) { 5620 si_convert_mc_reg_table_entry_to_smc(rdev, 5621 &state->performance_levels[i], 5622 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5623 } 5624 } 5625 5626 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5627 struct radeon_ps *radeon_boot_state) 5628 { 5629 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5630 struct si_power_info *si_pi = si_get_pi(rdev); 5631 struct si_ulv_param *ulv = &si_pi->ulv; 5632 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5633 5634 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5635 5636 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5637 5638 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5639 5640 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5641 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5642 5643 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5644 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5645 si_pi->mc_reg_table.last, 5646 si_pi->mc_reg_table.valid_flag); 5647 5648 if (ulv->supported && ulv->pl.vddc != 0) 5649 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5650 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5651 else 5652 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5653 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5654 si_pi->mc_reg_table.last, 5655 si_pi->mc_reg_table.valid_flag); 5656 5657 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5658 5659 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5660 (u8 *)smc_mc_reg_table, 5661 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5662 } 5663 5664 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5665 struct radeon_ps *radeon_new_state) 5666 { 5667 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5668 struct si_power_info *si_pi = si_get_pi(rdev); 5669 u32 address = si_pi->mc_reg_table_start + 5670 offsetof(SMC_SIslands_MCRegisters, 5671 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5672 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5673 5674 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5675 5676 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5677 5678 5679 return si_copy_bytes_to_smc(rdev, address, 5680 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5681 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5682 si_pi->sram_end); 5683 5684 } 5685 5686 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5687 { 5688 if (enable) 5689 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5690 else 5691 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5692 } 5693 5694 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5695 struct radeon_ps *radeon_state) 5696 { 5697 struct ni_ps *state = ni_get_ps(radeon_state); 5698 int i; 5699 u16 pcie_speed, max_speed = 0; 5700 5701 for (i = 0; i < state->performance_level_count; i++) { 5702 pcie_speed = state->performance_levels[i].pcie_gen; 5703 if (max_speed < pcie_speed) 5704 max_speed = pcie_speed; 5705 } 5706 return max_speed; 5707 } 5708 5709 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5710 { 5711 u32 speed_cntl; 5712 5713 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5714 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5715 5716 return (u16)speed_cntl; 5717 } 5718 5719 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5720 struct radeon_ps *radeon_new_state, 5721 struct radeon_ps *radeon_current_state) 5722 { 5723 struct si_power_info *si_pi = si_get_pi(rdev); 5724 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5725 enum radeon_pcie_gen current_link_speed; 5726 5727 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5728 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5729 else 5730 current_link_speed = si_pi->force_pcie_gen; 5731 5732 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5733 si_pi->pspp_notify_required = false; 5734 if (target_link_speed > current_link_speed) { 5735 switch (target_link_speed) { 5736 #if defined(CONFIG_ACPI) 5737 case RADEON_PCIE_GEN3: 5738 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5739 break; 5740 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5741 if (current_link_speed == RADEON_PCIE_GEN2) 5742 break; 5743 fallthrough; 5744 case RADEON_PCIE_GEN2: 5745 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5746 break; 5747 fallthrough; 5748 #endif 5749 default: 5750 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5751 break; 5752 } 5753 } else { 5754 if (target_link_speed < current_link_speed) 5755 si_pi->pspp_notify_required = true; 5756 } 5757 } 5758 5759 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5760 struct radeon_ps *radeon_new_state, 5761 struct radeon_ps *radeon_current_state) 5762 { 5763 struct si_power_info *si_pi = si_get_pi(rdev); 5764 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5765 u8 request; 5766 5767 if (si_pi->pspp_notify_required) { 5768 if (target_link_speed == RADEON_PCIE_GEN3) 5769 request = PCIE_PERF_REQ_PECI_GEN3; 5770 else if (target_link_speed == RADEON_PCIE_GEN2) 5771 request = PCIE_PERF_REQ_PECI_GEN2; 5772 else 5773 request = PCIE_PERF_REQ_PECI_GEN1; 5774 5775 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5776 (si_get_current_pcie_speed(rdev) > 0)) 5777 return; 5778 5779 #if defined(CONFIG_ACPI) 5780 radeon_acpi_pcie_performance_request(rdev, request, false); 5781 #endif 5782 } 5783 } 5784 5785 #if 0 5786 static int si_ds_request(struct radeon_device *rdev, 5787 bool ds_status_on, u32 count_write) 5788 { 5789 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5790 5791 if (eg_pi->sclk_deep_sleep) { 5792 if (ds_status_on) 5793 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5794 PPSMC_Result_OK) ? 5795 0 : -EINVAL; 5796 else 5797 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5798 PPSMC_Result_OK) ? 0 : -EINVAL; 5799 } 5800 return 0; 5801 } 5802 #endif 5803 5804 static void si_set_max_cu_value(struct radeon_device *rdev) 5805 { 5806 struct si_power_info *si_pi = si_get_pi(rdev); 5807 5808 if (rdev->family == CHIP_VERDE) { 5809 switch (rdev->pdev->device) { 5810 case 0x6820: 5811 case 0x6825: 5812 case 0x6821: 5813 case 0x6823: 5814 case 0x6827: 5815 si_pi->max_cu = 10; 5816 break; 5817 case 0x682D: 5818 case 0x6824: 5819 case 0x682F: 5820 case 0x6826: 5821 si_pi->max_cu = 8; 5822 break; 5823 case 0x6828: 5824 case 0x6830: 5825 case 0x6831: 5826 case 0x6838: 5827 case 0x6839: 5828 case 0x683D: 5829 si_pi->max_cu = 10; 5830 break; 5831 case 0x683B: 5832 case 0x683F: 5833 case 0x6829: 5834 si_pi->max_cu = 8; 5835 break; 5836 default: 5837 si_pi->max_cu = 0; 5838 break; 5839 } 5840 } else { 5841 si_pi->max_cu = 0; 5842 } 5843 } 5844 5845 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5846 struct radeon_clock_voltage_dependency_table *table) 5847 { 5848 u32 i; 5849 int j; 5850 u16 leakage_voltage; 5851 5852 if (table) { 5853 for (i = 0; i < table->count; i++) { 5854 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5855 table->entries[i].v, 5856 &leakage_voltage)) { 5857 case 0: 5858 table->entries[i].v = leakage_voltage; 5859 break; 5860 case -EAGAIN: 5861 return -EINVAL; 5862 case -EINVAL: 5863 default: 5864 break; 5865 } 5866 } 5867 5868 for (j = (table->count - 2); j >= 0; j--) { 5869 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5870 table->entries[j].v : table->entries[j + 1].v; 5871 } 5872 } 5873 return 0; 5874 } 5875 5876 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5877 { 5878 int ret; 5879 5880 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5881 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5882 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5883 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5884 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5885 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5886 return ret; 5887 } 5888 5889 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5890 struct radeon_ps *radeon_new_state, 5891 struct radeon_ps *radeon_current_state) 5892 { 5893 u32 lane_width; 5894 u32 new_lane_width = 5895 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5896 u32 current_lane_width = 5897 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5898 5899 if (new_lane_width != current_lane_width) { 5900 radeon_set_pcie_lanes(rdev, new_lane_width); 5901 lane_width = radeon_get_pcie_lanes(rdev); 5902 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5903 } 5904 } 5905 5906 static void si_set_vce_clock(struct radeon_device *rdev, 5907 struct radeon_ps *new_rps, 5908 struct radeon_ps *old_rps) 5909 { 5910 if ((old_rps->evclk != new_rps->evclk) || 5911 (old_rps->ecclk != new_rps->ecclk)) { 5912 /* turn the clocks on when encoding, off otherwise */ 5913 if (new_rps->evclk || new_rps->ecclk) 5914 vce_v1_0_enable_mgcg(rdev, false); 5915 else 5916 vce_v1_0_enable_mgcg(rdev, true); 5917 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5918 } 5919 } 5920 5921 void si_dpm_setup_asic(struct radeon_device *rdev) 5922 { 5923 int r; 5924 5925 r = si_mc_load_microcode(rdev); 5926 if (r) 5927 DRM_ERROR("Failed to load MC firmware!\n"); 5928 rv770_get_memory_type(rdev); 5929 si_read_clock_registers(rdev); 5930 si_enable_acpi_power_management(rdev); 5931 } 5932 5933 static int si_thermal_enable_alert(struct radeon_device *rdev, 5934 bool enable) 5935 { 5936 u32 thermal_int = RREG32(CG_THERMAL_INT); 5937 5938 if (enable) { 5939 PPSMC_Result result; 5940 5941 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5942 WREG32(CG_THERMAL_INT, thermal_int); 5943 rdev->irq.dpm_thermal = false; 5944 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5945 if (result != PPSMC_Result_OK) { 5946 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5947 return -EINVAL; 5948 } 5949 } else { 5950 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5951 WREG32(CG_THERMAL_INT, thermal_int); 5952 rdev->irq.dpm_thermal = true; 5953 } 5954 5955 return 0; 5956 } 5957 5958 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5959 int min_temp, int max_temp) 5960 { 5961 int low_temp = 0 * 1000; 5962 int high_temp = 255 * 1000; 5963 5964 if (low_temp < min_temp) 5965 low_temp = min_temp; 5966 if (high_temp > max_temp) 5967 high_temp = max_temp; 5968 if (high_temp < low_temp) { 5969 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5970 return -EINVAL; 5971 } 5972 5973 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5974 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5975 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5976 5977 rdev->pm.dpm.thermal.min_temp = low_temp; 5978 rdev->pm.dpm.thermal.max_temp = high_temp; 5979 5980 return 0; 5981 } 5982 5983 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5984 { 5985 struct si_power_info *si_pi = si_get_pi(rdev); 5986 u32 tmp; 5987 5988 if (si_pi->fan_ctrl_is_in_default_mode) { 5989 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5990 si_pi->fan_ctrl_default_mode = tmp; 5991 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5992 si_pi->t_min = tmp; 5993 si_pi->fan_ctrl_is_in_default_mode = false; 5994 } 5995 5996 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 5997 tmp |= TMIN(0); 5998 WREG32(CG_FDO_CTRL2, tmp); 5999 6000 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6001 tmp |= FDO_PWM_MODE(mode); 6002 WREG32(CG_FDO_CTRL2, tmp); 6003 } 6004 6005 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6006 { 6007 struct si_power_info *si_pi = si_get_pi(rdev); 6008 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6009 u32 duty100; 6010 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6011 u16 fdo_min, slope1, slope2; 6012 u32 reference_clock, tmp; 6013 int ret; 6014 u64 tmp64; 6015 6016 if (!si_pi->fan_table_start) { 6017 rdev->pm.dpm.fan.ucode_fan_control = false; 6018 return 0; 6019 } 6020 6021 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6022 6023 if (duty100 == 0) { 6024 rdev->pm.dpm.fan.ucode_fan_control = false; 6025 return 0; 6026 } 6027 6028 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6029 do_div(tmp64, 10000); 6030 fdo_min = (u16)tmp64; 6031 6032 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6033 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6034 6035 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6036 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6037 6038 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6039 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6040 6041 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6042 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6043 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6044 6045 fan_table.slope1 = cpu_to_be16(slope1); 6046 fan_table.slope2 = cpu_to_be16(slope2); 6047 6048 fan_table.fdo_min = cpu_to_be16(fdo_min); 6049 6050 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6051 6052 fan_table.hys_up = cpu_to_be16(1); 6053 6054 fan_table.hys_slope = cpu_to_be16(1); 6055 6056 fan_table.temp_resp_lim = cpu_to_be16(5); 6057 6058 reference_clock = radeon_get_xclk(rdev); 6059 6060 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6061 reference_clock) / 1600); 6062 6063 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6064 6065 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6066 fan_table.temp_src = (uint8_t)tmp; 6067 6068 ret = si_copy_bytes_to_smc(rdev, 6069 si_pi->fan_table_start, 6070 (u8 *)(&fan_table), 6071 sizeof(fan_table), 6072 si_pi->sram_end); 6073 6074 if (ret) { 6075 DRM_ERROR("Failed to load fan table to the SMC."); 6076 rdev->pm.dpm.fan.ucode_fan_control = false; 6077 } 6078 6079 return 0; 6080 } 6081 6082 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6083 { 6084 struct si_power_info *si_pi = si_get_pi(rdev); 6085 PPSMC_Result ret; 6086 6087 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6088 if (ret == PPSMC_Result_OK) { 6089 si_pi->fan_is_controlled_by_smc = true; 6090 return 0; 6091 } else { 6092 return -EINVAL; 6093 } 6094 } 6095 6096 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6097 { 6098 struct si_power_info *si_pi = si_get_pi(rdev); 6099 PPSMC_Result ret; 6100 6101 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6102 6103 if (ret == PPSMC_Result_OK) { 6104 si_pi->fan_is_controlled_by_smc = false; 6105 return 0; 6106 } else { 6107 return -EINVAL; 6108 } 6109 } 6110 6111 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6112 u32 *speed) 6113 { 6114 u32 duty, duty100; 6115 u64 tmp64; 6116 6117 if (rdev->pm.no_fan) 6118 return -ENOENT; 6119 6120 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6121 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6122 6123 if (duty100 == 0) 6124 return -EINVAL; 6125 6126 tmp64 = (u64)duty * 100; 6127 do_div(tmp64, duty100); 6128 *speed = (u32)tmp64; 6129 6130 if (*speed > 100) 6131 *speed = 100; 6132 6133 return 0; 6134 } 6135 6136 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6137 u32 speed) 6138 { 6139 struct si_power_info *si_pi = si_get_pi(rdev); 6140 u32 tmp; 6141 u32 duty, duty100; 6142 u64 tmp64; 6143 6144 if (rdev->pm.no_fan) 6145 return -ENOENT; 6146 6147 if (si_pi->fan_is_controlled_by_smc) 6148 return -EINVAL; 6149 6150 if (speed > 100) 6151 return -EINVAL; 6152 6153 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6154 6155 if (duty100 == 0) 6156 return -EINVAL; 6157 6158 tmp64 = (u64)speed * duty100; 6159 do_div(tmp64, 100); 6160 duty = (u32)tmp64; 6161 6162 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6163 tmp |= FDO_STATIC_DUTY(duty); 6164 WREG32(CG_FDO_CTRL0, tmp); 6165 6166 return 0; 6167 } 6168 6169 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6170 { 6171 if (mode) { 6172 /* stop auto-manage */ 6173 if (rdev->pm.dpm.fan.ucode_fan_control) 6174 si_fan_ctrl_stop_smc_fan_control(rdev); 6175 si_fan_ctrl_set_static_mode(rdev, mode); 6176 } else { 6177 /* restart auto-manage */ 6178 if (rdev->pm.dpm.fan.ucode_fan_control) 6179 si_thermal_start_smc_fan_control(rdev); 6180 else 6181 si_fan_ctrl_set_default_mode(rdev); 6182 } 6183 } 6184 6185 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6186 { 6187 struct si_power_info *si_pi = si_get_pi(rdev); 6188 u32 tmp; 6189 6190 if (si_pi->fan_is_controlled_by_smc) 6191 return 0; 6192 6193 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6194 return (tmp >> FDO_PWM_MODE_SHIFT); 6195 } 6196 6197 #if 0 6198 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6199 u32 *speed) 6200 { 6201 u32 tach_period; 6202 u32 xclk = radeon_get_xclk(rdev); 6203 6204 if (rdev->pm.no_fan) 6205 return -ENOENT; 6206 6207 if (rdev->pm.fan_pulses_per_revolution == 0) 6208 return -ENOENT; 6209 6210 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6211 if (tach_period == 0) 6212 return -ENOENT; 6213 6214 *speed = 60 * xclk * 10000 / tach_period; 6215 6216 return 0; 6217 } 6218 6219 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6220 u32 speed) 6221 { 6222 u32 tach_period, tmp; 6223 u32 xclk = radeon_get_xclk(rdev); 6224 6225 if (rdev->pm.no_fan) 6226 return -ENOENT; 6227 6228 if (rdev->pm.fan_pulses_per_revolution == 0) 6229 return -ENOENT; 6230 6231 if ((speed < rdev->pm.fan_min_rpm) || 6232 (speed > rdev->pm.fan_max_rpm)) 6233 return -EINVAL; 6234 6235 if (rdev->pm.dpm.fan.ucode_fan_control) 6236 si_fan_ctrl_stop_smc_fan_control(rdev); 6237 6238 tach_period = 60 * xclk * 10000 / (8 * speed); 6239 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6240 tmp |= TARGET_PERIOD(tach_period); 6241 WREG32(CG_TACH_CTRL, tmp); 6242 6243 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6244 6245 return 0; 6246 } 6247 #endif 6248 6249 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6250 { 6251 struct si_power_info *si_pi = si_get_pi(rdev); 6252 u32 tmp; 6253 6254 if (!si_pi->fan_ctrl_is_in_default_mode) { 6255 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6256 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6257 WREG32(CG_FDO_CTRL2, tmp); 6258 6259 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6260 tmp |= TMIN(si_pi->t_min); 6261 WREG32(CG_FDO_CTRL2, tmp); 6262 si_pi->fan_ctrl_is_in_default_mode = true; 6263 } 6264 } 6265 6266 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6267 { 6268 if (rdev->pm.dpm.fan.ucode_fan_control) { 6269 si_fan_ctrl_start_smc_fan_control(rdev); 6270 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6271 } 6272 } 6273 6274 static void si_thermal_initialize(struct radeon_device *rdev) 6275 { 6276 u32 tmp; 6277 6278 if (rdev->pm.fan_pulses_per_revolution) { 6279 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6280 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6281 WREG32(CG_TACH_CTRL, tmp); 6282 } 6283 6284 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6285 tmp |= TACH_PWM_RESP_RATE(0x28); 6286 WREG32(CG_FDO_CTRL2, tmp); 6287 } 6288 6289 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6290 { 6291 int ret; 6292 6293 si_thermal_initialize(rdev); 6294 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6295 if (ret) 6296 return ret; 6297 ret = si_thermal_enable_alert(rdev, true); 6298 if (ret) 6299 return ret; 6300 if (rdev->pm.dpm.fan.ucode_fan_control) { 6301 ret = si_halt_smc(rdev); 6302 if (ret) 6303 return ret; 6304 ret = si_thermal_setup_fan_table(rdev); 6305 if (ret) 6306 return ret; 6307 ret = si_resume_smc(rdev); 6308 if (ret) 6309 return ret; 6310 si_thermal_start_smc_fan_control(rdev); 6311 } 6312 6313 return 0; 6314 } 6315 6316 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6317 { 6318 if (!rdev->pm.no_fan) { 6319 si_fan_ctrl_set_default_mode(rdev); 6320 si_fan_ctrl_stop_smc_fan_control(rdev); 6321 } 6322 } 6323 6324 int si_dpm_enable(struct radeon_device *rdev) 6325 { 6326 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6327 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6328 struct si_power_info *si_pi = si_get_pi(rdev); 6329 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6330 int ret; 6331 6332 if (si_is_smc_running(rdev)) 6333 return -EINVAL; 6334 if (pi->voltage_control || si_pi->voltage_control_svi2) 6335 si_enable_voltage_control(rdev, true); 6336 if (pi->mvdd_control) 6337 si_get_mvdd_configuration(rdev); 6338 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6339 ret = si_construct_voltage_tables(rdev); 6340 if (ret) { 6341 DRM_ERROR("si_construct_voltage_tables failed\n"); 6342 return ret; 6343 } 6344 } 6345 if (eg_pi->dynamic_ac_timing) { 6346 ret = si_initialize_mc_reg_table(rdev); 6347 if (ret) 6348 eg_pi->dynamic_ac_timing = false; 6349 } 6350 if (pi->dynamic_ss) 6351 si_enable_spread_spectrum(rdev, true); 6352 if (pi->thermal_protection) 6353 si_enable_thermal_protection(rdev, true); 6354 si_setup_bsp(rdev); 6355 si_program_git(rdev); 6356 si_program_tp(rdev); 6357 si_program_tpp(rdev); 6358 si_program_sstp(rdev); 6359 si_enable_display_gap(rdev); 6360 si_program_vc(rdev); 6361 ret = si_upload_firmware(rdev); 6362 if (ret) { 6363 DRM_ERROR("si_upload_firmware failed\n"); 6364 return ret; 6365 } 6366 ret = si_process_firmware_header(rdev); 6367 if (ret) { 6368 DRM_ERROR("si_process_firmware_header failed\n"); 6369 return ret; 6370 } 6371 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6372 if (ret) { 6373 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6374 return ret; 6375 } 6376 ret = si_init_smc_table(rdev); 6377 if (ret) { 6378 DRM_ERROR("si_init_smc_table failed\n"); 6379 return ret; 6380 } 6381 ret = si_init_smc_spll_table(rdev); 6382 if (ret) { 6383 DRM_ERROR("si_init_smc_spll_table failed\n"); 6384 return ret; 6385 } 6386 ret = si_init_arb_table_index(rdev); 6387 if (ret) { 6388 DRM_ERROR("si_init_arb_table_index failed\n"); 6389 return ret; 6390 } 6391 if (eg_pi->dynamic_ac_timing) { 6392 ret = si_populate_mc_reg_table(rdev, boot_ps); 6393 if (ret) { 6394 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6395 return ret; 6396 } 6397 } 6398 ret = si_initialize_smc_cac_tables(rdev); 6399 if (ret) { 6400 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6401 return ret; 6402 } 6403 ret = si_initialize_hardware_cac_manager(rdev); 6404 if (ret) { 6405 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6406 return ret; 6407 } 6408 ret = si_initialize_smc_dte_tables(rdev); 6409 if (ret) { 6410 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6411 return ret; 6412 } 6413 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6414 if (ret) { 6415 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6416 return ret; 6417 } 6418 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6419 if (ret) { 6420 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6421 return ret; 6422 } 6423 si_program_response_times(rdev); 6424 si_program_ds_registers(rdev); 6425 si_dpm_start_smc(rdev); 6426 ret = si_notify_smc_display_change(rdev, false); 6427 if (ret) { 6428 DRM_ERROR("si_notify_smc_display_change failed\n"); 6429 return ret; 6430 } 6431 si_enable_sclk_control(rdev, true); 6432 si_start_dpm(rdev); 6433 6434 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6435 6436 si_thermal_start_thermal_controller(rdev); 6437 6438 ni_update_current_ps(rdev, boot_ps); 6439 6440 return 0; 6441 } 6442 6443 static int si_set_temperature_range(struct radeon_device *rdev) 6444 { 6445 int ret; 6446 6447 ret = si_thermal_enable_alert(rdev, false); 6448 if (ret) 6449 return ret; 6450 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6451 if (ret) 6452 return ret; 6453 ret = si_thermal_enable_alert(rdev, true); 6454 if (ret) 6455 return ret; 6456 6457 return ret; 6458 } 6459 6460 int si_dpm_late_enable(struct radeon_device *rdev) 6461 { 6462 int ret; 6463 6464 ret = si_set_temperature_range(rdev); 6465 if (ret) 6466 return ret; 6467 6468 return ret; 6469 } 6470 6471 void si_dpm_disable(struct radeon_device *rdev) 6472 { 6473 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6474 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6475 6476 if (!si_is_smc_running(rdev)) 6477 return; 6478 si_thermal_stop_thermal_controller(rdev); 6479 si_disable_ulv(rdev); 6480 si_clear_vc(rdev); 6481 if (pi->thermal_protection) 6482 si_enable_thermal_protection(rdev, false); 6483 si_enable_power_containment(rdev, boot_ps, false); 6484 si_enable_smc_cac(rdev, boot_ps, false); 6485 si_enable_spread_spectrum(rdev, false); 6486 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6487 si_stop_dpm(rdev); 6488 si_reset_to_default(rdev); 6489 si_dpm_stop_smc(rdev); 6490 si_force_switch_to_arb_f0(rdev); 6491 6492 ni_update_current_ps(rdev, boot_ps); 6493 } 6494 6495 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6496 { 6497 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6498 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6499 struct radeon_ps *new_ps = &requested_ps; 6500 6501 ni_update_requested_ps(rdev, new_ps); 6502 6503 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6504 6505 return 0; 6506 } 6507 6508 static int si_power_control_set_level(struct radeon_device *rdev) 6509 { 6510 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6511 int ret; 6512 6513 ret = si_restrict_performance_levels_before_switch(rdev); 6514 if (ret) 6515 return ret; 6516 ret = si_halt_smc(rdev); 6517 if (ret) 6518 return ret; 6519 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6520 if (ret) 6521 return ret; 6522 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6523 if (ret) 6524 return ret; 6525 ret = si_resume_smc(rdev); 6526 if (ret) 6527 return ret; 6528 ret = si_set_sw_state(rdev); 6529 if (ret) 6530 return ret; 6531 return 0; 6532 } 6533 6534 int si_dpm_set_power_state(struct radeon_device *rdev) 6535 { 6536 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6537 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6538 struct radeon_ps *old_ps = &eg_pi->current_rps; 6539 int ret; 6540 6541 ret = si_disable_ulv(rdev); 6542 if (ret) { 6543 DRM_ERROR("si_disable_ulv failed\n"); 6544 return ret; 6545 } 6546 ret = si_restrict_performance_levels_before_switch(rdev); 6547 if (ret) { 6548 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6549 return ret; 6550 } 6551 if (eg_pi->pcie_performance_request) 6552 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6553 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6554 ret = si_enable_power_containment(rdev, new_ps, false); 6555 if (ret) { 6556 DRM_ERROR("si_enable_power_containment failed\n"); 6557 return ret; 6558 } 6559 ret = si_enable_smc_cac(rdev, new_ps, false); 6560 if (ret) { 6561 DRM_ERROR("si_enable_smc_cac failed\n"); 6562 return ret; 6563 } 6564 ret = si_halt_smc(rdev); 6565 if (ret) { 6566 DRM_ERROR("si_halt_smc failed\n"); 6567 return ret; 6568 } 6569 ret = si_upload_sw_state(rdev, new_ps); 6570 if (ret) { 6571 DRM_ERROR("si_upload_sw_state failed\n"); 6572 return ret; 6573 } 6574 ret = si_upload_smc_data(rdev); 6575 if (ret) { 6576 DRM_ERROR("si_upload_smc_data failed\n"); 6577 return ret; 6578 } 6579 ret = si_upload_ulv_state(rdev); 6580 if (ret) { 6581 DRM_ERROR("si_upload_ulv_state failed\n"); 6582 return ret; 6583 } 6584 if (eg_pi->dynamic_ac_timing) { 6585 ret = si_upload_mc_reg_table(rdev, new_ps); 6586 if (ret) { 6587 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6588 return ret; 6589 } 6590 } 6591 ret = si_program_memory_timing_parameters(rdev, new_ps); 6592 if (ret) { 6593 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6594 return ret; 6595 } 6596 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6597 6598 ret = si_resume_smc(rdev); 6599 if (ret) { 6600 DRM_ERROR("si_resume_smc failed\n"); 6601 return ret; 6602 } 6603 ret = si_set_sw_state(rdev); 6604 if (ret) { 6605 DRM_ERROR("si_set_sw_state failed\n"); 6606 return ret; 6607 } 6608 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6609 si_set_vce_clock(rdev, new_ps, old_ps); 6610 if (eg_pi->pcie_performance_request) 6611 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6612 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6613 if (ret) { 6614 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6615 return ret; 6616 } 6617 ret = si_enable_smc_cac(rdev, new_ps, true); 6618 if (ret) { 6619 DRM_ERROR("si_enable_smc_cac failed\n"); 6620 return ret; 6621 } 6622 ret = si_enable_power_containment(rdev, new_ps, true); 6623 if (ret) { 6624 DRM_ERROR("si_enable_power_containment failed\n"); 6625 return ret; 6626 } 6627 6628 ret = si_power_control_set_level(rdev); 6629 if (ret) { 6630 DRM_ERROR("si_power_control_set_level failed\n"); 6631 return ret; 6632 } 6633 6634 return 0; 6635 } 6636 6637 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6638 { 6639 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6640 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6641 6642 ni_update_current_ps(rdev, new_ps); 6643 } 6644 6645 #if 0 6646 void si_dpm_reset_asic(struct radeon_device *rdev) 6647 { 6648 si_restrict_performance_levels_before_switch(rdev); 6649 si_disable_ulv(rdev); 6650 si_set_boot_state(rdev); 6651 } 6652 #endif 6653 6654 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6655 { 6656 si_program_display_gap(rdev); 6657 } 6658 6659 union power_info { 6660 struct _ATOM_POWERPLAY_INFO info; 6661 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6662 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6663 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6664 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6665 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6666 }; 6667 6668 union pplib_clock_info { 6669 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6670 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6671 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6672 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6673 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6674 }; 6675 6676 union pplib_power_state { 6677 struct _ATOM_PPLIB_STATE v1; 6678 struct _ATOM_PPLIB_STATE_V2 v2; 6679 }; 6680 6681 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6682 struct radeon_ps *rps, 6683 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6684 u8 table_rev) 6685 { 6686 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6687 rps->class = le16_to_cpu(non_clock_info->usClassification); 6688 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6689 6690 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6691 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6692 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6693 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6694 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6695 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6696 } else { 6697 rps->vclk = 0; 6698 rps->dclk = 0; 6699 } 6700 6701 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6702 rdev->pm.dpm.boot_ps = rps; 6703 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6704 rdev->pm.dpm.uvd_ps = rps; 6705 } 6706 6707 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6708 struct radeon_ps *rps, int index, 6709 union pplib_clock_info *clock_info) 6710 { 6711 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6712 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6713 struct si_power_info *si_pi = si_get_pi(rdev); 6714 struct ni_ps *ps = ni_get_ps(rps); 6715 u16 leakage_voltage; 6716 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6717 int ret; 6718 6719 ps->performance_level_count = index + 1; 6720 6721 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6722 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6723 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6724 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6725 6726 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6727 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6728 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6729 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6730 si_pi->sys_pcie_mask, 6731 si_pi->boot_pcie_gen, 6732 clock_info->si.ucPCIEGen); 6733 6734 /* patch up vddc if necessary */ 6735 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6736 &leakage_voltage); 6737 if (ret == 0) 6738 pl->vddc = leakage_voltage; 6739 6740 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6741 pi->acpi_vddc = pl->vddc; 6742 eg_pi->acpi_vddci = pl->vddci; 6743 si_pi->acpi_pcie_gen = pl->pcie_gen; 6744 } 6745 6746 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6747 index == 0) { 6748 /* XXX disable for A0 tahiti */ 6749 si_pi->ulv.supported = false; 6750 si_pi->ulv.pl = *pl; 6751 si_pi->ulv.one_pcie_lane_in_ulv = false; 6752 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6753 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6754 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6755 } 6756 6757 if (pi->min_vddc_in_table > pl->vddc) 6758 pi->min_vddc_in_table = pl->vddc; 6759 6760 if (pi->max_vddc_in_table < pl->vddc) 6761 pi->max_vddc_in_table = pl->vddc; 6762 6763 /* patch up boot state */ 6764 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6765 u16 vddc, vddci, mvdd; 6766 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6767 pl->mclk = rdev->clock.default_mclk; 6768 pl->sclk = rdev->clock.default_sclk; 6769 pl->vddc = vddc; 6770 pl->vddci = vddci; 6771 si_pi->mvdd_bootup_value = mvdd; 6772 } 6773 6774 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6775 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6776 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6777 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6778 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6779 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6780 } 6781 } 6782 6783 static int si_parse_power_table(struct radeon_device *rdev) 6784 { 6785 struct radeon_mode_info *mode_info = &rdev->mode_info; 6786 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6787 union pplib_power_state *power_state; 6788 int i, j, k, non_clock_array_index, clock_array_index; 6789 union pplib_clock_info *clock_info; 6790 struct _StateArray *state_array; 6791 struct _ClockInfoArray *clock_info_array; 6792 struct _NonClockInfoArray *non_clock_info_array; 6793 union power_info *power_info; 6794 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6795 u16 data_offset; 6796 u8 frev, crev; 6797 u8 *power_state_offset; 6798 struct ni_ps *ps; 6799 6800 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6801 &frev, &crev, &data_offset)) 6802 return -EINVAL; 6803 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6804 6805 state_array = (struct _StateArray *) 6806 (mode_info->atom_context->bios + data_offset + 6807 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6808 clock_info_array = (struct _ClockInfoArray *) 6809 (mode_info->atom_context->bios + data_offset + 6810 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6811 non_clock_info_array = (struct _NonClockInfoArray *) 6812 (mode_info->atom_context->bios + data_offset + 6813 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6814 6815 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6816 sizeof(struct radeon_ps), 6817 GFP_KERNEL); 6818 if (!rdev->pm.dpm.ps) 6819 return -ENOMEM; 6820 power_state_offset = (u8 *)state_array->states; 6821 for (i = 0; i < state_array->ucNumEntries; i++) { 6822 u8 *idx; 6823 power_state = (union pplib_power_state *)power_state_offset; 6824 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6825 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6826 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6827 if (!rdev->pm.power_state[i].clock_info) 6828 return -EINVAL; 6829 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6830 if (ps == NULL) { 6831 kfree(rdev->pm.dpm.ps); 6832 return -ENOMEM; 6833 } 6834 rdev->pm.dpm.ps[i].ps_priv = ps; 6835 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6836 non_clock_info, 6837 non_clock_info_array->ucEntrySize); 6838 k = 0; 6839 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6840 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6841 clock_array_index = idx[j]; 6842 if (clock_array_index >= clock_info_array->ucNumEntries) 6843 continue; 6844 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6845 break; 6846 clock_info = (union pplib_clock_info *) 6847 ((u8 *)&clock_info_array->clockInfo[0] + 6848 (clock_array_index * clock_info_array->ucEntrySize)); 6849 si_parse_pplib_clock_info(rdev, 6850 &rdev->pm.dpm.ps[i], k, 6851 clock_info); 6852 k++; 6853 } 6854 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6855 } 6856 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6857 6858 /* fill in the vce power states */ 6859 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6860 u32 sclk, mclk; 6861 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6862 clock_info = (union pplib_clock_info *) 6863 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6864 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6865 sclk |= clock_info->si.ucEngineClockHigh << 16; 6866 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6867 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6868 rdev->pm.dpm.vce_states[i].sclk = sclk; 6869 rdev->pm.dpm.vce_states[i].mclk = mclk; 6870 } 6871 6872 return 0; 6873 } 6874 6875 int si_dpm_init(struct radeon_device *rdev) 6876 { 6877 struct rv7xx_power_info *pi; 6878 struct evergreen_power_info *eg_pi; 6879 struct ni_power_info *ni_pi; 6880 struct si_power_info *si_pi; 6881 struct atom_clock_dividers dividers; 6882 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6883 struct pci_dev *root = rdev->pdev->bus->self; 6884 int ret; 6885 6886 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6887 if (si_pi == NULL) 6888 return -ENOMEM; 6889 rdev->pm.dpm.priv = si_pi; 6890 ni_pi = &si_pi->ni; 6891 eg_pi = &ni_pi->eg; 6892 pi = &eg_pi->rv7xx; 6893 6894 if (!pci_is_root_bus(rdev->pdev->bus)) 6895 speed_cap = pcie_get_speed_cap(root); 6896 if (speed_cap == PCI_SPEED_UNKNOWN) { 6897 si_pi->sys_pcie_mask = 0; 6898 } else { 6899 if (speed_cap == PCIE_SPEED_8_0GT) 6900 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6901 RADEON_PCIE_SPEED_50 | 6902 RADEON_PCIE_SPEED_80; 6903 else if (speed_cap == PCIE_SPEED_5_0GT) 6904 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6905 RADEON_PCIE_SPEED_50; 6906 else 6907 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6908 } 6909 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6910 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6911 6912 si_set_max_cu_value(rdev); 6913 6914 rv770_get_max_vddc(rdev); 6915 si_get_leakage_vddc(rdev); 6916 si_patch_dependency_tables_based_on_leakage(rdev); 6917 6918 pi->acpi_vddc = 0; 6919 eg_pi->acpi_vddci = 0; 6920 pi->min_vddc_in_table = 0; 6921 pi->max_vddc_in_table = 0; 6922 6923 ret = r600_get_platform_caps(rdev); 6924 if (ret) 6925 return ret; 6926 6927 ret = r600_parse_extended_power_table(rdev); 6928 if (ret) 6929 return ret; 6930 6931 ret = si_parse_power_table(rdev); 6932 if (ret) 6933 return ret; 6934 6935 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6936 kcalloc(4, 6937 sizeof(struct radeon_clock_voltage_dependency_entry), 6938 GFP_KERNEL); 6939 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6940 r600_free_extended_power_table(rdev); 6941 return -ENOMEM; 6942 } 6943 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6944 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6945 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6946 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6947 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6948 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6952 6953 if (rdev->pm.dpm.voltage_response_time == 0) 6954 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6955 if (rdev->pm.dpm.backbias_response_time == 0) 6956 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6957 6958 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6959 0, false, ÷rs); 6960 if (ret) 6961 pi->ref_div = dividers.ref_div + 1; 6962 else 6963 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6964 6965 eg_pi->smu_uvd_hs = false; 6966 6967 pi->mclk_strobe_mode_threshold = 40000; 6968 if (si_is_special_1gb_platform(rdev)) 6969 pi->mclk_stutter_mode_threshold = 0; 6970 else 6971 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6972 pi->mclk_edc_enable_threshold = 40000; 6973 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6974 6975 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6976 6977 pi->voltage_control = 6978 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6979 VOLTAGE_OBJ_GPIO_LUT); 6980 if (!pi->voltage_control) { 6981 si_pi->voltage_control_svi2 = 6982 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6983 VOLTAGE_OBJ_SVID2); 6984 if (si_pi->voltage_control_svi2) 6985 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6986 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6987 } 6988 6989 pi->mvdd_control = 6990 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6991 VOLTAGE_OBJ_GPIO_LUT); 6992 6993 eg_pi->vddci_control = 6994 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6995 VOLTAGE_OBJ_GPIO_LUT); 6996 if (!eg_pi->vddci_control) 6997 si_pi->vddci_control_svi2 = 6998 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6999 VOLTAGE_OBJ_SVID2); 7000 7001 si_pi->vddc_phase_shed_control = 7002 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7003 VOLTAGE_OBJ_PHASE_LUT); 7004 7005 rv770_get_engine_memory_ss(rdev); 7006 7007 pi->asi = RV770_ASI_DFLT; 7008 pi->pasi = CYPRESS_HASI_DFLT; 7009 pi->vrc = SISLANDS_VRC_DFLT; 7010 7011 pi->gfx_clock_gating = true; 7012 7013 eg_pi->sclk_deep_sleep = true; 7014 si_pi->sclk_deep_sleep_above_low = false; 7015 7016 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7017 pi->thermal_protection = true; 7018 else 7019 pi->thermal_protection = false; 7020 7021 eg_pi->dynamic_ac_timing = true; 7022 7023 eg_pi->light_sleep = true; 7024 #if defined(CONFIG_ACPI) 7025 eg_pi->pcie_performance_request = 7026 radeon_acpi_is_pcie_performance_request_supported(rdev); 7027 #else 7028 eg_pi->pcie_performance_request = false; 7029 #endif 7030 7031 si_pi->sram_end = SMC_RAM_END; 7032 7033 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7034 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7035 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7036 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7037 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7038 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7039 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7040 7041 si_initialize_powertune_defaults(rdev); 7042 7043 /* make sure dc limits are valid */ 7044 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7045 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7046 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7047 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7048 7049 si_pi->fan_ctrl_is_in_default_mode = true; 7050 7051 return 0; 7052 } 7053 7054 void si_dpm_fini(struct radeon_device *rdev) 7055 { 7056 int i; 7057 7058 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7059 kfree(rdev->pm.dpm.ps[i].ps_priv); 7060 } 7061 kfree(rdev->pm.dpm.ps); 7062 kfree(rdev->pm.dpm.priv); 7063 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7064 r600_free_extended_power_table(rdev); 7065 } 7066 7067 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7068 struct seq_file *m) 7069 { 7070 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7071 struct radeon_ps *rps = &eg_pi->current_rps; 7072 struct ni_ps *ps = ni_get_ps(rps); 7073 struct rv7xx_pl *pl; 7074 u32 current_index = 7075 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7076 CURRENT_STATE_INDEX_SHIFT; 7077 7078 if (current_index >= ps->performance_level_count) { 7079 seq_printf(m, "invalid dpm profile %d\n", current_index); 7080 } else { 7081 pl = &ps->performance_levels[current_index]; 7082 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7083 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7084 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7085 } 7086 } 7087 7088 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7089 { 7090 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7091 struct radeon_ps *rps = &eg_pi->current_rps; 7092 struct ni_ps *ps = ni_get_ps(rps); 7093 struct rv7xx_pl *pl; 7094 u32 current_index = 7095 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7096 CURRENT_STATE_INDEX_SHIFT; 7097 7098 if (current_index >= ps->performance_level_count) { 7099 return 0; 7100 } else { 7101 pl = &ps->performance_levels[current_index]; 7102 return pl->sclk; 7103 } 7104 } 7105 7106 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7107 { 7108 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7109 struct radeon_ps *rps = &eg_pi->current_rps; 7110 struct ni_ps *ps = ni_get_ps(rps); 7111 struct rv7xx_pl *pl; 7112 u32 current_index = 7113 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7114 CURRENT_STATE_INDEX_SHIFT; 7115 7116 if (current_index >= ps->performance_level_count) { 7117 return 0; 7118 } else { 7119 pl = &ps->performance_levels[current_index]; 7120 return pl->mclk; 7121 } 7122 } 7123