1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "drmP.h" 25 #include "radeon.h" 26 #include "sid.h" 27 #include "r600_dpm.h" 28 #include "si_dpm.h" 29 #include "atom.h" 30 #include <linux/math64.h> 31 #include <linux/seq_file.h> 32 33 #define MC_CG_ARB_FREQ_F0 0x0a 34 #define MC_CG_ARB_FREQ_F1 0x0b 35 #define MC_CG_ARB_FREQ_F2 0x0c 36 #define MC_CG_ARB_FREQ_F3 0x0d 37 38 #define SMC_RAM_END 0x20000 39 40 #define DDR3_DRAM_ROWS 0x2000 41 42 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 43 44 static const struct si_cac_config_reg cac_weights_tahiti[] = 45 { 46 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 47 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 50 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 59 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 64 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 65 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 68 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 81 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 84 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 106 { 0xFFFFFFFF } 107 }; 108 109 static const struct si_cac_config_reg lcac_tahiti[] = 110 { 111 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 197 { 0xFFFFFFFF } 198 199 }; 200 201 static const struct si_cac_config_reg cac_override_tahiti[] = 202 { 203 { 0xFFFFFFFF } 204 }; 205 206 static const struct si_powertune_data powertune_data_tahiti = 207 { 208 ((1 << 16) | 27027), 209 6, 210 0, 211 4, 212 95, 213 { 214 0UL, 215 0UL, 216 4521550UL, 217 309631529UL, 218 -1270850L, 219 4513710L, 220 40 221 }, 222 595000000UL, 223 12, 224 { 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0 233 }, 234 true 235 }; 236 237 static const struct si_dte_data dte_data_tahiti = 238 { 239 { 1159409, 0, 0, 0, 0 }, 240 { 777, 0, 0, 0, 0 }, 241 2, 242 54000, 243 127000, 244 25, 245 2, 246 10, 247 13, 248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 249 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 251 85, 252 false 253 }; 254 255 static const struct si_dte_data dte_data_tahiti_le = 256 { 257 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 258 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 259 0x5, 260 0xAFC8, 261 0x64, 262 0x32, 263 1, 264 0, 265 0x10, 266 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 267 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 268 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 269 85, 270 true 271 }; 272 273 static const struct si_dte_data dte_data_tahiti_pro = 274 { 275 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 276 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 277 5, 278 45000, 279 100, 280 0xA, 281 1, 282 0, 283 0x10, 284 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 285 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 286 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 287 90, 288 true 289 }; 290 291 static const struct si_dte_data dte_data_new_zealand = 292 { 293 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 294 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 295 0x5, 296 0xAFC8, 297 0x69, 298 0x32, 299 1, 300 0, 301 0x10, 302 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 303 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 304 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 305 85, 306 true 307 }; 308 309 static const struct si_dte_data dte_data_aruba_pro = 310 { 311 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 312 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 313 5, 314 45000, 315 100, 316 0xA, 317 1, 318 0, 319 0x10, 320 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 321 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 322 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 323 90, 324 true 325 }; 326 327 static const struct si_dte_data dte_data_malta = 328 { 329 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 330 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 331 5, 332 45000, 333 100, 334 0xA, 335 1, 336 0, 337 0x10, 338 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 339 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 340 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 341 90, 342 true 343 }; 344 345 struct si_cac_config_reg cac_weights_pitcairn[] = 346 { 347 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 348 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 350 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 351 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 353 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 355 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 357 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 359 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 360 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 364 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 365 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 366 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 368 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 369 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 374 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 378 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 382 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 384 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 407 { 0xFFFFFFFF } 408 }; 409 410 static const struct si_cac_config_reg lcac_pitcairn[] = 411 { 412 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 413 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 415 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 417 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 419 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 421 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 423 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 425 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 427 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 429 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 431 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 433 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 435 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 437 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 439 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 441 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 443 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 445 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 451 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 453 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 455 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 457 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 459 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 463 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 465 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 467 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 471 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 473 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 475 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 477 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 479 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 481 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 485 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 487 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 489 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 491 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 493 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 497 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 498 { 0xFFFFFFFF } 499 }; 500 501 static const struct si_cac_config_reg cac_override_pitcairn[] = 502 { 503 { 0xFFFFFFFF } 504 }; 505 506 static const struct si_powertune_data powertune_data_pitcairn = 507 { 508 ((1 << 16) | 27027), 509 5, 510 0, 511 6, 512 100, 513 { 514 51600000UL, 515 1800000UL, 516 7194395UL, 517 309631529UL, 518 -1270850L, 519 4513710L, 520 100 521 }, 522 117830498UL, 523 12, 524 { 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0, 532 0 533 }, 534 true 535 }; 536 537 static const struct si_dte_data dte_data_pitcairn = 538 { 539 { 0, 0, 0, 0, 0 }, 540 { 0, 0, 0, 0, 0 }, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 0, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 551 0, 552 false 553 }; 554 555 static const struct si_dte_data dte_data_curacao_xt = 556 { 557 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 558 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 559 5, 560 45000, 561 100, 562 0xA, 563 1, 564 0, 565 0x10, 566 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 567 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 568 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 569 90, 570 true 571 }; 572 573 static const struct si_dte_data dte_data_curacao_pro = 574 { 575 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 576 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 577 5, 578 45000, 579 100, 580 0xA, 581 1, 582 0, 583 0x10, 584 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 585 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 586 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 587 90, 588 true 589 }; 590 591 static const struct si_dte_data dte_data_neptune_xt = 592 { 593 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 594 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 595 5, 596 45000, 597 100, 598 0xA, 599 1, 600 0, 601 0x10, 602 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 603 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 604 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 605 90, 606 true 607 }; 608 609 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 610 { 611 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 612 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 614 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 615 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 617 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 619 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 621 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 623 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 624 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 626 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 628 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 629 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 630 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 632 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 633 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 636 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 638 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 642 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 643 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 646 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 649 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 651 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 652 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 671 { 0xFFFFFFFF } 672 }; 673 674 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 675 { 676 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 677 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 679 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 680 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 682 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 684 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 686 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 688 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 689 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 691 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 693 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 694 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 695 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 697 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 698 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 701 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 703 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 707 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 708 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 711 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 714 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 716 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 717 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 736 { 0xFFFFFFFF } 737 }; 738 739 static const struct si_cac_config_reg cac_weights_heathrow[] = 740 { 741 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 742 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 744 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 745 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 747 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 749 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 751 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 753 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 754 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 756 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 758 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 759 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 760 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 762 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 763 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 766 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 768 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 772 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 773 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 776 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 779 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 781 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 782 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 801 { 0xFFFFFFFF } 802 }; 803 804 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 805 { 806 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 807 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 809 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 810 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 812 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 814 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 816 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 818 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 819 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 821 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 823 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 824 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 825 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 827 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 828 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 831 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 833 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 837 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 838 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 841 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 844 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 846 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 847 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 866 { 0xFFFFFFFF } 867 }; 868 869 static const struct si_cac_config_reg cac_weights_cape_verde[] = 870 { 871 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 872 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 874 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 875 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 877 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 879 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 881 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 883 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 884 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 886 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 888 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 889 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 890 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 892 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 893 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 896 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 898 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 902 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 903 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 906 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 909 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 911 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 912 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 931 { 0xFFFFFFFF } 932 }; 933 934 static const struct si_cac_config_reg lcac_cape_verde[] = 935 { 936 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 937 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 939 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 941 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 945 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 951 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 953 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 955 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 965 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 967 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 969 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 971 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 973 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 977 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 981 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0xFFFFFFFF } 991 }; 992 993 static const struct si_cac_config_reg cac_override_cape_verde[] = 994 { 995 { 0xFFFFFFFF } 996 }; 997 998 static const struct si_powertune_data powertune_data_cape_verde = 999 { 1000 ((1 << 16) | 0x6993), 1001 5, 1002 0, 1003 7, 1004 105, 1005 { 1006 0UL, 1007 0UL, 1008 7194395UL, 1009 309631529UL, 1010 -1270850L, 1011 4513710L, 1012 100 1013 }, 1014 117830498UL, 1015 12, 1016 { 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0, 1024 0 1025 }, 1026 true 1027 }; 1028 1029 static const struct si_dte_data dte_data_cape_verde = 1030 { 1031 { 0, 0, 0, 0, 0 }, 1032 { 0, 0, 0, 0, 0 }, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 0, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1043 0, 1044 false 1045 }; 1046 1047 static const struct si_dte_data dte_data_venus_xtx = 1048 { 1049 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1050 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1051 5, 1052 55000, 1053 0x69, 1054 0xA, 1055 1, 1056 0, 1057 0x3, 1058 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 90, 1062 true 1063 }; 1064 1065 static const struct si_dte_data dte_data_venus_xt = 1066 { 1067 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1068 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1069 5, 1070 55000, 1071 0x69, 1072 0xA, 1073 1, 1074 0, 1075 0x3, 1076 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 90, 1080 true 1081 }; 1082 1083 static const struct si_dte_data dte_data_venus_pro = 1084 { 1085 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1086 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1087 5, 1088 55000, 1089 0x69, 1090 0xA, 1091 1, 1092 0, 1093 0x3, 1094 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1097 90, 1098 true 1099 }; 1100 1101 struct si_cac_config_reg cac_weights_oland[] = 1102 { 1103 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1163 { 0xFFFFFFFF } 1164 }; 1165 1166 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1167 { 1168 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xFFFFFFFF } 1229 }; 1230 1231 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1232 { 1233 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xFFFFFFFF } 1294 }; 1295 1296 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1297 { 1298 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xFFFFFFFF } 1359 }; 1360 1361 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1362 { 1363 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xFFFFFFFF } 1424 }; 1425 1426 static const struct si_cac_config_reg lcac_oland[] = 1427 { 1428 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0xFFFFFFFF } 1471 }; 1472 1473 static const struct si_cac_config_reg lcac_mars_pro[] = 1474 { 1475 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0xFFFFFFFF } 1518 }; 1519 1520 static const struct si_cac_config_reg cac_override_oland[] = 1521 { 1522 { 0xFFFFFFFF } 1523 }; 1524 1525 static const struct si_powertune_data powertune_data_oland = 1526 { 1527 ((1 << 16) | 0x6993), 1528 5, 1529 0, 1530 7, 1531 105, 1532 { 1533 0UL, 1534 0UL, 1535 7194395UL, 1536 309631529UL, 1537 -1270850L, 1538 4513710L, 1539 100 1540 }, 1541 117830498UL, 1542 12, 1543 { 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0, 1551 0 1552 }, 1553 true 1554 }; 1555 1556 static const struct si_powertune_data powertune_data_mars_pro = 1557 { 1558 ((1 << 16) | 0x6993), 1559 5, 1560 0, 1561 7, 1562 105, 1563 { 1564 0UL, 1565 0UL, 1566 7194395UL, 1567 309631529UL, 1568 -1270850L, 1569 4513710L, 1570 100 1571 }, 1572 117830498UL, 1573 12, 1574 { 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0, 1582 0 1583 }, 1584 true 1585 }; 1586 1587 static const struct si_dte_data dte_data_oland = 1588 { 1589 { 0, 0, 0, 0, 0 }, 1590 { 0, 0, 0, 0, 0 }, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 0, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1601 0, 1602 false 1603 }; 1604 1605 static const struct si_dte_data dte_data_mars_pro = 1606 { 1607 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1608 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1609 5, 1610 55000, 1611 105, 1612 0xA, 1613 1, 1614 0, 1615 0x10, 1616 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1617 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1618 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1619 90, 1620 true 1621 }; 1622 1623 static const struct si_dte_data dte_data_sun_xt = 1624 { 1625 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1626 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1627 5, 1628 55000, 1629 105, 1630 0xA, 1631 1, 1632 0, 1633 0x10, 1634 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1635 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1636 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1637 90, 1638 true 1639 }; 1640 1641 1642 static const struct si_cac_config_reg cac_weights_hainan[] = 1643 { 1644 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1704 { 0xFFFFFFFF } 1705 }; 1706 1707 static const struct si_powertune_data powertune_data_hainan = 1708 { 1709 ((1 << 16) | 0x6993), 1710 5, 1711 0, 1712 9, 1713 105, 1714 { 1715 0UL, 1716 0UL, 1717 7194395UL, 1718 309631529UL, 1719 -1270850L, 1720 4513710L, 1721 100 1722 }, 1723 117830498UL, 1724 12, 1725 { 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0, 1733 0 1734 }, 1735 true 1736 }; 1737 1738 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1739 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1740 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1741 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1742 1743 static int si_populate_voltage_value(struct radeon_device *rdev, 1744 const struct atom_voltage_table *table, 1745 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1746 static int si_get_std_voltage_value(struct radeon_device *rdev, 1747 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1748 u16 *std_voltage); 1749 static int si_write_smc_soft_register(struct radeon_device *rdev, 1750 u16 reg_offset, u32 value); 1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1752 struct rv7xx_pl *pl, 1753 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1754 static int si_calculate_sclk_params(struct radeon_device *rdev, 1755 u32 engine_clock, 1756 SISLANDS_SMC_SCLK_VALUE *sclk); 1757 1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1759 { 1760 struct si_power_info *pi = rdev->pm.dpm.priv; 1761 1762 return pi; 1763 } 1764 1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1766 u16 v, s32 t, u32 ileakage, u32 *leakage) 1767 { 1768 s64 kt, kv, leakage_w, i_leakage, vddc; 1769 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1770 1771 i_leakage = drm_int2fixp(ileakage / 100); 1772 vddc = div64_s64(drm_int2fixp(v), 1000); 1773 temperature = div64_s64(drm_int2fixp(t), 1000); 1774 1775 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1776 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1777 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1778 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1779 t_ref = drm_int2fixp(coeff->t_ref); 1780 1781 kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)), 1782 drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref))); 1783 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1784 1785 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1786 1787 *leakage = drm_fixp2int(leakage_w * 1000); 1788 } 1789 1790 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1791 const struct ni_leakage_coeffients *coeff, 1792 u16 v, 1793 s32 t, 1794 u32 i_leakage, 1795 u32 *leakage) 1796 { 1797 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1798 } 1799 1800 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1801 const u32 fixed_kt, u16 v, 1802 u32 ileakage, u32 *leakage) 1803 { 1804 s64 kt, kv, leakage_w, i_leakage, vddc; 1805 1806 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1807 vddc = div64_s64(drm_int2fixp(v), 1000); 1808 1809 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1810 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1811 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1812 1813 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1814 1815 *leakage = drm_fixp2int(leakage_w * 1000); 1816 } 1817 1818 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1819 const struct ni_leakage_coeffients *coeff, 1820 const u32 fixed_kt, 1821 u16 v, 1822 u32 i_leakage, 1823 u32 *leakage) 1824 { 1825 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1826 } 1827 1828 1829 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1830 struct si_dte_data *dte_data) 1831 { 1832 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1833 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1834 u32 k = dte_data->k; 1835 u32 t_max = dte_data->max_t; 1836 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1837 u32 t_0 = dte_data->t0; 1838 u32 i; 1839 1840 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1841 dte_data->tdep_count = 3; 1842 1843 for (i = 0; i < k; i++) { 1844 dte_data->r[i] = 1845 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1846 (p_limit2 * (u32)100); 1847 } 1848 1849 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1850 1851 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1852 dte_data->tdep_r[i] = dte_data->r[4]; 1853 } 1854 } else { 1855 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1856 } 1857 } 1858 1859 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1860 { 1861 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1862 struct si_power_info *si_pi = si_get_pi(rdev); 1863 bool update_dte_from_pl2 = false; 1864 1865 if (rdev->family == CHIP_TAHITI) { 1866 si_pi->cac_weights = cac_weights_tahiti; 1867 si_pi->lcac_config = lcac_tahiti; 1868 si_pi->cac_override = cac_override_tahiti; 1869 si_pi->powertune_data = &powertune_data_tahiti; 1870 si_pi->dte_data = dte_data_tahiti; 1871 1872 switch (rdev->pdev->device) { 1873 case 0x6798: 1874 si_pi->dte_data.enable_dte_by_default = true; 1875 break; 1876 case 0x6799: 1877 si_pi->dte_data = dte_data_new_zealand; 1878 break; 1879 case 0x6790: 1880 case 0x6791: 1881 case 0x6792: 1882 case 0x679E: 1883 si_pi->dte_data = dte_data_aruba_pro; 1884 update_dte_from_pl2 = true; 1885 break; 1886 case 0x679B: 1887 si_pi->dte_data = dte_data_malta; 1888 update_dte_from_pl2 = true; 1889 break; 1890 case 0x679A: 1891 si_pi->dte_data = dte_data_tahiti_pro; 1892 update_dte_from_pl2 = true; 1893 break; 1894 default: 1895 if (si_pi->dte_data.enable_dte_by_default == true) 1896 DRM_ERROR("DTE is not enabled!\n"); 1897 break; 1898 } 1899 } else if (rdev->family == CHIP_PITCAIRN) { 1900 switch (rdev->pdev->device) { 1901 case 0x6810: 1902 case 0x6818: 1903 si_pi->cac_weights = cac_weights_pitcairn; 1904 si_pi->lcac_config = lcac_pitcairn; 1905 si_pi->cac_override = cac_override_pitcairn; 1906 si_pi->powertune_data = &powertune_data_pitcairn; 1907 si_pi->dte_data = dte_data_curacao_xt; 1908 update_dte_from_pl2 = true; 1909 break; 1910 case 0x6819: 1911 case 0x6811: 1912 si_pi->cac_weights = cac_weights_pitcairn; 1913 si_pi->lcac_config = lcac_pitcairn; 1914 si_pi->cac_override = cac_override_pitcairn; 1915 si_pi->powertune_data = &powertune_data_pitcairn; 1916 si_pi->dte_data = dte_data_curacao_pro; 1917 update_dte_from_pl2 = true; 1918 break; 1919 case 0x6800: 1920 case 0x6806: 1921 si_pi->cac_weights = cac_weights_pitcairn; 1922 si_pi->lcac_config = lcac_pitcairn; 1923 si_pi->cac_override = cac_override_pitcairn; 1924 si_pi->powertune_data = &powertune_data_pitcairn; 1925 si_pi->dte_data = dte_data_neptune_xt; 1926 update_dte_from_pl2 = true; 1927 break; 1928 default: 1929 si_pi->cac_weights = cac_weights_pitcairn; 1930 si_pi->lcac_config = lcac_pitcairn; 1931 si_pi->cac_override = cac_override_pitcairn; 1932 si_pi->powertune_data = &powertune_data_pitcairn; 1933 si_pi->dte_data = dte_data_pitcairn; 1934 } 1935 } else if (rdev->family == CHIP_VERDE) { 1936 si_pi->lcac_config = lcac_cape_verde; 1937 si_pi->cac_override = cac_override_cape_verde; 1938 si_pi->powertune_data = &powertune_data_cape_verde; 1939 1940 switch (rdev->pdev->device) { 1941 case 0x683B: 1942 case 0x683F: 1943 case 0x6829: 1944 si_pi->cac_weights = cac_weights_cape_verde_pro; 1945 si_pi->dte_data = dte_data_cape_verde; 1946 break; 1947 case 0x6825: 1948 case 0x6827: 1949 si_pi->cac_weights = cac_weights_heathrow; 1950 si_pi->dte_data = dte_data_cape_verde; 1951 break; 1952 case 0x6824: 1953 case 0x682D: 1954 si_pi->cac_weights = cac_weights_chelsea_xt; 1955 si_pi->dte_data = dte_data_cape_verde; 1956 break; 1957 case 0x682F: 1958 si_pi->cac_weights = cac_weights_chelsea_pro; 1959 si_pi->dte_data = dte_data_cape_verde; 1960 break; 1961 case 0x6820: 1962 si_pi->cac_weights = cac_weights_heathrow; 1963 si_pi->dte_data = dte_data_venus_xtx; 1964 break; 1965 case 0x6821: 1966 si_pi->cac_weights = cac_weights_heathrow; 1967 si_pi->dte_data = dte_data_venus_xt; 1968 break; 1969 case 0x6823: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_venus_pro; 1972 break; 1973 case 0x682B: 1974 si_pi->cac_weights = cac_weights_chelsea_pro; 1975 si_pi->dte_data = dte_data_venus_pro; 1976 break; 1977 default: 1978 si_pi->cac_weights = cac_weights_cape_verde; 1979 si_pi->dte_data = dte_data_cape_verde; 1980 break; 1981 } 1982 } else if (rdev->family == CHIP_OLAND) { 1983 switch (rdev->pdev->device) { 1984 case 0x6601: 1985 case 0x6621: 1986 case 0x6603: 1987 si_pi->cac_weights = cac_weights_mars_pro; 1988 si_pi->lcac_config = lcac_mars_pro; 1989 si_pi->cac_override = cac_override_oland; 1990 si_pi->powertune_data = &powertune_data_mars_pro; 1991 si_pi->dte_data = dte_data_mars_pro; 1992 update_dte_from_pl2 = true; 1993 break; 1994 case 0x6600: 1995 case 0x6606: 1996 case 0x6620: 1997 si_pi->cac_weights = cac_weights_mars_xt; 1998 si_pi->lcac_config = lcac_mars_pro; 1999 si_pi->cac_override = cac_override_oland; 2000 si_pi->powertune_data = &powertune_data_mars_pro; 2001 si_pi->dte_data = dte_data_mars_pro; 2002 update_dte_from_pl2 = true; 2003 break; 2004 case 0x6611: 2005 si_pi->cac_weights = cac_weights_oland_pro; 2006 si_pi->lcac_config = lcac_mars_pro; 2007 si_pi->cac_override = cac_override_oland; 2008 si_pi->powertune_data = &powertune_data_mars_pro; 2009 si_pi->dte_data = dte_data_mars_pro; 2010 update_dte_from_pl2 = true; 2011 break; 2012 case 0x6610: 2013 si_pi->cac_weights = cac_weights_oland_xt; 2014 si_pi->lcac_config = lcac_mars_pro; 2015 si_pi->cac_override = cac_override_oland; 2016 si_pi->powertune_data = &powertune_data_mars_pro; 2017 si_pi->dte_data = dte_data_mars_pro; 2018 update_dte_from_pl2 = true; 2019 break; 2020 default: 2021 si_pi->cac_weights = cac_weights_oland; 2022 si_pi->lcac_config = lcac_oland; 2023 si_pi->cac_override = cac_override_oland; 2024 si_pi->powertune_data = &powertune_data_oland; 2025 si_pi->dte_data = dte_data_oland; 2026 break; 2027 } 2028 } else if (rdev->family == CHIP_HAINAN) { 2029 si_pi->cac_weights = cac_weights_hainan; 2030 si_pi->lcac_config = lcac_oland; 2031 si_pi->cac_override = cac_override_oland; 2032 si_pi->powertune_data = &powertune_data_hainan; 2033 si_pi->dte_data = dte_data_sun_xt; 2034 update_dte_from_pl2 = true; 2035 } else { 2036 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2037 return; 2038 } 2039 2040 ni_pi->enable_power_containment = false; 2041 ni_pi->enable_cac = false; 2042 ni_pi->enable_sq_ramping = false; 2043 si_pi->enable_dte = false; 2044 2045 if (si_pi->powertune_data->enable_powertune_by_default) { 2046 ni_pi->enable_power_containment= true; 2047 ni_pi->enable_cac = true; 2048 if (si_pi->dte_data.enable_dte_by_default) { 2049 si_pi->enable_dte = true; 2050 if (update_dte_from_pl2) 2051 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2052 2053 } 2054 ni_pi->enable_sq_ramping = true; 2055 } 2056 2057 ni_pi->driver_calculate_cac_leakage = true; 2058 ni_pi->cac_configuration_required = true; 2059 2060 if (ni_pi->cac_configuration_required) { 2061 ni_pi->support_cac_long_term_average = true; 2062 si_pi->dyn_powertune_data.l2_lta_window_size = 2063 si_pi->powertune_data->l2_lta_window_size_default; 2064 si_pi->dyn_powertune_data.lts_truncate = 2065 si_pi->powertune_data->lts_truncate_default; 2066 } else { 2067 ni_pi->support_cac_long_term_average = false; 2068 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2069 si_pi->dyn_powertune_data.lts_truncate = 0; 2070 } 2071 2072 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2073 } 2074 2075 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2076 { 2077 return 1; 2078 } 2079 2080 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2081 { 2082 u32 xclk; 2083 u32 wintime; 2084 u32 cac_window; 2085 u32 cac_window_size; 2086 2087 xclk = radeon_get_xclk(rdev); 2088 2089 if (xclk == 0) 2090 return 0; 2091 2092 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2093 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2094 2095 wintime = (cac_window_size * 100) / xclk; 2096 2097 return wintime; 2098 } 2099 2100 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2101 { 2102 return power_in_watts; 2103 } 2104 2105 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2106 bool adjust_polarity, 2107 u32 tdp_adjustment, 2108 u32 *tdp_limit, 2109 u32 *near_tdp_limit) 2110 { 2111 u32 adjustment_delta, max_tdp_limit; 2112 2113 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2114 return -EINVAL; 2115 2116 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2117 2118 if (adjust_polarity) { 2119 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2120 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2121 } else { 2122 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2123 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2124 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2126 else 2127 *near_tdp_limit = 0; 2128 } 2129 2130 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2131 return -EINVAL; 2132 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2133 return -EINVAL; 2134 2135 return 0; 2136 } 2137 2138 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2139 struct radeon_ps *radeon_state) 2140 { 2141 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2142 struct si_power_info *si_pi = si_get_pi(rdev); 2143 2144 if (ni_pi->enable_power_containment) { 2145 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2146 PP_SIslands_PAPMParameters *papm_parm; 2147 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2148 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2149 u32 tdp_limit; 2150 u32 near_tdp_limit; 2151 int ret; 2152 2153 if (scaling_factor == 0) 2154 return -EINVAL; 2155 2156 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2157 2158 ret = si_calculate_adjusted_tdp_limits(rdev, 2159 false, /* ??? */ 2160 rdev->pm.dpm.tdp_adjustment, 2161 &tdp_limit, 2162 &near_tdp_limit); 2163 if (ret) 2164 return ret; 2165 2166 smc_table->dpm2Params.TDPLimit = 2167 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2168 smc_table->dpm2Params.NearTDPLimit = 2169 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2170 smc_table->dpm2Params.SafePowerLimit = 2171 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2172 2173 ret = si_copy_bytes_to_smc(rdev, 2174 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2175 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2176 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2177 sizeof(u32) * 3, 2178 si_pi->sram_end); 2179 if (ret) 2180 return ret; 2181 2182 if (si_pi->enable_ppm) { 2183 papm_parm = &si_pi->papm_parm; 2184 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2185 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2186 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2187 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2188 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2189 papm_parm->PlatformPowerLimit = 0xffffffff; 2190 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2191 2192 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2193 (u8 *)papm_parm, 2194 sizeof(PP_SIslands_PAPMParameters), 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 } 2199 } 2200 return 0; 2201 } 2202 2203 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2204 struct radeon_ps *radeon_state) 2205 { 2206 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2207 struct si_power_info *si_pi = si_get_pi(rdev); 2208 2209 if (ni_pi->enable_power_containment) { 2210 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2211 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2212 int ret; 2213 2214 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2215 2216 smc_table->dpm2Params.NearTDPLimit = 2217 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2218 smc_table->dpm2Params.SafePowerLimit = 2219 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2220 2221 ret = si_copy_bytes_to_smc(rdev, 2222 (si_pi->state_table_start + 2223 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2224 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2225 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2226 sizeof(u32) * 2, 2227 si_pi->sram_end); 2228 if (ret) 2229 return ret; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2236 const u16 prev_std_vddc, 2237 const u16 curr_std_vddc) 2238 { 2239 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2240 u64 prev_vddc = (u64)prev_std_vddc; 2241 u64 curr_vddc = (u64)curr_std_vddc; 2242 u64 pwr_efficiency_ratio, n, d; 2243 2244 if ((prev_vddc == 0) || (curr_vddc == 0)) 2245 return 0; 2246 2247 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2248 d = prev_vddc * prev_vddc; 2249 pwr_efficiency_ratio = div64_u64(n, d); 2250 2251 if (pwr_efficiency_ratio > (u64)0xFFFF) 2252 return 0; 2253 2254 return (u16)pwr_efficiency_ratio; 2255 } 2256 2257 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2258 struct radeon_ps *radeon_state) 2259 { 2260 struct si_power_info *si_pi = si_get_pi(rdev); 2261 2262 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2263 radeon_state->vclk && radeon_state->dclk) 2264 return true; 2265 2266 return false; 2267 } 2268 2269 static int si_populate_power_containment_values(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state, 2271 SISLANDS_SMC_SWSTATE *smc_state) 2272 { 2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2274 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2275 struct ni_ps *state = ni_get_ps(radeon_state); 2276 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2277 u32 prev_sclk; 2278 u32 max_sclk; 2279 u32 min_sclk; 2280 u16 prev_std_vddc; 2281 u16 curr_std_vddc; 2282 int i; 2283 u16 pwr_efficiency_ratio; 2284 u8 max_ps_percent; 2285 bool disable_uvd_power_tune; 2286 int ret; 2287 2288 if (ni_pi->enable_power_containment == false) 2289 return 0; 2290 2291 if (state->performance_level_count == 0) 2292 return -EINVAL; 2293 2294 if (smc_state->levelCount != state->performance_level_count) 2295 return -EINVAL; 2296 2297 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2298 2299 smc_state->levels[0].dpm2.MaxPS = 0; 2300 smc_state->levels[0].dpm2.NearTDPDec = 0; 2301 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2302 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2304 2305 for (i = 1; i < state->performance_level_count; i++) { 2306 prev_sclk = state->performance_levels[i-1].sclk; 2307 max_sclk = state->performance_levels[i].sclk; 2308 if (i == 1) 2309 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2310 else 2311 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2312 2313 if (prev_sclk > max_sclk) 2314 return -EINVAL; 2315 2316 if ((max_ps_percent == 0) || 2317 (prev_sclk == max_sclk) || 2318 disable_uvd_power_tune) { 2319 min_sclk = max_sclk; 2320 } else if (i == 1) { 2321 min_sclk = prev_sclk; 2322 } else { 2323 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2324 } 2325 2326 if (min_sclk < state->performance_levels[0].sclk) 2327 min_sclk = state->performance_levels[0].sclk; 2328 2329 if (min_sclk == 0) 2330 return -EINVAL; 2331 2332 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2333 state->performance_levels[i-1].vddc, &vddc); 2334 if (ret) 2335 return ret; 2336 2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2338 if (ret) 2339 return ret; 2340 2341 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2342 state->performance_levels[i].vddc, &vddc); 2343 if (ret) 2344 return ret; 2345 2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2347 if (ret) 2348 return ret; 2349 2350 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2351 prev_std_vddc, curr_std_vddc); 2352 2353 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2358 } 2359 2360 return 0; 2361 } 2362 2363 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2364 struct radeon_ps *radeon_state, 2365 SISLANDS_SMC_SWSTATE *smc_state) 2366 { 2367 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2368 struct ni_ps *state = ni_get_ps(radeon_state); 2369 u32 sq_power_throttle, sq_power_throttle2; 2370 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2371 int i; 2372 2373 if (state->performance_level_count == 0) 2374 return -EINVAL; 2375 2376 if (smc_state->levelCount != state->performance_level_count) 2377 return -EINVAL; 2378 2379 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2380 return -EINVAL; 2381 2382 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2383 enable_sq_ramping = false; 2384 2385 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2386 enable_sq_ramping = false; 2387 2388 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2389 enable_sq_ramping = false; 2390 2391 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2392 enable_sq_ramping = false; 2393 2394 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 for (i = 0; i < state->performance_level_count; i++) { 2398 sq_power_throttle = 0; 2399 sq_power_throttle2 = 0; 2400 2401 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2402 enable_sq_ramping) { 2403 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2404 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2405 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2406 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2407 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2408 } else { 2409 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2410 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2411 } 2412 2413 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2414 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2415 } 2416 2417 return 0; 2418 } 2419 2420 static int si_enable_power_containment(struct radeon_device *rdev, 2421 struct radeon_ps *radeon_new_state, 2422 bool enable) 2423 { 2424 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2425 PPSMC_Result smc_result; 2426 int ret = 0; 2427 2428 if (ni_pi->enable_power_containment) { 2429 if (enable) { 2430 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2431 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2432 if (smc_result != PPSMC_Result_OK) { 2433 ret = -EINVAL; 2434 ni_pi->pc_enabled = false; 2435 } else { 2436 ni_pi->pc_enabled = true; 2437 } 2438 } 2439 } else { 2440 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2441 if (smc_result != PPSMC_Result_OK) 2442 ret = -EINVAL; 2443 ni_pi->pc_enabled = false; 2444 } 2445 } 2446 2447 return ret; 2448 } 2449 2450 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2451 { 2452 struct si_power_info *si_pi = si_get_pi(rdev); 2453 int ret = 0; 2454 struct si_dte_data *dte_data = &si_pi->dte_data; 2455 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2456 u32 table_size; 2457 u8 tdep_count; 2458 u32 i; 2459 2460 if (dte_data == NULL) 2461 si_pi->enable_dte = false; 2462 2463 if (si_pi->enable_dte == false) 2464 return 0; 2465 2466 if (dte_data->k <= 0) 2467 return -EINVAL; 2468 2469 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2470 if (dte_tables == NULL) { 2471 si_pi->enable_dte = false; 2472 return -ENOMEM; 2473 } 2474 2475 table_size = dte_data->k; 2476 2477 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2478 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2479 2480 tdep_count = dte_data->tdep_count; 2481 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2482 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2483 2484 dte_tables->K = cpu_to_be32(table_size); 2485 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2486 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2487 dte_tables->WindowSize = dte_data->window_size; 2488 dte_tables->temp_select = dte_data->temp_select; 2489 dte_tables->DTE_mode = dte_data->dte_mode; 2490 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2491 2492 if (tdep_count > 0) 2493 table_size--; 2494 2495 for (i = 0; i < table_size; i++) { 2496 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2497 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2498 } 2499 2500 dte_tables->Tdep_count = tdep_count; 2501 2502 for (i = 0; i < (u32)tdep_count; i++) { 2503 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2504 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2505 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2506 } 2507 2508 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2509 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2510 kfree(dte_tables); 2511 2512 return ret; 2513 } 2514 2515 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2516 u16 *max, u16 *min) 2517 { 2518 struct si_power_info *si_pi = si_get_pi(rdev); 2519 struct radeon_cac_leakage_table *table = 2520 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2521 u32 i; 2522 u32 v0_loadline; 2523 2524 2525 if (table == NULL) 2526 return -EINVAL; 2527 2528 *max = 0; 2529 *min = 0xFFFF; 2530 2531 for (i = 0; i < table->count; i++) { 2532 if (table->entries[i].vddc > *max) 2533 *max = table->entries[i].vddc; 2534 if (table->entries[i].vddc < *min) 2535 *min = table->entries[i].vddc; 2536 } 2537 2538 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2539 return -EINVAL; 2540 2541 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2542 2543 if (v0_loadline > 0xFFFFUL) 2544 return -EINVAL; 2545 2546 *min = (u16)v0_loadline; 2547 2548 if ((*min > *max) || (*max == 0) || (*min == 0)) 2549 return -EINVAL; 2550 2551 return 0; 2552 } 2553 2554 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2555 { 2556 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2557 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2558 } 2559 2560 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2561 PP_SIslands_CacConfig *cac_tables, 2562 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2563 u16 t0, u16 t_step) 2564 { 2565 struct si_power_info *si_pi = si_get_pi(rdev); 2566 u32 leakage; 2567 unsigned int i, j; 2568 s32 t; 2569 u32 smc_leakage; 2570 u32 scaling_factor; 2571 u16 voltage; 2572 2573 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2574 2575 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2576 t = (1000 * (i * t_step + t0)); 2577 2578 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2579 voltage = vddc_max - (vddc_step * j); 2580 2581 si_calculate_leakage_for_v_and_t(rdev, 2582 &si_pi->powertune_data->leakage_coefficients, 2583 voltage, 2584 t, 2585 si_pi->dyn_powertune_data.cac_leakage, 2586 &leakage); 2587 2588 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2589 2590 if (smc_leakage > 0xFFFF) 2591 smc_leakage = 0xFFFF; 2592 2593 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2594 cpu_to_be16((u16)smc_leakage); 2595 } 2596 } 2597 return 0; 2598 } 2599 2600 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2601 PP_SIslands_CacConfig *cac_tables, 2602 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2603 { 2604 struct si_power_info *si_pi = si_get_pi(rdev); 2605 u32 leakage; 2606 unsigned int i, j; 2607 u32 smc_leakage; 2608 u32 scaling_factor; 2609 u16 voltage; 2610 2611 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2612 2613 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2614 voltage = vddc_max - (vddc_step * j); 2615 2616 si_calculate_leakage_for_v(rdev, 2617 &si_pi->powertune_data->leakage_coefficients, 2618 si_pi->powertune_data->fixed_kt, 2619 voltage, 2620 si_pi->dyn_powertune_data.cac_leakage, 2621 &leakage); 2622 2623 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2624 2625 if (smc_leakage > 0xFFFF) 2626 smc_leakage = 0xFFFF; 2627 2628 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2629 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2630 cpu_to_be16((u16)smc_leakage); 2631 } 2632 return 0; 2633 } 2634 2635 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2636 { 2637 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2638 struct si_power_info *si_pi = si_get_pi(rdev); 2639 PP_SIslands_CacConfig *cac_tables = NULL; 2640 u16 vddc_max, vddc_min, vddc_step; 2641 u16 t0, t_step; 2642 u32 load_line_slope, reg; 2643 int ret = 0; 2644 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2645 2646 if (ni_pi->enable_cac == false) 2647 return 0; 2648 2649 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2650 if (!cac_tables) 2651 return -ENOMEM; 2652 2653 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2654 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2655 WREG32(CG_CAC_CTRL, reg); 2656 2657 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2658 si_pi->dyn_powertune_data.dc_pwr_value = 2659 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2660 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2661 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2662 2663 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2664 2665 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2666 if (ret) 2667 goto done_free; 2668 2669 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2670 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2671 t_step = 4; 2672 t0 = 60; 2673 2674 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2675 ret = si_init_dte_leakage_table(rdev, cac_tables, 2676 vddc_max, vddc_min, vddc_step, 2677 t0, t_step); 2678 else 2679 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2680 vddc_max, vddc_min, vddc_step); 2681 if (ret) 2682 goto done_free; 2683 2684 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2685 2686 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2687 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2688 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2689 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2690 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2691 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2692 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2693 cac_tables->calculation_repeats = cpu_to_be32(2); 2694 cac_tables->dc_cac = cpu_to_be32(0); 2695 cac_tables->log2_PG_LKG_SCALE = 12; 2696 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2697 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2698 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2699 2700 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2701 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2702 2703 if (ret) 2704 goto done_free; 2705 2706 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2707 2708 done_free: 2709 if (ret) { 2710 ni_pi->enable_cac = false; 2711 ni_pi->enable_power_containment = false; 2712 } 2713 2714 kfree(cac_tables); 2715 2716 return 0; 2717 } 2718 2719 static int si_program_cac_config_registers(struct radeon_device *rdev, 2720 const struct si_cac_config_reg *cac_config_regs) 2721 { 2722 const struct si_cac_config_reg *config_regs = cac_config_regs; 2723 u32 data = 0, offset; 2724 2725 if (!config_regs) 2726 return -EINVAL; 2727 2728 while (config_regs->offset != 0xFFFFFFFF) { 2729 switch (config_regs->type) { 2730 case SISLANDS_CACCONFIG_CGIND: 2731 offset = SMC_CG_IND_START + config_regs->offset; 2732 if (offset < SMC_CG_IND_END) 2733 data = RREG32_SMC(offset); 2734 break; 2735 default: 2736 data = RREG32(config_regs->offset << 2); 2737 break; 2738 } 2739 2740 data &= ~config_regs->mask; 2741 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2742 2743 switch (config_regs->type) { 2744 case SISLANDS_CACCONFIG_CGIND: 2745 offset = SMC_CG_IND_START + config_regs->offset; 2746 if (offset < SMC_CG_IND_END) 2747 WREG32_SMC(offset, data); 2748 break; 2749 default: 2750 WREG32(config_regs->offset << 2, data); 2751 break; 2752 } 2753 config_regs++; 2754 } 2755 return 0; 2756 } 2757 2758 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2759 { 2760 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2761 struct si_power_info *si_pi = si_get_pi(rdev); 2762 int ret; 2763 2764 if ((ni_pi->enable_cac == false) || 2765 (ni_pi->cac_configuration_required == false)) 2766 return 0; 2767 2768 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2769 if (ret) 2770 return ret; 2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2772 if (ret) 2773 return ret; 2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2775 if (ret) 2776 return ret; 2777 2778 return 0; 2779 } 2780 2781 static int si_enable_smc_cac(struct radeon_device *rdev, 2782 struct radeon_ps *radeon_new_state, 2783 bool enable) 2784 { 2785 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2786 struct si_power_info *si_pi = si_get_pi(rdev); 2787 PPSMC_Result smc_result; 2788 int ret = 0; 2789 2790 if (ni_pi->enable_cac) { 2791 if (enable) { 2792 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2793 if (ni_pi->support_cac_long_term_average) { 2794 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2795 if (smc_result != PPSMC_Result_OK) 2796 ni_pi->support_cac_long_term_average = false; 2797 } 2798 2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2800 if (smc_result != PPSMC_Result_OK) { 2801 ret = -EINVAL; 2802 ni_pi->cac_enabled = false; 2803 } else { 2804 ni_pi->cac_enabled = true; 2805 } 2806 2807 if (si_pi->enable_dte) { 2808 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2809 if (smc_result != PPSMC_Result_OK) 2810 ret = -EINVAL; 2811 } 2812 } 2813 } else if (ni_pi->cac_enabled) { 2814 if (si_pi->enable_dte) 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2816 2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2818 2819 ni_pi->cac_enabled = false; 2820 2821 if (ni_pi->support_cac_long_term_average) 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2823 } 2824 } 2825 return ret; 2826 } 2827 2828 static int si_init_smc_spll_table(struct radeon_device *rdev) 2829 { 2830 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2831 struct si_power_info *si_pi = si_get_pi(rdev); 2832 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2833 SISLANDS_SMC_SCLK_VALUE sclk_params; 2834 u32 fb_div, p_div; 2835 u32 clk_s, clk_v; 2836 u32 sclk = 0; 2837 int ret = 0; 2838 u32 tmp; 2839 int i; 2840 2841 if (si_pi->spll_table_start == 0) 2842 return -EINVAL; 2843 2844 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2845 if (spll_table == NULL) 2846 return -ENOMEM; 2847 2848 for (i = 0; i < 256; i++) { 2849 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2850 if (ret) 2851 break; 2852 2853 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2854 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2855 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2856 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2857 2858 fb_div &= ~0x00001FFF; 2859 fb_div >>= 1; 2860 clk_v >>= 6; 2861 2862 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2863 ret = -EINVAL; 2864 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2865 ret = -EINVAL; 2866 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2867 ret = -EINVAL; 2868 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2869 ret = -EINVAL; 2870 2871 if (ret) 2872 break; 2873 2874 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2875 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2876 spll_table->freq[i] = cpu_to_be32(tmp); 2877 2878 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2879 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2880 spll_table->ss[i] = cpu_to_be32(tmp); 2881 2882 sclk += 512; 2883 } 2884 2885 2886 if (!ret) 2887 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2888 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2889 si_pi->sram_end); 2890 2891 if (ret) 2892 ni_pi->enable_power_containment = false; 2893 2894 kfree(spll_table); 2895 2896 return ret; 2897 } 2898 2899 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2900 struct radeon_ps *rps) 2901 { 2902 struct ni_ps *ps = ni_get_ps(rps); 2903 struct radeon_clock_and_voltage_limits *max_limits; 2904 bool disable_mclk_switching; 2905 u32 mclk, sclk; 2906 u16 vddc, vddci; 2907 int i; 2908 2909 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2910 ni_dpm_vblank_too_short(rdev)) 2911 disable_mclk_switching = true; 2912 else 2913 disable_mclk_switching = false; 2914 2915 if (rdev->pm.dpm.ac_power) 2916 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2917 else 2918 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2919 2920 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2921 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2922 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2923 } 2924 if (rdev->pm.dpm.ac_power == false) { 2925 for (i = 0; i < ps->performance_level_count; i++) { 2926 if (ps->performance_levels[i].mclk > max_limits->mclk) 2927 ps->performance_levels[i].mclk = max_limits->mclk; 2928 if (ps->performance_levels[i].sclk > max_limits->sclk) 2929 ps->performance_levels[i].sclk = max_limits->sclk; 2930 if (ps->performance_levels[i].vddc > max_limits->vddc) 2931 ps->performance_levels[i].vddc = max_limits->vddc; 2932 if (ps->performance_levels[i].vddci > max_limits->vddci) 2933 ps->performance_levels[i].vddci = max_limits->vddci; 2934 } 2935 } 2936 2937 /* XXX validate the min clocks required for display */ 2938 2939 if (disable_mclk_switching) { 2940 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 2941 sclk = ps->performance_levels[0].sclk; 2942 vddc = ps->performance_levels[0].vddc; 2943 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 2944 } else { 2945 sclk = ps->performance_levels[0].sclk; 2946 mclk = ps->performance_levels[0].mclk; 2947 vddc = ps->performance_levels[0].vddc; 2948 vddci = ps->performance_levels[0].vddci; 2949 } 2950 2951 /* adjusted low state */ 2952 ps->performance_levels[0].sclk = sclk; 2953 ps->performance_levels[0].mclk = mclk; 2954 ps->performance_levels[0].vddc = vddc; 2955 ps->performance_levels[0].vddci = vddci; 2956 2957 for (i = 1; i < ps->performance_level_count; i++) { 2958 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 2959 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 2960 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 2961 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 2962 } 2963 2964 if (disable_mclk_switching) { 2965 mclk = ps->performance_levels[0].mclk; 2966 for (i = 1; i < ps->performance_level_count; i++) { 2967 if (mclk < ps->performance_levels[i].mclk) 2968 mclk = ps->performance_levels[i].mclk; 2969 } 2970 for (i = 0; i < ps->performance_level_count; i++) { 2971 ps->performance_levels[i].mclk = mclk; 2972 ps->performance_levels[i].vddci = vddci; 2973 } 2974 } else { 2975 for (i = 1; i < ps->performance_level_count; i++) { 2976 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 2977 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 2978 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 2979 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 2980 } 2981 } 2982 2983 for (i = 0; i < ps->performance_level_count; i++) 2984 btc_adjust_clock_combinations(rdev, max_limits, 2985 &ps->performance_levels[i]); 2986 2987 for (i = 0; i < ps->performance_level_count; i++) { 2988 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2989 ps->performance_levels[i].sclk, 2990 max_limits->vddc, &ps->performance_levels[i].vddc); 2991 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2992 ps->performance_levels[i].mclk, 2993 max_limits->vddci, &ps->performance_levels[i].vddci); 2994 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 2995 ps->performance_levels[i].mclk, 2996 max_limits->vddc, &ps->performance_levels[i].vddc); 2997 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 2998 rdev->clock.current_dispclk, 2999 max_limits->vddc, &ps->performance_levels[i].vddc); 3000 } 3001 3002 for (i = 0; i < ps->performance_level_count; i++) { 3003 btc_apply_voltage_delta_rules(rdev, 3004 max_limits->vddc, max_limits->vddci, 3005 &ps->performance_levels[i].vddc, 3006 &ps->performance_levels[i].vddci); 3007 } 3008 3009 ps->dc_compatible = true; 3010 for (i = 0; i < ps->performance_level_count; i++) { 3011 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3012 ps->dc_compatible = false; 3013 } 3014 3015 } 3016 3017 #if 0 3018 static int si_read_smc_soft_register(struct radeon_device *rdev, 3019 u16 reg_offset, u32 *value) 3020 { 3021 struct si_power_info *si_pi = si_get_pi(rdev); 3022 3023 return si_read_smc_sram_dword(rdev, 3024 si_pi->soft_regs_start + reg_offset, value, 3025 si_pi->sram_end); 3026 } 3027 #endif 3028 3029 static int si_write_smc_soft_register(struct radeon_device *rdev, 3030 u16 reg_offset, u32 value) 3031 { 3032 struct si_power_info *si_pi = si_get_pi(rdev); 3033 3034 return si_write_smc_sram_dword(rdev, 3035 si_pi->soft_regs_start + reg_offset, 3036 value, si_pi->sram_end); 3037 } 3038 3039 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3040 { 3041 bool ret = false; 3042 u32 tmp, width, row, column, bank, density; 3043 bool is_memory_gddr5, is_special; 3044 3045 tmp = RREG32(MC_SEQ_MISC0); 3046 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3047 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3048 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3049 3050 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3051 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3052 3053 tmp = RREG32(MC_ARB_RAMCFG); 3054 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3055 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3056 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3057 3058 density = (1 << (row + column - 20 + bank)) * width; 3059 3060 if ((rdev->pdev->device == 0x6819) && 3061 is_memory_gddr5 && is_special && (density == 0x400)) 3062 ret = true; 3063 3064 return ret; 3065 } 3066 3067 static void si_get_leakage_vddc(struct radeon_device *rdev) 3068 { 3069 struct si_power_info *si_pi = si_get_pi(rdev); 3070 u16 vddc, count = 0; 3071 int i, ret; 3072 3073 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3074 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3075 3076 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3077 si_pi->leakage_voltage.entries[count].voltage = vddc; 3078 si_pi->leakage_voltage.entries[count].leakage_index = 3079 SISLANDS_LEAKAGE_INDEX0 + i; 3080 count++; 3081 } 3082 } 3083 si_pi->leakage_voltage.count = count; 3084 } 3085 3086 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3087 u32 index, u16 *leakage_voltage) 3088 { 3089 struct si_power_info *si_pi = si_get_pi(rdev); 3090 int i; 3091 3092 if (leakage_voltage == NULL) 3093 return -EINVAL; 3094 3095 if ((index & 0xff00) != 0xff00) 3096 return -EINVAL; 3097 3098 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3099 return -EINVAL; 3100 3101 if (index < SISLANDS_LEAKAGE_INDEX0) 3102 return -EINVAL; 3103 3104 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3105 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3106 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3107 return 0; 3108 } 3109 } 3110 return -EAGAIN; 3111 } 3112 3113 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3114 { 3115 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3116 bool want_thermal_protection; 3117 enum radeon_dpm_event_src dpm_event_src; 3118 3119 switch (sources) { 3120 case 0: 3121 default: 3122 want_thermal_protection = false; 3123 break; 3124 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3125 want_thermal_protection = true; 3126 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3127 break; 3128 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3129 want_thermal_protection = true; 3130 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3131 break; 3132 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3133 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3134 want_thermal_protection = true; 3135 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3136 break; 3137 } 3138 3139 if (want_thermal_protection) { 3140 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3141 if (pi->thermal_protection) 3142 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3143 } else { 3144 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3145 } 3146 } 3147 3148 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3149 enum radeon_dpm_auto_throttle_src source, 3150 bool enable) 3151 { 3152 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3153 3154 if (enable) { 3155 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3156 pi->active_auto_throttle_sources |= 1 << source; 3157 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3158 } 3159 } else { 3160 if (pi->active_auto_throttle_sources & (1 << source)) { 3161 pi->active_auto_throttle_sources &= ~(1 << source); 3162 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3163 } 3164 } 3165 } 3166 3167 static void si_start_dpm(struct radeon_device *rdev) 3168 { 3169 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3170 } 3171 3172 static void si_stop_dpm(struct radeon_device *rdev) 3173 { 3174 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3175 } 3176 3177 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3178 { 3179 if (enable) 3180 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3181 else 3182 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3183 3184 } 3185 3186 #if 0 3187 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3188 u32 thermal_level) 3189 { 3190 PPSMC_Result ret; 3191 3192 if (thermal_level == 0) { 3193 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3194 if (ret == PPSMC_Result_OK) 3195 return 0; 3196 else 3197 return -EINVAL; 3198 } 3199 return 0; 3200 } 3201 3202 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3203 { 3204 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3205 } 3206 #endif 3207 3208 #if 0 3209 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3210 { 3211 if (ac_power) 3212 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3213 0 : -EINVAL; 3214 3215 return 0; 3216 } 3217 #endif 3218 3219 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3220 PPSMC_Msg msg, u32 parameter) 3221 { 3222 WREG32(SMC_SCRATCH0, parameter); 3223 return si_send_msg_to_smc(rdev, msg); 3224 } 3225 3226 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3227 { 3228 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3229 return -EINVAL; 3230 3231 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3232 0 : -EINVAL; 3233 } 3234 3235 int si_dpm_force_performance_level(struct radeon_device *rdev, 3236 enum radeon_dpm_forced_level level) 3237 { 3238 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3239 struct ni_ps *ps = ni_get_ps(rps); 3240 u32 levels; 3241 3242 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3243 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3244 return -EINVAL; 3245 3246 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3247 return -EINVAL; 3248 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3249 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3250 return -EINVAL; 3251 3252 levels = ps->performance_level_count - 1; 3253 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3254 return -EINVAL; 3255 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3256 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3257 return -EINVAL; 3258 3259 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) 3260 return -EINVAL; 3261 } 3262 3263 rdev->pm.dpm.forced_level = level; 3264 3265 return 0; 3266 } 3267 3268 static int si_set_boot_state(struct radeon_device *rdev) 3269 { 3270 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3271 0 : -EINVAL; 3272 } 3273 3274 static int si_set_sw_state(struct radeon_device *rdev) 3275 { 3276 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3277 0 : -EINVAL; 3278 } 3279 3280 static int si_halt_smc(struct radeon_device *rdev) 3281 { 3282 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3283 return -EINVAL; 3284 3285 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3286 0 : -EINVAL; 3287 } 3288 3289 static int si_resume_smc(struct radeon_device *rdev) 3290 { 3291 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3292 return -EINVAL; 3293 3294 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3295 0 : -EINVAL; 3296 } 3297 3298 static void si_dpm_start_smc(struct radeon_device *rdev) 3299 { 3300 si_program_jump_on_start(rdev); 3301 si_start_smc(rdev); 3302 si_start_smc_clock(rdev); 3303 } 3304 3305 static void si_dpm_stop_smc(struct radeon_device *rdev) 3306 { 3307 si_reset_smc(rdev); 3308 si_stop_smc_clock(rdev); 3309 } 3310 3311 static int si_process_firmware_header(struct radeon_device *rdev) 3312 { 3313 struct si_power_info *si_pi = si_get_pi(rdev); 3314 u32 tmp; 3315 int ret; 3316 3317 ret = si_read_smc_sram_dword(rdev, 3318 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3319 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3320 &tmp, si_pi->sram_end); 3321 if (ret) 3322 return ret; 3323 3324 si_pi->state_table_start = tmp; 3325 3326 ret = si_read_smc_sram_dword(rdev, 3327 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3328 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3329 &tmp, si_pi->sram_end); 3330 if (ret) 3331 return ret; 3332 3333 si_pi->soft_regs_start = tmp; 3334 3335 ret = si_read_smc_sram_dword(rdev, 3336 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3337 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3338 &tmp, si_pi->sram_end); 3339 if (ret) 3340 return ret; 3341 3342 si_pi->mc_reg_table_start = tmp; 3343 3344 ret = si_read_smc_sram_dword(rdev, 3345 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3346 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3347 &tmp, si_pi->sram_end); 3348 if (ret) 3349 return ret; 3350 3351 si_pi->arb_table_start = tmp; 3352 3353 ret = si_read_smc_sram_dword(rdev, 3354 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3355 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3356 &tmp, si_pi->sram_end); 3357 if (ret) 3358 return ret; 3359 3360 si_pi->cac_table_start = tmp; 3361 3362 ret = si_read_smc_sram_dword(rdev, 3363 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3364 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3365 &tmp, si_pi->sram_end); 3366 if (ret) 3367 return ret; 3368 3369 si_pi->dte_table_start = tmp; 3370 3371 ret = si_read_smc_sram_dword(rdev, 3372 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3373 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3374 &tmp, si_pi->sram_end); 3375 if (ret) 3376 return ret; 3377 3378 si_pi->spll_table_start = tmp; 3379 3380 ret = si_read_smc_sram_dword(rdev, 3381 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3382 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3383 &tmp, si_pi->sram_end); 3384 if (ret) 3385 return ret; 3386 3387 si_pi->papm_cfg_table_start = tmp; 3388 3389 return ret; 3390 } 3391 3392 static void si_read_clock_registers(struct radeon_device *rdev) 3393 { 3394 struct si_power_info *si_pi = si_get_pi(rdev); 3395 3396 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3397 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3398 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3399 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3400 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3401 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3402 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3403 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3404 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3405 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3406 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3407 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3408 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3409 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3410 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3411 } 3412 3413 static void si_enable_thermal_protection(struct radeon_device *rdev, 3414 bool enable) 3415 { 3416 if (enable) 3417 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3418 else 3419 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3420 } 3421 3422 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3423 { 3424 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3425 } 3426 3427 #if 0 3428 static int si_enter_ulp_state(struct radeon_device *rdev) 3429 { 3430 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3431 3432 udelay(25000); 3433 3434 return 0; 3435 } 3436 3437 static int si_exit_ulp_state(struct radeon_device *rdev) 3438 { 3439 int i; 3440 3441 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3442 3443 udelay(7000); 3444 3445 for (i = 0; i < rdev->usec_timeout; i++) { 3446 if (RREG32(SMC_RESP_0) == 1) 3447 break; 3448 udelay(1000); 3449 } 3450 3451 return 0; 3452 } 3453 #endif 3454 3455 static int si_notify_smc_display_change(struct radeon_device *rdev, 3456 bool has_display) 3457 { 3458 PPSMC_Msg msg = has_display ? 3459 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3460 3461 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3462 0 : -EINVAL; 3463 } 3464 3465 static void si_program_response_times(struct radeon_device *rdev) 3466 { 3467 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3468 u32 vddc_dly, acpi_dly, vbi_dly; 3469 u32 reference_clock; 3470 3471 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3472 3473 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3474 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3475 3476 if (voltage_response_time == 0) 3477 voltage_response_time = 1000; 3478 3479 acpi_delay_time = 15000; 3480 vbi_time_out = 100000; 3481 3482 reference_clock = radeon_get_xclk(rdev); 3483 3484 vddc_dly = (voltage_response_time * reference_clock) / 100; 3485 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3486 vbi_dly = (vbi_time_out * reference_clock) / 100; 3487 3488 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3489 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3490 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3491 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3492 } 3493 3494 static void si_program_ds_registers(struct radeon_device *rdev) 3495 { 3496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3497 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3498 3499 if (eg_pi->sclk_deep_sleep) { 3500 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3501 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3502 ~AUTOSCALE_ON_SS_CLEAR); 3503 } 3504 } 3505 3506 static void si_program_display_gap(struct radeon_device *rdev) 3507 { 3508 u32 tmp, pipe; 3509 int i; 3510 3511 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3512 if (rdev->pm.dpm.new_active_crtc_count > 0) 3513 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3514 else 3515 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3516 3517 if (rdev->pm.dpm.new_active_crtc_count > 1) 3518 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3519 else 3520 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3521 3522 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3523 3524 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3525 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3526 3527 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3528 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3529 /* find the first active crtc */ 3530 for (i = 0; i < rdev->num_crtc; i++) { 3531 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3532 break; 3533 } 3534 if (i == rdev->num_crtc) 3535 pipe = 0; 3536 else 3537 pipe = i; 3538 3539 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3540 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3541 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3542 } 3543 3544 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3545 } 3546 3547 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3548 { 3549 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3550 3551 if (enable) { 3552 if (pi->sclk_ss) 3553 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3554 } else { 3555 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3556 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3557 } 3558 } 3559 3560 static void si_setup_bsp(struct radeon_device *rdev) 3561 { 3562 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3563 u32 xclk = radeon_get_xclk(rdev); 3564 3565 r600_calculate_u_and_p(pi->asi, 3566 xclk, 3567 16, 3568 &pi->bsp, 3569 &pi->bsu); 3570 3571 r600_calculate_u_and_p(pi->pasi, 3572 xclk, 3573 16, 3574 &pi->pbsp, 3575 &pi->pbsu); 3576 3577 3578 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3579 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3580 3581 WREG32(CG_BSP, pi->dsp); 3582 } 3583 3584 static void si_program_git(struct radeon_device *rdev) 3585 { 3586 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3587 } 3588 3589 static void si_program_tp(struct radeon_device *rdev) 3590 { 3591 int i; 3592 enum r600_td td = R600_TD_DFLT; 3593 3594 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3595 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3596 3597 if (td == R600_TD_AUTO) 3598 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3599 else 3600 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3601 3602 if (td == R600_TD_UP) 3603 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3604 3605 if (td == R600_TD_DOWN) 3606 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3607 } 3608 3609 static void si_program_tpp(struct radeon_device *rdev) 3610 { 3611 WREG32(CG_TPC, R600_TPC_DFLT); 3612 } 3613 3614 static void si_program_sstp(struct radeon_device *rdev) 3615 { 3616 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3617 } 3618 3619 static void si_enable_display_gap(struct radeon_device *rdev) 3620 { 3621 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3622 3623 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3624 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) | 3625 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3626 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3627 } 3628 3629 static void si_program_vc(struct radeon_device *rdev) 3630 { 3631 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3632 3633 WREG32(CG_FTV, pi->vrc); 3634 } 3635 3636 static void si_clear_vc(struct radeon_device *rdev) 3637 { 3638 WREG32(CG_FTV, 0); 3639 } 3640 3641 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3642 { 3643 u8 mc_para_index; 3644 3645 if (memory_clock < 10000) 3646 mc_para_index = 0; 3647 else if (memory_clock >= 80000) 3648 mc_para_index = 0x0f; 3649 else 3650 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3651 return mc_para_index; 3652 } 3653 3654 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3655 { 3656 u8 mc_para_index; 3657 3658 if (strobe_mode) { 3659 if (memory_clock < 12500) 3660 mc_para_index = 0x00; 3661 else if (memory_clock > 47500) 3662 mc_para_index = 0x0f; 3663 else 3664 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3665 } else { 3666 if (memory_clock < 65000) 3667 mc_para_index = 0x00; 3668 else if (memory_clock > 135000) 3669 mc_para_index = 0x0f; 3670 else 3671 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3672 } 3673 return mc_para_index; 3674 } 3675 3676 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3677 { 3678 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3679 bool strobe_mode = false; 3680 u8 result = 0; 3681 3682 if (mclk <= pi->mclk_strobe_mode_threshold) 3683 strobe_mode = true; 3684 3685 if (pi->mem_gddr5) 3686 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3687 else 3688 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3689 3690 if (strobe_mode) 3691 result |= SISLANDS_SMC_STROBE_ENABLE; 3692 3693 return result; 3694 } 3695 3696 static int si_upload_firmware(struct radeon_device *rdev) 3697 { 3698 struct si_power_info *si_pi = si_get_pi(rdev); 3699 int ret; 3700 3701 si_reset_smc(rdev); 3702 si_stop_smc_clock(rdev); 3703 3704 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3705 3706 return ret; 3707 } 3708 3709 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3710 const struct atom_voltage_table *table, 3711 const struct radeon_phase_shedding_limits_table *limits) 3712 { 3713 u32 data, num_bits, num_levels; 3714 3715 if ((table == NULL) || (limits == NULL)) 3716 return false; 3717 3718 data = table->mask_low; 3719 3720 num_bits = hweight32(data); 3721 3722 if (num_bits == 0) 3723 return false; 3724 3725 num_levels = (1 << num_bits); 3726 3727 if (table->count != num_levels) 3728 return false; 3729 3730 if (limits->count != (num_levels - 1)) 3731 return false; 3732 3733 return true; 3734 } 3735 3736 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3737 struct atom_voltage_table *voltage_table) 3738 { 3739 unsigned int i, diff; 3740 3741 if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS) 3742 return; 3743 3744 diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS; 3745 3746 for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++) 3747 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3748 3749 voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS; 3750 } 3751 3752 static int si_construct_voltage_tables(struct radeon_device *rdev) 3753 { 3754 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3755 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3756 struct si_power_info *si_pi = si_get_pi(rdev); 3757 int ret; 3758 3759 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3760 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3761 if (ret) 3762 return ret; 3763 3764 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3765 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table); 3766 3767 if (eg_pi->vddci_control) { 3768 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3769 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3770 if (ret) 3771 return ret; 3772 3773 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3774 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table); 3775 } 3776 3777 if (pi->mvdd_control) { 3778 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3779 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3780 3781 if (ret) { 3782 pi->mvdd_control = false; 3783 return ret; 3784 } 3785 3786 if (si_pi->mvdd_voltage_table.count == 0) { 3787 pi->mvdd_control = false; 3788 return -EINVAL; 3789 } 3790 3791 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3792 si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table); 3793 } 3794 3795 if (si_pi->vddc_phase_shed_control) { 3796 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3797 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3798 if (ret) 3799 si_pi->vddc_phase_shed_control = false; 3800 3801 if ((si_pi->vddc_phase_shed_table.count == 0) || 3802 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3803 si_pi->vddc_phase_shed_control = false; 3804 } 3805 3806 return 0; 3807 } 3808 3809 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3810 const struct atom_voltage_table *voltage_table, 3811 SISLANDS_SMC_STATETABLE *table) 3812 { 3813 unsigned int i; 3814 3815 for (i = 0; i < voltage_table->count; i++) 3816 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3817 } 3818 3819 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3820 SISLANDS_SMC_STATETABLE *table) 3821 { 3822 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3823 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3824 struct si_power_info *si_pi = si_get_pi(rdev); 3825 u8 i; 3826 3827 if (eg_pi->vddc_voltage_table.count) { 3828 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 3829 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3830 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 3831 3832 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 3833 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 3834 table->maxVDDCIndexInPPTable = i; 3835 break; 3836 } 3837 } 3838 } 3839 3840 if (eg_pi->vddci_voltage_table.count) { 3841 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 3842 3843 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 3844 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 3845 } 3846 3847 3848 if (si_pi->mvdd_voltage_table.count) { 3849 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 3850 3851 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 3852 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 3853 } 3854 3855 if (si_pi->vddc_phase_shed_control) { 3856 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 3857 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 3858 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 3859 3860 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 3861 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 3862 3863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 3864 (u32)si_pi->vddc_phase_shed_table.phase_delay); 3865 } else { 3866 si_pi->vddc_phase_shed_control = false; 3867 } 3868 } 3869 3870 return 0; 3871 } 3872 3873 static int si_populate_voltage_value(struct radeon_device *rdev, 3874 const struct atom_voltage_table *table, 3875 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3876 { 3877 unsigned int i; 3878 3879 for (i = 0; i < table->count; i++) { 3880 if (value <= table->entries[i].value) { 3881 voltage->index = (u8)i; 3882 voltage->value = cpu_to_be16(table->entries[i].value); 3883 break; 3884 } 3885 } 3886 3887 if (i >= table->count) 3888 return -EINVAL; 3889 3890 return 0; 3891 } 3892 3893 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 3894 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3895 { 3896 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3897 struct si_power_info *si_pi = si_get_pi(rdev); 3898 3899 if (pi->mvdd_control) { 3900 if (mclk <= pi->mvdd_split_frequency) 3901 voltage->index = 0; 3902 else 3903 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 3904 3905 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 3906 } 3907 return 0; 3908 } 3909 3910 static int si_get_std_voltage_value(struct radeon_device *rdev, 3911 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 3912 u16 *std_voltage) 3913 { 3914 u16 v_index; 3915 bool voltage_found = false; 3916 *std_voltage = be16_to_cpu(voltage->value); 3917 3918 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 3919 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 3920 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 3921 return -EINVAL; 3922 3923 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3924 if (be16_to_cpu(voltage->value) == 3925 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3926 voltage_found = true; 3927 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3928 *std_voltage = 3929 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3930 else 3931 *std_voltage = 3932 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3933 break; 3934 } 3935 } 3936 3937 if (!voltage_found) { 3938 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 3939 if (be16_to_cpu(voltage->value) <= 3940 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 3941 voltage_found = true; 3942 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3943 *std_voltage = 3944 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 3945 else 3946 *std_voltage = 3947 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 3948 break; 3949 } 3950 } 3951 } 3952 } else { 3953 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 3954 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 3955 } 3956 } 3957 3958 return 0; 3959 } 3960 3961 static int si_populate_std_voltage_value(struct radeon_device *rdev, 3962 u16 value, u8 index, 3963 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 3964 { 3965 voltage->index = index; 3966 voltage->value = cpu_to_be16(value); 3967 3968 return 0; 3969 } 3970 3971 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 3972 const struct radeon_phase_shedding_limits_table *limits, 3973 u16 voltage, u32 sclk, u32 mclk, 3974 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 3975 { 3976 unsigned int i; 3977 3978 for (i = 0; i < limits->count; i++) { 3979 if ((voltage <= limits->entries[i].voltage) && 3980 (sclk <= limits->entries[i].sclk) && 3981 (mclk <= limits->entries[i].mclk)) 3982 break; 3983 } 3984 3985 smc_voltage->phase_settings = (u8)i; 3986 3987 return 0; 3988 } 3989 3990 static int si_init_arb_table_index(struct radeon_device *rdev) 3991 { 3992 struct si_power_info *si_pi = si_get_pi(rdev); 3993 u32 tmp; 3994 int ret; 3995 3996 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 3997 if (ret) 3998 return ret; 3999 4000 tmp &= 0x00FFFFFF; 4001 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4002 4003 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4004 } 4005 4006 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4007 { 4008 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4009 } 4010 4011 static int si_reset_to_default(struct radeon_device *rdev) 4012 { 4013 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4014 0 : -EINVAL; 4015 } 4016 4017 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4018 { 4019 struct si_power_info *si_pi = si_get_pi(rdev); 4020 u32 tmp; 4021 int ret; 4022 4023 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4024 &tmp, si_pi->sram_end); 4025 if (ret) 4026 return ret; 4027 4028 tmp = (tmp >> 24) & 0xff; 4029 4030 if (tmp == MC_CG_ARB_FREQ_F0) 4031 return 0; 4032 4033 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4034 } 4035 4036 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4037 u32 engine_clock) 4038 { 4039 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4040 u32 dram_rows; 4041 u32 dram_refresh_rate; 4042 u32 mc_arb_rfsh_rate; 4043 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4044 4045 if (pi->mem_gddr5) 4046 dram_rows = 1 << (tmp + 10); 4047 else 4048 dram_rows = DDR3_DRAM_ROWS; 4049 4050 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4051 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4052 4053 return mc_arb_rfsh_rate; 4054 } 4055 4056 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4057 struct rv7xx_pl *pl, 4058 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4059 { 4060 u32 dram_timing; 4061 u32 dram_timing2; 4062 u32 burst_time; 4063 4064 arb_regs->mc_arb_rfsh_rate = 4065 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4066 4067 radeon_atom_set_engine_dram_timings(rdev, 4068 pl->sclk, 4069 pl->mclk); 4070 4071 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4072 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4073 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4074 4075 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4076 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4077 arb_regs->mc_arb_burst_time = (u8)burst_time; 4078 4079 return 0; 4080 } 4081 4082 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4083 struct radeon_ps *radeon_state, 4084 unsigned int first_arb_set) 4085 { 4086 struct si_power_info *si_pi = si_get_pi(rdev); 4087 struct ni_ps *state = ni_get_ps(radeon_state); 4088 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4089 int i, ret = 0; 4090 4091 for (i = 0; i < state->performance_level_count; i++) { 4092 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4093 if (ret) 4094 break; 4095 ret = si_copy_bytes_to_smc(rdev, 4096 si_pi->arb_table_start + 4097 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4098 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4099 (u8 *)&arb_regs, 4100 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4101 si_pi->sram_end); 4102 if (ret) 4103 break; 4104 } 4105 4106 return ret; 4107 } 4108 4109 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4110 struct radeon_ps *radeon_new_state) 4111 { 4112 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4113 SISLANDS_DRIVER_STATE_ARB_INDEX); 4114 } 4115 4116 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4117 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4118 { 4119 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4120 struct si_power_info *si_pi = si_get_pi(rdev); 4121 4122 if (pi->mvdd_control) 4123 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4124 si_pi->mvdd_bootup_value, voltage); 4125 4126 return 0; 4127 } 4128 4129 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4130 struct radeon_ps *radeon_initial_state, 4131 SISLANDS_SMC_STATETABLE *table) 4132 { 4133 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4134 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4135 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4136 struct si_power_info *si_pi = si_get_pi(rdev); 4137 u32 reg; 4138 int ret; 4139 4140 table->initialState.levels[0].mclk.vDLL_CNTL = 4141 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4142 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4143 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4144 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4145 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4146 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4147 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4148 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4149 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4150 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4151 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4152 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4153 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4154 table->initialState.levels[0].mclk.vMPLL_SS = 4155 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4156 table->initialState.levels[0].mclk.vMPLL_SS2 = 4157 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4158 4159 table->initialState.levels[0].mclk.mclk_value = 4160 cpu_to_be32(initial_state->performance_levels[0].mclk); 4161 4162 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4163 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4164 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4165 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4166 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4167 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4168 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4169 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4170 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4171 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4172 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4173 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4174 4175 table->initialState.levels[0].sclk.sclk_value = 4176 cpu_to_be32(initial_state->performance_levels[0].sclk); 4177 4178 table->initialState.levels[0].arbRefreshState = 4179 SISLANDS_INITIAL_STATE_ARB_INDEX; 4180 4181 table->initialState.levels[0].ACIndex = 0; 4182 4183 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4184 initial_state->performance_levels[0].vddc, 4185 &table->initialState.levels[0].vddc); 4186 4187 if (!ret) { 4188 u16 std_vddc; 4189 4190 ret = si_get_std_voltage_value(rdev, 4191 &table->initialState.levels[0].vddc, 4192 &std_vddc); 4193 if (!ret) 4194 si_populate_std_voltage_value(rdev, std_vddc, 4195 table->initialState.levels[0].vddc.index, 4196 &table->initialState.levels[0].std_vddc); 4197 } 4198 4199 if (eg_pi->vddci_control) 4200 si_populate_voltage_value(rdev, 4201 &eg_pi->vddci_voltage_table, 4202 initial_state->performance_levels[0].vddci, 4203 &table->initialState.levels[0].vddci); 4204 4205 if (si_pi->vddc_phase_shed_control) 4206 si_populate_phase_shedding_value(rdev, 4207 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4208 initial_state->performance_levels[0].vddc, 4209 initial_state->performance_levels[0].sclk, 4210 initial_state->performance_levels[0].mclk, 4211 &table->initialState.levels[0].vddc); 4212 4213 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4214 4215 reg = CG_R(0xffff) | CG_L(0); 4216 table->initialState.levels[0].aT = cpu_to_be32(reg); 4217 4218 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4219 4220 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4221 4222 if (pi->mem_gddr5) { 4223 table->initialState.levels[0].strobeMode = 4224 si_get_strobe_mode_settings(rdev, 4225 initial_state->performance_levels[0].mclk); 4226 4227 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4228 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4229 else 4230 table->initialState.levels[0].mcFlags = 0; 4231 } 4232 4233 table->initialState.levelCount = 1; 4234 4235 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4236 4237 table->initialState.levels[0].dpm2.MaxPS = 0; 4238 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4239 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4240 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4241 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4242 4243 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4244 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4245 4246 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4247 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4248 4249 return 0; 4250 } 4251 4252 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4253 SISLANDS_SMC_STATETABLE *table) 4254 { 4255 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4256 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4257 struct si_power_info *si_pi = si_get_pi(rdev); 4258 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4259 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4260 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4261 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4262 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4263 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4264 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4265 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4266 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4267 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4268 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4269 u32 reg; 4270 int ret; 4271 4272 table->ACPIState = table->initialState; 4273 4274 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4275 4276 if (pi->acpi_vddc) { 4277 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4278 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4279 if (!ret) { 4280 u16 std_vddc; 4281 4282 ret = si_get_std_voltage_value(rdev, 4283 &table->ACPIState.levels[0].vddc, &std_vddc); 4284 if (!ret) 4285 si_populate_std_voltage_value(rdev, std_vddc, 4286 table->ACPIState.levels[0].vddc.index, 4287 &table->ACPIState.levels[0].std_vddc); 4288 } 4289 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4290 4291 if (si_pi->vddc_phase_shed_control) { 4292 si_populate_phase_shedding_value(rdev, 4293 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4294 pi->acpi_vddc, 4295 0, 4296 0, 4297 &table->ACPIState.levels[0].vddc); 4298 } 4299 } else { 4300 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4301 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4302 if (!ret) { 4303 u16 std_vddc; 4304 4305 ret = si_get_std_voltage_value(rdev, 4306 &table->ACPIState.levels[0].vddc, &std_vddc); 4307 4308 if (!ret) 4309 si_populate_std_voltage_value(rdev, std_vddc, 4310 table->ACPIState.levels[0].vddc.index, 4311 &table->ACPIState.levels[0].std_vddc); 4312 } 4313 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4314 si_pi->sys_pcie_mask, 4315 si_pi->boot_pcie_gen, 4316 RADEON_PCIE_GEN1); 4317 4318 if (si_pi->vddc_phase_shed_control) 4319 si_populate_phase_shedding_value(rdev, 4320 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4321 pi->min_vddc_in_table, 4322 0, 4323 0, 4324 &table->ACPIState.levels[0].vddc); 4325 } 4326 4327 if (pi->acpi_vddc) { 4328 if (eg_pi->acpi_vddci) 4329 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4330 eg_pi->acpi_vddci, 4331 &table->ACPIState.levels[0].vddci); 4332 } 4333 4334 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4335 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4336 4337 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4338 4339 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4340 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4341 4342 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4343 cpu_to_be32(dll_cntl); 4344 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4345 cpu_to_be32(mclk_pwrmgt_cntl); 4346 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4347 cpu_to_be32(mpll_ad_func_cntl); 4348 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4349 cpu_to_be32(mpll_dq_func_cntl); 4350 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4351 cpu_to_be32(mpll_func_cntl); 4352 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4353 cpu_to_be32(mpll_func_cntl_1); 4354 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4355 cpu_to_be32(mpll_func_cntl_2); 4356 table->ACPIState.levels[0].mclk.vMPLL_SS = 4357 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4358 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4359 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4360 4361 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4362 cpu_to_be32(spll_func_cntl); 4363 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4364 cpu_to_be32(spll_func_cntl_2); 4365 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4366 cpu_to_be32(spll_func_cntl_3); 4367 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4368 cpu_to_be32(spll_func_cntl_4); 4369 4370 table->ACPIState.levels[0].mclk.mclk_value = 0; 4371 table->ACPIState.levels[0].sclk.sclk_value = 0; 4372 4373 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4374 4375 if (eg_pi->dynamic_ac_timing) 4376 table->ACPIState.levels[0].ACIndex = 0; 4377 4378 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4379 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4380 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4381 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4382 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4383 4384 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4385 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4386 4387 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4388 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4389 4390 return 0; 4391 } 4392 4393 static int si_populate_ulv_state(struct radeon_device *rdev, 4394 SISLANDS_SMC_SWSTATE *state) 4395 { 4396 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4397 struct si_power_info *si_pi = si_get_pi(rdev); 4398 struct si_ulv_param *ulv = &si_pi->ulv; 4399 u32 sclk_in_sr = 1350; /* ??? */ 4400 int ret; 4401 4402 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4403 &state->levels[0]); 4404 if (!ret) { 4405 if (eg_pi->sclk_deep_sleep) { 4406 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4407 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4408 else 4409 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4410 } 4411 if (ulv->one_pcie_lane_in_ulv) 4412 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4413 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4414 state->levels[0].ACIndex = 1; 4415 state->levels[0].std_vddc = state->levels[0].vddc; 4416 state->levelCount = 1; 4417 4418 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4419 } 4420 4421 return ret; 4422 } 4423 4424 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4425 { 4426 struct si_power_info *si_pi = si_get_pi(rdev); 4427 struct si_ulv_param *ulv = &si_pi->ulv; 4428 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4429 int ret; 4430 4431 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4432 &arb_regs); 4433 if (ret) 4434 return ret; 4435 4436 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4437 ulv->volt_change_delay); 4438 4439 ret = si_copy_bytes_to_smc(rdev, 4440 si_pi->arb_table_start + 4441 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4442 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4443 (u8 *)&arb_regs, 4444 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4445 si_pi->sram_end); 4446 4447 return ret; 4448 } 4449 4450 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4451 { 4452 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4453 4454 pi->mvdd_split_frequency = 30000; 4455 } 4456 4457 static int si_init_smc_table(struct radeon_device *rdev) 4458 { 4459 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4460 struct si_power_info *si_pi = si_get_pi(rdev); 4461 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4462 const struct si_ulv_param *ulv = &si_pi->ulv; 4463 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4464 int ret; 4465 u32 lane_width; 4466 u32 vr_hot_gpio; 4467 4468 si_populate_smc_voltage_tables(rdev, table); 4469 4470 switch (rdev->pm.int_thermal_type) { 4471 case THERMAL_TYPE_SI: 4472 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4473 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4474 break; 4475 case THERMAL_TYPE_NONE: 4476 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4477 break; 4478 default: 4479 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4480 break; 4481 } 4482 4483 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4484 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4485 4486 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4487 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4488 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4489 } 4490 4491 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4492 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4493 4494 if (pi->mem_gddr5) 4495 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4496 4497 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4498 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4499 4500 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4501 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4502 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4503 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4504 vr_hot_gpio); 4505 } 4506 4507 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4508 if (ret) 4509 return ret; 4510 4511 ret = si_populate_smc_acpi_state(rdev, table); 4512 if (ret) 4513 return ret; 4514 4515 table->driverState = table->initialState; 4516 4517 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4518 SISLANDS_INITIAL_STATE_ARB_INDEX); 4519 if (ret) 4520 return ret; 4521 4522 if (ulv->supported && ulv->pl.vddc) { 4523 ret = si_populate_ulv_state(rdev, &table->ULVState); 4524 if (ret) 4525 return ret; 4526 4527 ret = si_program_ulv_memory_timing_parameters(rdev); 4528 if (ret) 4529 return ret; 4530 4531 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4532 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4533 4534 lane_width = radeon_get_pcie_lanes(rdev); 4535 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4536 } else { 4537 table->ULVState = table->initialState; 4538 } 4539 4540 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4541 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4542 si_pi->sram_end); 4543 } 4544 4545 static int si_calculate_sclk_params(struct radeon_device *rdev, 4546 u32 engine_clock, 4547 SISLANDS_SMC_SCLK_VALUE *sclk) 4548 { 4549 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4550 struct si_power_info *si_pi = si_get_pi(rdev); 4551 struct atom_clock_dividers dividers; 4552 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4553 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4554 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4555 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4556 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4557 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4558 u64 tmp; 4559 u32 reference_clock = rdev->clock.spll.reference_freq; 4560 u32 reference_divider; 4561 u32 fbdiv; 4562 int ret; 4563 4564 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4565 engine_clock, false, ÷rs); 4566 if (ret) 4567 return ret; 4568 4569 reference_divider = 1 + dividers.ref_div; 4570 4571 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4572 do_div(tmp, reference_clock); 4573 fbdiv = (u32) tmp; 4574 4575 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4576 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4577 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4578 4579 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4580 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4581 4582 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4583 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4584 spll_func_cntl_3 |= SPLL_DITHEN; 4585 4586 if (pi->sclk_ss) { 4587 struct radeon_atom_ss ss; 4588 u32 vco_freq = engine_clock * dividers.post_div; 4589 4590 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4591 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4592 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4593 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4594 4595 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4596 cg_spll_spread_spectrum |= CLK_S(clk_s); 4597 cg_spll_spread_spectrum |= SSEN; 4598 4599 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4600 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4601 } 4602 } 4603 4604 sclk->sclk_value = engine_clock; 4605 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4606 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4607 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4608 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4609 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4610 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4611 4612 return 0; 4613 } 4614 4615 static int si_populate_sclk_value(struct radeon_device *rdev, 4616 u32 engine_clock, 4617 SISLANDS_SMC_SCLK_VALUE *sclk) 4618 { 4619 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4620 int ret; 4621 4622 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4623 if (!ret) { 4624 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4625 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4626 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4627 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4628 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4629 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4630 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4631 } 4632 4633 return ret; 4634 } 4635 4636 static int si_populate_mclk_value(struct radeon_device *rdev, 4637 u32 engine_clock, 4638 u32 memory_clock, 4639 SISLANDS_SMC_MCLK_VALUE *mclk, 4640 bool strobe_mode, 4641 bool dll_state_on) 4642 { 4643 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4644 struct si_power_info *si_pi = si_get_pi(rdev); 4645 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4646 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4647 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4648 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4649 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4650 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4651 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4652 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4653 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4654 struct atom_mpll_param mpll_param; 4655 int ret; 4656 4657 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4658 if (ret) 4659 return ret; 4660 4661 mpll_func_cntl &= ~BWCTRL_MASK; 4662 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4663 4664 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4665 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4666 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4667 4668 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4669 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4670 4671 if (pi->mem_gddr5) { 4672 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4673 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4674 YCLK_POST_DIV(mpll_param.post_div); 4675 } 4676 4677 if (pi->mclk_ss) { 4678 struct radeon_atom_ss ss; 4679 u32 freq_nom; 4680 u32 tmp; 4681 u32 reference_clock = rdev->clock.mpll.reference_freq; 4682 4683 if (pi->mem_gddr5) 4684 freq_nom = memory_clock * 4; 4685 else 4686 freq_nom = memory_clock * 2; 4687 4688 tmp = freq_nom / reference_clock; 4689 tmp = tmp * tmp; 4690 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4691 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4692 u32 clks = reference_clock * 5 / ss.rate; 4693 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4694 4695 mpll_ss1 &= ~CLKV_MASK; 4696 mpll_ss1 |= CLKV(clkv); 4697 4698 mpll_ss2 &= ~CLKS_MASK; 4699 mpll_ss2 |= CLKS(clks); 4700 } 4701 } 4702 4703 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4704 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4705 4706 if (dll_state_on) 4707 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4708 else 4709 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4710 4711 mclk->mclk_value = cpu_to_be32(memory_clock); 4712 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4713 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4714 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4715 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4716 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4717 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4718 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4719 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4720 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4721 4722 return 0; 4723 } 4724 4725 static void si_populate_smc_sp(struct radeon_device *rdev, 4726 struct radeon_ps *radeon_state, 4727 SISLANDS_SMC_SWSTATE *smc_state) 4728 { 4729 struct ni_ps *ps = ni_get_ps(radeon_state); 4730 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4731 int i; 4732 4733 for (i = 0; i < ps->performance_level_count - 1; i++) 4734 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4735 4736 smc_state->levels[ps->performance_level_count - 1].bSP = 4737 cpu_to_be32(pi->psp); 4738 } 4739 4740 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4741 struct rv7xx_pl *pl, 4742 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4743 { 4744 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4745 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4746 struct si_power_info *si_pi = si_get_pi(rdev); 4747 int ret; 4748 bool dll_state_on; 4749 u16 std_vddc; 4750 bool gmc_pg = false; 4751 4752 if (eg_pi->pcie_performance_request && 4753 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4754 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4755 else 4756 level->gen2PCIE = (u8)pl->pcie_gen; 4757 4758 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4759 if (ret) 4760 return ret; 4761 4762 level->mcFlags = 0; 4763 4764 if (pi->mclk_stutter_mode_threshold && 4765 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4766 !eg_pi->uvd_enabled && 4767 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4768 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4769 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4770 4771 if (gmc_pg) 4772 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4773 } 4774 4775 if (pi->mem_gddr5) { 4776 if (pl->mclk > pi->mclk_edc_enable_threshold) 4777 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4778 4779 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4780 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4781 4782 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4783 4784 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4785 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4786 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4787 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4788 else 4789 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4790 } else { 4791 dll_state_on = false; 4792 } 4793 } else { 4794 level->strobeMode = si_get_strobe_mode_settings(rdev, 4795 pl->mclk); 4796 4797 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4798 } 4799 4800 ret = si_populate_mclk_value(rdev, 4801 pl->sclk, 4802 pl->mclk, 4803 &level->mclk, 4804 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4805 if (ret) 4806 return ret; 4807 4808 ret = si_populate_voltage_value(rdev, 4809 &eg_pi->vddc_voltage_table, 4810 pl->vddc, &level->vddc); 4811 if (ret) 4812 return ret; 4813 4814 4815 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4816 if (ret) 4817 return ret; 4818 4819 ret = si_populate_std_voltage_value(rdev, std_vddc, 4820 level->vddc.index, &level->std_vddc); 4821 if (ret) 4822 return ret; 4823 4824 if (eg_pi->vddci_control) { 4825 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4826 pl->vddci, &level->vddci); 4827 if (ret) 4828 return ret; 4829 } 4830 4831 if (si_pi->vddc_phase_shed_control) { 4832 ret = si_populate_phase_shedding_value(rdev, 4833 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4834 pl->vddc, 4835 pl->sclk, 4836 pl->mclk, 4837 &level->vddc); 4838 if (ret) 4839 return ret; 4840 } 4841 4842 level->MaxPoweredUpCU = si_pi->max_cu; 4843 4844 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 4845 4846 return ret; 4847 } 4848 4849 static int si_populate_smc_t(struct radeon_device *rdev, 4850 struct radeon_ps *radeon_state, 4851 SISLANDS_SMC_SWSTATE *smc_state) 4852 { 4853 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4854 struct ni_ps *state = ni_get_ps(radeon_state); 4855 u32 a_t; 4856 u32 t_l, t_h; 4857 u32 high_bsp; 4858 int i, ret; 4859 4860 if (state->performance_level_count >= 9) 4861 return -EINVAL; 4862 4863 if (state->performance_level_count < 2) { 4864 a_t = CG_R(0xffff) | CG_L(0); 4865 smc_state->levels[0].aT = cpu_to_be32(a_t); 4866 return 0; 4867 } 4868 4869 smc_state->levels[0].aT = cpu_to_be32(0); 4870 4871 for (i = 0; i <= state->performance_level_count - 2; i++) { 4872 ret = r600_calculate_at( 4873 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 4874 100 * R600_AH_DFLT, 4875 state->performance_levels[i + 1].sclk, 4876 state->performance_levels[i].sclk, 4877 &t_l, 4878 &t_h); 4879 4880 if (ret) { 4881 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 4882 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 4883 } 4884 4885 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 4886 a_t |= CG_R(t_l * pi->bsp / 20000); 4887 smc_state->levels[i].aT = cpu_to_be32(a_t); 4888 4889 high_bsp = (i == state->performance_level_count - 2) ? 4890 pi->pbsp : pi->bsp; 4891 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 4892 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 4893 } 4894 4895 return 0; 4896 } 4897 4898 static int si_disable_ulv(struct radeon_device *rdev) 4899 { 4900 struct si_power_info *si_pi = si_get_pi(rdev); 4901 struct si_ulv_param *ulv = &si_pi->ulv; 4902 4903 if (ulv->supported) 4904 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 4905 0 : -EINVAL; 4906 4907 return 0; 4908 } 4909 4910 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 4911 struct radeon_ps *radeon_state) 4912 { 4913 const struct si_power_info *si_pi = si_get_pi(rdev); 4914 const struct si_ulv_param *ulv = &si_pi->ulv; 4915 const struct ni_ps *state = ni_get_ps(radeon_state); 4916 int i; 4917 4918 if (state->performance_levels[0].mclk != ulv->pl.mclk) 4919 return false; 4920 4921 /* XXX validate against display requirements! */ 4922 4923 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 4924 if (rdev->clock.current_dispclk <= 4925 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 4926 if (ulv->pl.vddc < 4927 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 4928 return false; 4929 } 4930 } 4931 4932 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 4933 return false; 4934 4935 return true; 4936 } 4937 4938 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 4939 struct radeon_ps *radeon_new_state) 4940 { 4941 const struct si_power_info *si_pi = si_get_pi(rdev); 4942 const struct si_ulv_param *ulv = &si_pi->ulv; 4943 4944 if (ulv->supported) { 4945 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 4946 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 4947 0 : -EINVAL; 4948 } 4949 return 0; 4950 } 4951 4952 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 4953 struct radeon_ps *radeon_state, 4954 SISLANDS_SMC_SWSTATE *smc_state) 4955 { 4956 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4957 struct ni_power_info *ni_pi = ni_get_pi(rdev); 4958 struct si_power_info *si_pi = si_get_pi(rdev); 4959 struct ni_ps *state = ni_get_ps(radeon_state); 4960 int i, ret; 4961 u32 threshold; 4962 u32 sclk_in_sr = 1350; /* ??? */ 4963 4964 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 4965 return -EINVAL; 4966 4967 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 4968 4969 if (radeon_state->vclk && radeon_state->dclk) { 4970 eg_pi->uvd_enabled = true; 4971 if (eg_pi->smu_uvd_hs) 4972 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 4973 } else { 4974 eg_pi->uvd_enabled = false; 4975 } 4976 4977 if (state->dc_compatible) 4978 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 4979 4980 smc_state->levelCount = 0; 4981 for (i = 0; i < state->performance_level_count; i++) { 4982 if (eg_pi->sclk_deep_sleep) { 4983 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 4984 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4985 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4986 else 4987 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4988 } 4989 } 4990 4991 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 4992 &smc_state->levels[i]); 4993 smc_state->levels[i].arbRefreshState = 4994 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 4995 4996 if (ret) 4997 return ret; 4998 4999 if (ni_pi->enable_power_containment) 5000 smc_state->levels[i].displayWatermark = 5001 (state->performance_levels[i].sclk < threshold) ? 5002 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5003 else 5004 smc_state->levels[i].displayWatermark = (i < 2) ? 5005 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5006 5007 if (eg_pi->dynamic_ac_timing) 5008 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5009 else 5010 smc_state->levels[i].ACIndex = 0; 5011 5012 smc_state->levelCount++; 5013 } 5014 5015 si_write_smc_soft_register(rdev, 5016 SI_SMC_SOFT_REGISTER_watermark_threshold, 5017 threshold / 512); 5018 5019 si_populate_smc_sp(rdev, radeon_state, smc_state); 5020 5021 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5022 if (ret) 5023 ni_pi->enable_power_containment = false; 5024 5025 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5026 if (ret) 5027 ni_pi->enable_sq_ramping = false; 5028 5029 return si_populate_smc_t(rdev, radeon_state, smc_state); 5030 } 5031 5032 static int si_upload_sw_state(struct radeon_device *rdev, 5033 struct radeon_ps *radeon_new_state) 5034 { 5035 struct si_power_info *si_pi = si_get_pi(rdev); 5036 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5037 int ret; 5038 u32 address = si_pi->state_table_start + 5039 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5040 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5041 ((new_state->performance_level_count - 1) * 5042 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5043 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5044 5045 memset(smc_state, 0, state_size); 5046 5047 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5048 if (ret) 5049 return ret; 5050 5051 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5052 state_size, si_pi->sram_end); 5053 5054 return ret; 5055 } 5056 5057 static int si_upload_ulv_state(struct radeon_device *rdev) 5058 { 5059 struct si_power_info *si_pi = si_get_pi(rdev); 5060 struct si_ulv_param *ulv = &si_pi->ulv; 5061 int ret = 0; 5062 5063 if (ulv->supported && ulv->pl.vddc) { 5064 u32 address = si_pi->state_table_start + 5065 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5066 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5067 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5068 5069 memset(smc_state, 0, state_size); 5070 5071 ret = si_populate_ulv_state(rdev, smc_state); 5072 if (!ret) 5073 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5074 state_size, si_pi->sram_end); 5075 } 5076 5077 return ret; 5078 } 5079 5080 static int si_upload_smc_data(struct radeon_device *rdev) 5081 { 5082 struct radeon_crtc *radeon_crtc = NULL; 5083 int i; 5084 5085 if (rdev->pm.dpm.new_active_crtc_count == 0) 5086 return 0; 5087 5088 for (i = 0; i < rdev->num_crtc; i++) { 5089 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5090 radeon_crtc = rdev->mode_info.crtcs[i]; 5091 break; 5092 } 5093 } 5094 5095 if (radeon_crtc == NULL) 5096 return 0; 5097 5098 if (radeon_crtc->line_time <= 0) 5099 return 0; 5100 5101 if (si_write_smc_soft_register(rdev, 5102 SI_SMC_SOFT_REGISTER_crtc_index, 5103 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5104 return 0; 5105 5106 if (si_write_smc_soft_register(rdev, 5107 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5108 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5109 return 0; 5110 5111 if (si_write_smc_soft_register(rdev, 5112 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5113 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5114 return 0; 5115 5116 return 0; 5117 } 5118 5119 static int si_set_mc_special_registers(struct radeon_device *rdev, 5120 struct si_mc_reg_table *table) 5121 { 5122 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5123 u8 i, j, k; 5124 u32 temp_reg; 5125 5126 for (i = 0, j = table->last; i < table->last; i++) { 5127 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5128 return -EINVAL; 5129 switch (table->mc_reg_address[i].s1 << 2) { 5130 case MC_SEQ_MISC1: 5131 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5132 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5133 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5134 for (k = 0; k < table->num_entries; k++) 5135 table->mc_reg_table_entry[k].mc_data[j] = 5136 ((temp_reg & 0xffff0000)) | 5137 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5138 j++; 5139 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5140 return -EINVAL; 5141 5142 temp_reg = RREG32(MC_PMG_CMD_MRS); 5143 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5144 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5145 for (k = 0; k < table->num_entries; k++) { 5146 table->mc_reg_table_entry[k].mc_data[j] = 5147 (temp_reg & 0xffff0000) | 5148 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5149 if (!pi->mem_gddr5) 5150 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5151 } 5152 j++; 5153 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5154 return -EINVAL; 5155 5156 if (!pi->mem_gddr5) { 5157 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5158 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5159 for (k = 0; k < table->num_entries; k++) 5160 table->mc_reg_table_entry[k].mc_data[j] = 5161 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5162 j++; 5163 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5164 return -EINVAL; 5165 } 5166 break; 5167 case MC_SEQ_RESERVE_M: 5168 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5169 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5170 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5171 for(k = 0; k < table->num_entries; k++) 5172 table->mc_reg_table_entry[k].mc_data[j] = 5173 (temp_reg & 0xffff0000) | 5174 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5175 j++; 5176 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5177 return -EINVAL; 5178 break; 5179 default: 5180 break; 5181 } 5182 } 5183 5184 table->last = j; 5185 5186 return 0; 5187 } 5188 5189 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5190 { 5191 bool result = true; 5192 5193 switch (in_reg) { 5194 case MC_SEQ_RAS_TIMING >> 2: 5195 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5196 break; 5197 case MC_SEQ_CAS_TIMING >> 2: 5198 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5199 break; 5200 case MC_SEQ_MISC_TIMING >> 2: 5201 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5202 break; 5203 case MC_SEQ_MISC_TIMING2 >> 2: 5204 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5205 break; 5206 case MC_SEQ_RD_CTL_D0 >> 2: 5207 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5208 break; 5209 case MC_SEQ_RD_CTL_D1 >> 2: 5210 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5211 break; 5212 case MC_SEQ_WR_CTL_D0 >> 2: 5213 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5214 break; 5215 case MC_SEQ_WR_CTL_D1 >> 2: 5216 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5217 break; 5218 case MC_PMG_CMD_EMRS >> 2: 5219 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5220 break; 5221 case MC_PMG_CMD_MRS >> 2: 5222 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5223 break; 5224 case MC_PMG_CMD_MRS1 >> 2: 5225 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5226 break; 5227 case MC_SEQ_PMG_TIMING >> 2: 5228 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5229 break; 5230 case MC_PMG_CMD_MRS2 >> 2: 5231 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5232 break; 5233 case MC_SEQ_WR_CTL_2 >> 2: 5234 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5235 break; 5236 default: 5237 result = false; 5238 break; 5239 } 5240 5241 return result; 5242 } 5243 5244 static void si_set_valid_flag(struct si_mc_reg_table *table) 5245 { 5246 u8 i, j; 5247 5248 for (i = 0; i < table->last; i++) { 5249 for (j = 1; j < table->num_entries; j++) { 5250 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5251 table->valid_flag |= 1 << i; 5252 break; 5253 } 5254 } 5255 } 5256 } 5257 5258 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5259 { 5260 u32 i; 5261 u16 address; 5262 5263 for (i = 0; i < table->last; i++) 5264 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5265 address : table->mc_reg_address[i].s1; 5266 5267 } 5268 5269 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5270 struct si_mc_reg_table *si_table) 5271 { 5272 u8 i, j; 5273 5274 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5275 return -EINVAL; 5276 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5277 return -EINVAL; 5278 5279 for (i = 0; i < table->last; i++) 5280 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5281 si_table->last = table->last; 5282 5283 for (i = 0; i < table->num_entries; i++) { 5284 si_table->mc_reg_table_entry[i].mclk_max = 5285 table->mc_reg_table_entry[i].mclk_max; 5286 for (j = 0; j < table->last; j++) { 5287 si_table->mc_reg_table_entry[i].mc_data[j] = 5288 table->mc_reg_table_entry[i].mc_data[j]; 5289 } 5290 } 5291 si_table->num_entries = table->num_entries; 5292 5293 return 0; 5294 } 5295 5296 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5297 { 5298 struct si_power_info *si_pi = si_get_pi(rdev); 5299 struct atom_mc_reg_table *table; 5300 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5301 u8 module_index = rv770_get_memory_module_index(rdev); 5302 int ret; 5303 5304 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5305 if (!table) 5306 return -ENOMEM; 5307 5308 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5309 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5310 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5311 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5312 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5313 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5314 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5315 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5316 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5317 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5318 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5319 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5320 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5321 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5322 5323 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5324 if (ret) 5325 goto init_mc_done; 5326 5327 ret = si_copy_vbios_mc_reg_table(table, si_table); 5328 if (ret) 5329 goto init_mc_done; 5330 5331 si_set_s0_mc_reg_index(si_table); 5332 5333 ret = si_set_mc_special_registers(rdev, si_table); 5334 if (ret) 5335 goto init_mc_done; 5336 5337 si_set_valid_flag(si_table); 5338 5339 init_mc_done: 5340 kfree(table); 5341 5342 return ret; 5343 5344 } 5345 5346 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5347 SMC_SIslands_MCRegisters *mc_reg_table) 5348 { 5349 struct si_power_info *si_pi = si_get_pi(rdev); 5350 u32 i, j; 5351 5352 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5353 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5354 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE) 5355 break; 5356 mc_reg_table->address[i].s0 = 5357 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5358 mc_reg_table->address[i].s1 = 5359 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5360 i++; 5361 } 5362 } 5363 mc_reg_table->last = (u8)i; 5364 } 5365 5366 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5367 SMC_SIslands_MCRegisterSet *data, 5368 u32 num_entries, u32 valid_flag) 5369 { 5370 u32 i, j; 5371 5372 for(i = 0, j = 0; j < num_entries; j++) { 5373 if (valid_flag & (1 << j)) { 5374 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5375 i++; 5376 } 5377 } 5378 } 5379 5380 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5381 struct rv7xx_pl *pl, 5382 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5383 { 5384 struct si_power_info *si_pi = si_get_pi(rdev); 5385 u32 i = 0; 5386 5387 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5388 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5389 break; 5390 } 5391 5392 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5393 --i; 5394 5395 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5396 mc_reg_table_data, si_pi->mc_reg_table.last, 5397 si_pi->mc_reg_table.valid_flag); 5398 } 5399 5400 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5401 struct radeon_ps *radeon_state, 5402 SMC_SIslands_MCRegisters *mc_reg_table) 5403 { 5404 struct ni_ps *state = ni_get_ps(radeon_state); 5405 int i; 5406 5407 for (i = 0; i < state->performance_level_count; i++) { 5408 si_convert_mc_reg_table_entry_to_smc(rdev, 5409 &state->performance_levels[i], 5410 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5411 } 5412 } 5413 5414 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5415 struct radeon_ps *radeon_boot_state) 5416 { 5417 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5418 struct si_power_info *si_pi = si_get_pi(rdev); 5419 struct si_ulv_param *ulv = &si_pi->ulv; 5420 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5421 5422 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5423 5424 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5425 5426 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5427 5428 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5429 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5430 5431 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5432 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5433 si_pi->mc_reg_table.last, 5434 si_pi->mc_reg_table.valid_flag); 5435 5436 if (ulv->supported && ulv->pl.vddc != 0) 5437 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5438 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5439 else 5440 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5441 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5442 si_pi->mc_reg_table.last, 5443 si_pi->mc_reg_table.valid_flag); 5444 5445 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5446 5447 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5448 (u8 *)smc_mc_reg_table, 5449 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5450 } 5451 5452 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5453 struct radeon_ps *radeon_new_state) 5454 { 5455 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5456 struct si_power_info *si_pi = si_get_pi(rdev); 5457 u32 address = si_pi->mc_reg_table_start + 5458 offsetof(SMC_SIslands_MCRegisters, 5459 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5460 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5461 5462 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5463 5464 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5465 5466 5467 return si_copy_bytes_to_smc(rdev, address, 5468 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5469 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5470 si_pi->sram_end); 5471 5472 } 5473 5474 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5475 { 5476 if (enable) 5477 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5478 else 5479 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5480 } 5481 5482 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5483 struct radeon_ps *radeon_state) 5484 { 5485 struct ni_ps *state = ni_get_ps(radeon_state); 5486 int i; 5487 u16 pcie_speed, max_speed = 0; 5488 5489 for (i = 0; i < state->performance_level_count; i++) { 5490 pcie_speed = state->performance_levels[i].pcie_gen; 5491 if (max_speed < pcie_speed) 5492 max_speed = pcie_speed; 5493 } 5494 return max_speed; 5495 } 5496 5497 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5498 { 5499 u32 speed_cntl; 5500 5501 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5502 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5503 5504 return (u16)speed_cntl; 5505 } 5506 5507 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5508 struct radeon_ps *radeon_new_state, 5509 struct radeon_ps *radeon_current_state) 5510 { 5511 struct si_power_info *si_pi = si_get_pi(rdev); 5512 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5513 enum radeon_pcie_gen current_link_speed; 5514 5515 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5516 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5517 else 5518 current_link_speed = si_pi->force_pcie_gen; 5519 5520 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5521 si_pi->pspp_notify_required = false; 5522 if (target_link_speed > current_link_speed) { 5523 switch (target_link_speed) { 5524 #if defined(CONFIG_ACPI) 5525 case RADEON_PCIE_GEN3: 5526 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5527 break; 5528 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5529 if (current_link_speed == RADEON_PCIE_GEN2) 5530 break; 5531 case RADEON_PCIE_GEN2: 5532 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5533 break; 5534 #endif 5535 default: 5536 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5537 break; 5538 } 5539 } else { 5540 if (target_link_speed < current_link_speed) 5541 si_pi->pspp_notify_required = true; 5542 } 5543 } 5544 5545 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5546 struct radeon_ps *radeon_new_state, 5547 struct radeon_ps *radeon_current_state) 5548 { 5549 struct si_power_info *si_pi = si_get_pi(rdev); 5550 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5551 u8 request; 5552 5553 if (si_pi->pspp_notify_required) { 5554 if (target_link_speed == RADEON_PCIE_GEN3) 5555 request = PCIE_PERF_REQ_PECI_GEN3; 5556 else if (target_link_speed == RADEON_PCIE_GEN2) 5557 request = PCIE_PERF_REQ_PECI_GEN2; 5558 else 5559 request = PCIE_PERF_REQ_PECI_GEN1; 5560 5561 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5562 (si_get_current_pcie_speed(rdev) > 0)) 5563 return; 5564 5565 #if defined(CONFIG_ACPI) 5566 radeon_acpi_pcie_performance_request(rdev, request, false); 5567 #endif 5568 } 5569 } 5570 5571 #if 0 5572 static int si_ds_request(struct radeon_device *rdev, 5573 bool ds_status_on, u32 count_write) 5574 { 5575 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5576 5577 if (eg_pi->sclk_deep_sleep) { 5578 if (ds_status_on) 5579 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5580 PPSMC_Result_OK) ? 5581 0 : -EINVAL; 5582 else 5583 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5584 PPSMC_Result_OK) ? 0 : -EINVAL; 5585 } 5586 return 0; 5587 } 5588 #endif 5589 5590 static void si_set_max_cu_value(struct radeon_device *rdev) 5591 { 5592 struct si_power_info *si_pi = si_get_pi(rdev); 5593 5594 if (rdev->family == CHIP_VERDE) { 5595 switch (rdev->pdev->device) { 5596 case 0x6820: 5597 case 0x6825: 5598 case 0x6821: 5599 case 0x6823: 5600 case 0x6827: 5601 si_pi->max_cu = 10; 5602 break; 5603 case 0x682D: 5604 case 0x6824: 5605 case 0x682F: 5606 case 0x6826: 5607 si_pi->max_cu = 8; 5608 break; 5609 case 0x6828: 5610 case 0x6830: 5611 case 0x6831: 5612 case 0x6838: 5613 case 0x6839: 5614 case 0x683D: 5615 si_pi->max_cu = 10; 5616 break; 5617 case 0x683B: 5618 case 0x683F: 5619 case 0x6829: 5620 si_pi->max_cu = 8; 5621 break; 5622 default: 5623 si_pi->max_cu = 0; 5624 break; 5625 } 5626 } else { 5627 si_pi->max_cu = 0; 5628 } 5629 } 5630 5631 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5632 struct radeon_clock_voltage_dependency_table *table) 5633 { 5634 u32 i; 5635 int j; 5636 u16 leakage_voltage; 5637 5638 if (table) { 5639 for (i = 0; i < table->count; i++) { 5640 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5641 table->entries[i].v, 5642 &leakage_voltage)) { 5643 case 0: 5644 table->entries[i].v = leakage_voltage; 5645 break; 5646 case -EAGAIN: 5647 return -EINVAL; 5648 case -EINVAL: 5649 default: 5650 break; 5651 } 5652 } 5653 5654 for (j = (table->count - 2); j >= 0; j--) { 5655 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5656 table->entries[j].v : table->entries[j + 1].v; 5657 } 5658 } 5659 return 0; 5660 } 5661 5662 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5663 { 5664 int ret = 0; 5665 5666 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5667 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5668 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5669 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5670 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5671 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5672 return ret; 5673 } 5674 5675 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5676 struct radeon_ps *radeon_new_state, 5677 struct radeon_ps *radeon_current_state) 5678 { 5679 u32 lane_width; 5680 u32 new_lane_width = 5681 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5682 u32 current_lane_width = 5683 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5684 5685 if (new_lane_width != current_lane_width) { 5686 radeon_set_pcie_lanes(rdev, new_lane_width); 5687 lane_width = radeon_get_pcie_lanes(rdev); 5688 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5689 } 5690 } 5691 5692 void si_dpm_setup_asic(struct radeon_device *rdev) 5693 { 5694 rv770_get_memory_type(rdev); 5695 si_read_clock_registers(rdev); 5696 si_enable_acpi_power_management(rdev); 5697 } 5698 5699 static int si_set_thermal_temperature_range(struct radeon_device *rdev, 5700 int min_temp, int max_temp) 5701 { 5702 int low_temp = 0 * 1000; 5703 int high_temp = 255 * 1000; 5704 5705 if (low_temp < min_temp) 5706 low_temp = min_temp; 5707 if (high_temp > max_temp) 5708 high_temp = max_temp; 5709 if (high_temp < low_temp) { 5710 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5711 return -EINVAL; 5712 } 5713 5714 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5715 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5716 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5717 5718 rdev->pm.dpm.thermal.min_temp = low_temp; 5719 rdev->pm.dpm.thermal.max_temp = high_temp; 5720 5721 return 0; 5722 } 5723 5724 int si_dpm_enable(struct radeon_device *rdev) 5725 { 5726 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5727 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5728 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5729 int ret; 5730 5731 if (si_is_smc_running(rdev)) 5732 return -EINVAL; 5733 if (pi->voltage_control) 5734 si_enable_voltage_control(rdev, true); 5735 if (pi->mvdd_control) 5736 si_get_mvdd_configuration(rdev); 5737 if (pi->voltage_control) { 5738 ret = si_construct_voltage_tables(rdev); 5739 if (ret) { 5740 DRM_ERROR("si_construct_voltage_tables failed\n"); 5741 return ret; 5742 } 5743 } 5744 if (eg_pi->dynamic_ac_timing) { 5745 ret = si_initialize_mc_reg_table(rdev); 5746 if (ret) 5747 eg_pi->dynamic_ac_timing = false; 5748 } 5749 if (pi->dynamic_ss) 5750 si_enable_spread_spectrum(rdev, true); 5751 if (pi->thermal_protection) 5752 si_enable_thermal_protection(rdev, true); 5753 si_setup_bsp(rdev); 5754 si_program_git(rdev); 5755 si_program_tp(rdev); 5756 si_program_tpp(rdev); 5757 si_program_sstp(rdev); 5758 si_enable_display_gap(rdev); 5759 si_program_vc(rdev); 5760 ret = si_upload_firmware(rdev); 5761 if (ret) { 5762 DRM_ERROR("si_upload_firmware failed\n"); 5763 return ret; 5764 } 5765 ret = si_process_firmware_header(rdev); 5766 if (ret) { 5767 DRM_ERROR("si_process_firmware_header failed\n"); 5768 return ret; 5769 } 5770 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 5771 if (ret) { 5772 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 5773 return ret; 5774 } 5775 ret = si_init_smc_table(rdev); 5776 if (ret) { 5777 DRM_ERROR("si_init_smc_table failed\n"); 5778 return ret; 5779 } 5780 ret = si_init_smc_spll_table(rdev); 5781 if (ret) { 5782 DRM_ERROR("si_init_smc_spll_table failed\n"); 5783 return ret; 5784 } 5785 ret = si_init_arb_table_index(rdev); 5786 if (ret) { 5787 DRM_ERROR("si_init_arb_table_index failed\n"); 5788 return ret; 5789 } 5790 if (eg_pi->dynamic_ac_timing) { 5791 ret = si_populate_mc_reg_table(rdev, boot_ps); 5792 if (ret) { 5793 DRM_ERROR("si_populate_mc_reg_table failed\n"); 5794 return ret; 5795 } 5796 } 5797 ret = si_initialize_smc_cac_tables(rdev); 5798 if (ret) { 5799 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 5800 return ret; 5801 } 5802 ret = si_initialize_hardware_cac_manager(rdev); 5803 if (ret) { 5804 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 5805 return ret; 5806 } 5807 ret = si_initialize_smc_dte_tables(rdev); 5808 if (ret) { 5809 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 5810 return ret; 5811 } 5812 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 5813 if (ret) { 5814 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 5815 return ret; 5816 } 5817 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 5818 if (ret) { 5819 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 5820 return ret; 5821 } 5822 si_program_response_times(rdev); 5823 si_program_ds_registers(rdev); 5824 si_dpm_start_smc(rdev); 5825 ret = si_notify_smc_display_change(rdev, false); 5826 if (ret) { 5827 DRM_ERROR("si_notify_smc_display_change failed\n"); 5828 return ret; 5829 } 5830 si_enable_sclk_control(rdev, true); 5831 si_start_dpm(rdev); 5832 5833 if (rdev->irq.installed && 5834 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { 5835 PPSMC_Result result; 5836 5837 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 5838 if (ret) 5839 return ret; 5840 rdev->irq.dpm_thermal = true; 5841 radeon_irq_set(rdev); 5842 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5843 5844 if (result != PPSMC_Result_OK) 5845 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5846 } 5847 5848 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 5849 5850 ni_update_current_ps(rdev, boot_ps); 5851 5852 return 0; 5853 } 5854 5855 void si_dpm_disable(struct radeon_device *rdev) 5856 { 5857 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5858 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 5859 5860 if (!si_is_smc_running(rdev)) 5861 return; 5862 si_disable_ulv(rdev); 5863 si_clear_vc(rdev); 5864 if (pi->thermal_protection) 5865 si_enable_thermal_protection(rdev, false); 5866 si_enable_power_containment(rdev, boot_ps, false); 5867 si_enable_smc_cac(rdev, boot_ps, false); 5868 si_enable_spread_spectrum(rdev, false); 5869 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 5870 si_stop_dpm(rdev); 5871 si_reset_to_default(rdev); 5872 si_dpm_stop_smc(rdev); 5873 si_force_switch_to_arb_f0(rdev); 5874 5875 ni_update_current_ps(rdev, boot_ps); 5876 } 5877 5878 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 5879 { 5880 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5881 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 5882 struct radeon_ps *new_ps = &requested_ps; 5883 5884 ni_update_requested_ps(rdev, new_ps); 5885 5886 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 5887 5888 return 0; 5889 } 5890 5891 static int si_power_control_set_level(struct radeon_device *rdev) 5892 { 5893 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 5894 int ret; 5895 5896 ret = si_restrict_performance_levels_before_switch(rdev); 5897 if (ret) 5898 return ret; 5899 ret = si_halt_smc(rdev); 5900 if (ret) 5901 return ret; 5902 ret = si_populate_smc_tdp_limits(rdev, new_ps); 5903 if (ret) 5904 return ret; 5905 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 5906 if (ret) 5907 return ret; 5908 ret = si_resume_smc(rdev); 5909 if (ret) 5910 return ret; 5911 ret = si_set_sw_state(rdev); 5912 if (ret) 5913 return ret; 5914 return 0; 5915 } 5916 5917 int si_dpm_set_power_state(struct radeon_device *rdev) 5918 { 5919 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5920 struct radeon_ps *new_ps = &eg_pi->requested_rps; 5921 struct radeon_ps *old_ps = &eg_pi->current_rps; 5922 int ret; 5923 5924 ret = si_disable_ulv(rdev); 5925 if (ret) { 5926 DRM_ERROR("si_disable_ulv failed\n"); 5927 return ret; 5928 } 5929 ret = si_restrict_performance_levels_before_switch(rdev); 5930 if (ret) { 5931 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 5932 return ret; 5933 } 5934 if (eg_pi->pcie_performance_request) 5935 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 5936 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 5937 ret = si_enable_power_containment(rdev, new_ps, false); 5938 if (ret) { 5939 DRM_ERROR("si_enable_power_containment failed\n"); 5940 return ret; 5941 } 5942 ret = si_enable_smc_cac(rdev, new_ps, false); 5943 if (ret) { 5944 DRM_ERROR("si_enable_smc_cac failed\n"); 5945 return ret; 5946 } 5947 ret = si_halt_smc(rdev); 5948 if (ret) { 5949 DRM_ERROR("si_halt_smc failed\n"); 5950 return ret; 5951 } 5952 ret = si_upload_sw_state(rdev, new_ps); 5953 if (ret) { 5954 DRM_ERROR("si_upload_sw_state failed\n"); 5955 return ret; 5956 } 5957 ret = si_upload_smc_data(rdev); 5958 if (ret) { 5959 DRM_ERROR("si_upload_smc_data failed\n"); 5960 return ret; 5961 } 5962 ret = si_upload_ulv_state(rdev); 5963 if (ret) { 5964 DRM_ERROR("si_upload_ulv_state failed\n"); 5965 return ret; 5966 } 5967 if (eg_pi->dynamic_ac_timing) { 5968 ret = si_upload_mc_reg_table(rdev, new_ps); 5969 if (ret) { 5970 DRM_ERROR("si_upload_mc_reg_table failed\n"); 5971 return ret; 5972 } 5973 } 5974 ret = si_program_memory_timing_parameters(rdev, new_ps); 5975 if (ret) { 5976 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 5977 return ret; 5978 } 5979 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 5980 5981 ret = si_resume_smc(rdev); 5982 if (ret) { 5983 DRM_ERROR("si_resume_smc failed\n"); 5984 return ret; 5985 } 5986 ret = si_set_sw_state(rdev); 5987 if (ret) { 5988 DRM_ERROR("si_set_sw_state failed\n"); 5989 return ret; 5990 } 5991 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 5992 if (eg_pi->pcie_performance_request) 5993 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 5994 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 5995 if (ret) { 5996 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 5997 return ret; 5998 } 5999 ret = si_enable_smc_cac(rdev, new_ps, true); 6000 if (ret) { 6001 DRM_ERROR("si_enable_smc_cac failed\n"); 6002 return ret; 6003 } 6004 ret = si_enable_power_containment(rdev, new_ps, true); 6005 if (ret) { 6006 DRM_ERROR("si_enable_power_containment failed\n"); 6007 return ret; 6008 } 6009 6010 ret = si_power_control_set_level(rdev); 6011 if (ret) { 6012 DRM_ERROR("si_power_control_set_level failed\n"); 6013 return ret; 6014 } 6015 6016 #if 0 6017 /* XXX */ 6018 ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); 6019 if (ret) { 6020 DRM_ERROR("si_dpm_force_performance_level failed\n"); 6021 return ret; 6022 } 6023 #else 6024 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 6025 #endif 6026 6027 return 0; 6028 } 6029 6030 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6031 { 6032 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6033 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6034 6035 ni_update_current_ps(rdev, new_ps); 6036 } 6037 6038 6039 void si_dpm_reset_asic(struct radeon_device *rdev) 6040 { 6041 si_restrict_performance_levels_before_switch(rdev); 6042 si_disable_ulv(rdev); 6043 si_set_boot_state(rdev); 6044 } 6045 6046 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6047 { 6048 si_program_display_gap(rdev); 6049 } 6050 6051 union power_info { 6052 struct _ATOM_POWERPLAY_INFO info; 6053 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6054 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6055 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6056 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6057 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6058 }; 6059 6060 union pplib_clock_info { 6061 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6062 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6063 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6064 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6065 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6066 }; 6067 6068 union pplib_power_state { 6069 struct _ATOM_PPLIB_STATE v1; 6070 struct _ATOM_PPLIB_STATE_V2 v2; 6071 }; 6072 6073 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6074 struct radeon_ps *rps, 6075 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6076 u8 table_rev) 6077 { 6078 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6079 rps->class = le16_to_cpu(non_clock_info->usClassification); 6080 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6081 6082 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6083 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6084 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6085 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6086 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6087 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6088 } else { 6089 rps->vclk = 0; 6090 rps->dclk = 0; 6091 } 6092 6093 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6094 rdev->pm.dpm.boot_ps = rps; 6095 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6096 rdev->pm.dpm.uvd_ps = rps; 6097 } 6098 6099 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6100 struct radeon_ps *rps, int index, 6101 union pplib_clock_info *clock_info) 6102 { 6103 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6104 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6105 struct si_power_info *si_pi = si_get_pi(rdev); 6106 struct ni_ps *ps = ni_get_ps(rps); 6107 u16 leakage_voltage; 6108 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6109 int ret; 6110 6111 ps->performance_level_count = index + 1; 6112 6113 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6114 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6115 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6116 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6117 6118 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6119 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6120 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6121 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6122 si_pi->sys_pcie_mask, 6123 si_pi->boot_pcie_gen, 6124 clock_info->si.ucPCIEGen); 6125 6126 /* patch up vddc if necessary */ 6127 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6128 &leakage_voltage); 6129 if (ret == 0) 6130 pl->vddc = leakage_voltage; 6131 6132 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6133 pi->acpi_vddc = pl->vddc; 6134 eg_pi->acpi_vddci = pl->vddci; 6135 si_pi->acpi_pcie_gen = pl->pcie_gen; 6136 } 6137 6138 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6139 index == 0) { 6140 /* XXX disable for A0 tahiti */ 6141 si_pi->ulv.supported = true; 6142 si_pi->ulv.pl = *pl; 6143 si_pi->ulv.one_pcie_lane_in_ulv = false; 6144 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6145 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6146 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6147 } 6148 6149 if (pi->min_vddc_in_table > pl->vddc) 6150 pi->min_vddc_in_table = pl->vddc; 6151 6152 if (pi->max_vddc_in_table < pl->vddc) 6153 pi->max_vddc_in_table = pl->vddc; 6154 6155 /* patch up boot state */ 6156 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6157 u16 vddc, vddci, mvdd; 6158 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6159 pl->mclk = rdev->clock.default_mclk; 6160 pl->sclk = rdev->clock.default_sclk; 6161 pl->vddc = vddc; 6162 pl->vddci = vddci; 6163 si_pi->mvdd_bootup_value = mvdd; 6164 } 6165 6166 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6167 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6168 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6169 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6170 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6171 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6172 } 6173 } 6174 6175 static int si_parse_power_table(struct radeon_device *rdev) 6176 { 6177 struct radeon_mode_info *mode_info = &rdev->mode_info; 6178 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6179 union pplib_power_state *power_state; 6180 int i, j, k, non_clock_array_index, clock_array_index; 6181 union pplib_clock_info *clock_info; 6182 struct _StateArray *state_array; 6183 struct _ClockInfoArray *clock_info_array; 6184 struct _NonClockInfoArray *non_clock_info_array; 6185 union power_info *power_info; 6186 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6187 u16 data_offset; 6188 u8 frev, crev; 6189 u8 *power_state_offset; 6190 struct ni_ps *ps; 6191 6192 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6193 &frev, &crev, &data_offset)) 6194 return -EINVAL; 6195 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6196 6197 state_array = (struct _StateArray *) 6198 (mode_info->atom_context->bios + data_offset + 6199 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6200 clock_info_array = (struct _ClockInfoArray *) 6201 (mode_info->atom_context->bios + data_offset + 6202 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6203 non_clock_info_array = (struct _NonClockInfoArray *) 6204 (mode_info->atom_context->bios + data_offset + 6205 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6206 6207 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6208 state_array->ucNumEntries, GFP_KERNEL); 6209 if (!rdev->pm.dpm.ps) 6210 return -ENOMEM; 6211 power_state_offset = (u8 *)state_array->states; 6212 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); 6213 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); 6214 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); 6215 for (i = 0; i < state_array->ucNumEntries; i++) { 6216 power_state = (union pplib_power_state *)power_state_offset; 6217 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6218 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6219 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6220 if (!rdev->pm.power_state[i].clock_info) 6221 return -EINVAL; 6222 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6223 if (ps == NULL) { 6224 kfree(rdev->pm.dpm.ps); 6225 return -ENOMEM; 6226 } 6227 rdev->pm.dpm.ps[i].ps_priv = ps; 6228 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6229 non_clock_info, 6230 non_clock_info_array->ucEntrySize); 6231 k = 0; 6232 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6233 clock_array_index = power_state->v2.clockInfoIndex[j]; 6234 if (clock_array_index >= clock_info_array->ucNumEntries) 6235 continue; 6236 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6237 break; 6238 clock_info = (union pplib_clock_info *) 6239 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6240 si_parse_pplib_clock_info(rdev, 6241 &rdev->pm.dpm.ps[i], k, 6242 clock_info); 6243 k++; 6244 } 6245 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6246 } 6247 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6248 return 0; 6249 } 6250 6251 int si_dpm_init(struct radeon_device *rdev) 6252 { 6253 struct rv7xx_power_info *pi; 6254 struct evergreen_power_info *eg_pi; 6255 struct ni_power_info *ni_pi; 6256 struct si_power_info *si_pi; 6257 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 6258 u16 data_offset, size; 6259 u8 frev, crev; 6260 struct atom_clock_dividers dividers; 6261 int ret; 6262 u32 mask; 6263 6264 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6265 if (si_pi == NULL) 6266 return -ENOMEM; 6267 rdev->pm.dpm.priv = si_pi; 6268 ni_pi = &si_pi->ni; 6269 eg_pi = &ni_pi->eg; 6270 pi = &eg_pi->rv7xx; 6271 6272 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6273 if (ret) 6274 si_pi->sys_pcie_mask = 0; 6275 else 6276 si_pi->sys_pcie_mask = mask; 6277 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6278 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6279 6280 si_set_max_cu_value(rdev); 6281 6282 rv770_get_max_vddc(rdev); 6283 si_get_leakage_vddc(rdev); 6284 si_patch_dependency_tables_based_on_leakage(rdev); 6285 6286 pi->acpi_vddc = 0; 6287 eg_pi->acpi_vddci = 0; 6288 pi->min_vddc_in_table = 0; 6289 pi->max_vddc_in_table = 0; 6290 6291 ret = si_parse_power_table(rdev); 6292 if (ret) 6293 return ret; 6294 ret = r600_parse_extended_power_table(rdev); 6295 if (ret) 6296 return ret; 6297 6298 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6299 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6300 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6301 r600_free_extended_power_table(rdev); 6302 return -ENOMEM; 6303 } 6304 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6305 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6306 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6307 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6308 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6309 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6310 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6311 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6312 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6313 6314 if (rdev->pm.dpm.voltage_response_time == 0) 6315 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6316 if (rdev->pm.dpm.backbias_response_time == 0) 6317 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6318 6319 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6320 0, false, ÷rs); 6321 if (ret) 6322 pi->ref_div = dividers.ref_div + 1; 6323 else 6324 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6325 6326 eg_pi->smu_uvd_hs = false; 6327 6328 pi->mclk_strobe_mode_threshold = 40000; 6329 if (si_is_special_1gb_platform(rdev)) 6330 pi->mclk_stutter_mode_threshold = 0; 6331 else 6332 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6333 pi->mclk_edc_enable_threshold = 40000; 6334 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6335 6336 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6337 6338 pi->voltage_control = 6339 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT); 6340 6341 pi->mvdd_control = 6342 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT); 6343 6344 eg_pi->vddci_control = 6345 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT); 6346 6347 si_pi->vddc_phase_shed_control = 6348 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT); 6349 6350 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 6351 &frev, &crev, &data_offset)) { 6352 pi->sclk_ss = true; 6353 pi->mclk_ss = true; 6354 pi->dynamic_ss = true; 6355 } else { 6356 pi->sclk_ss = false; 6357 pi->mclk_ss = false; 6358 pi->dynamic_ss = true; 6359 } 6360 6361 pi->asi = RV770_ASI_DFLT; 6362 pi->pasi = CYPRESS_HASI_DFLT; 6363 pi->vrc = SISLANDS_VRC_DFLT; 6364 6365 pi->gfx_clock_gating = true; 6366 6367 eg_pi->sclk_deep_sleep = true; 6368 si_pi->sclk_deep_sleep_above_low = false; 6369 6370 if (pi->gfx_clock_gating && 6371 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) 6372 pi->thermal_protection = true; 6373 else 6374 pi->thermal_protection = false; 6375 6376 eg_pi->dynamic_ac_timing = true; 6377 6378 eg_pi->light_sleep = true; 6379 #if defined(CONFIG_ACPI) 6380 eg_pi->pcie_performance_request = 6381 radeon_acpi_is_pcie_performance_request_supported(rdev); 6382 #else 6383 eg_pi->pcie_performance_request = false; 6384 #endif 6385 6386 si_pi->sram_end = SMC_RAM_END; 6387 6388 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6389 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6390 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6391 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6392 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6393 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6394 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6395 6396 si_initialize_powertune_defaults(rdev); 6397 6398 return 0; 6399 } 6400 6401 void si_dpm_fini(struct radeon_device *rdev) 6402 { 6403 int i; 6404 6405 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6406 kfree(rdev->pm.dpm.ps[i].ps_priv); 6407 } 6408 kfree(rdev->pm.dpm.ps); 6409 kfree(rdev->pm.dpm.priv); 6410 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6411 r600_free_extended_power_table(rdev); 6412 } 6413 6414 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6415 struct seq_file *m) 6416 { 6417 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 6418 struct ni_ps *ps = ni_get_ps(rps); 6419 struct rv7xx_pl *pl; 6420 u32 current_index = 6421 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6422 CURRENT_STATE_INDEX_SHIFT; 6423 6424 if (current_index >= ps->performance_level_count) { 6425 seq_printf(m, "invalid dpm profile %d\n", current_index); 6426 } else { 6427 pl = &ps->performance_levels[current_index]; 6428 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6429 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6430 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 6431 } 6432 } 6433