1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include "drmP.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "radeon_drm.h" 35 #include "rv770d.h" 36 #include "atom.h" 37 #include "avivod.h" 38 39 #define R700_PFP_UCODE_SIZE 848 40 #define R700_PM4_UCODE_SIZE 1360 41 42 static void rv770_gpu_init(struct radeon_device *rdev); 43 void rv770_fini(struct radeon_device *rdev); 44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 45 46 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 47 { 48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 50 51 /* Lock the graphics update lock */ 52 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 53 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 54 55 /* update the scanout addresses */ 56 if (radeon_crtc->crtc_id) { 57 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 58 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 59 } else { 60 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 61 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); 62 } 63 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 64 (u32)crtc_base); 65 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 66 (u32)crtc_base); 67 68 /* Wait for update_pending to go high. */ 69 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)); 70 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 71 72 /* Unlock the lock, so double-buffering can take place inside vblank */ 73 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 74 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 75 76 /* Return current update_pending status: */ 77 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 78 } 79 80 /* get temperature in millidegrees */ 81 int rv770_get_temp(struct radeon_device *rdev) 82 { 83 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 84 ASIC_T_SHIFT; 85 int actual_temp; 86 87 if (temp & 0x400) 88 actual_temp = -256; 89 else if (temp & 0x200) 90 actual_temp = 255; 91 else if (temp & 0x100) { 92 actual_temp = temp & 0x1ff; 93 actual_temp |= ~0x1ff; 94 } else 95 actual_temp = temp & 0xff; 96 97 return (actual_temp * 1000) / 2; 98 } 99 100 void rv770_pm_misc(struct radeon_device *rdev) 101 { 102 int req_ps_idx = rdev->pm.requested_power_state_index; 103 int req_cm_idx = rdev->pm.requested_clock_mode_index; 104 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 105 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 106 107 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 108 /* 0xff01 is a flag rather then an actual voltage */ 109 if (voltage->voltage == 0xff01) 110 return; 111 if (voltage->voltage != rdev->pm.current_vddc) { 112 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 113 rdev->pm.current_vddc = voltage->voltage; 114 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 115 } 116 } 117 } 118 119 /* 120 * GART 121 */ 122 int rv770_pcie_gart_enable(struct radeon_device *rdev) 123 { 124 u32 tmp; 125 int r, i; 126 127 if (rdev->gart.robj == NULL) { 128 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 129 return -EINVAL; 130 } 131 r = radeon_gart_table_vram_pin(rdev); 132 if (r) 133 return r; 134 radeon_gart_restore(rdev); 135 /* Setup L2 cache */ 136 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 137 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 138 EFFECTIVE_L2_QUEUE_SIZE(7)); 139 WREG32(VM_L2_CNTL2, 0); 140 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 141 /* Setup TLB control */ 142 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 143 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 144 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 145 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 146 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 147 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 148 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 149 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 150 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 151 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 152 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 153 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 154 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 155 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 156 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 157 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 158 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 159 (u32)(rdev->dummy_page.addr >> 12)); 160 for (i = 1; i < 7; i++) 161 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 162 163 r600_pcie_gart_tlb_flush(rdev); 164 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 165 (unsigned)(rdev->mc.gtt_size >> 20), 166 (unsigned long long)rdev->gart.table_addr); 167 rdev->gart.ready = true; 168 return 0; 169 } 170 171 void rv770_pcie_gart_disable(struct radeon_device *rdev) 172 { 173 u32 tmp; 174 int i; 175 176 /* Disable all tables */ 177 for (i = 0; i < 7; i++) 178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 179 180 /* Setup L2 cache */ 181 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 182 EFFECTIVE_L2_QUEUE_SIZE(7)); 183 WREG32(VM_L2_CNTL2, 0); 184 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 185 /* Setup TLB control */ 186 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 187 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 188 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 189 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 190 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 191 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 192 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 193 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 194 radeon_gart_table_vram_unpin(rdev); 195 } 196 197 void rv770_pcie_gart_fini(struct radeon_device *rdev) 198 { 199 radeon_gart_fini(rdev); 200 rv770_pcie_gart_disable(rdev); 201 radeon_gart_table_vram_free(rdev); 202 } 203 204 205 void rv770_agp_enable(struct radeon_device *rdev) 206 { 207 u32 tmp; 208 int i; 209 210 /* Setup L2 cache */ 211 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 212 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 213 EFFECTIVE_L2_QUEUE_SIZE(7)); 214 WREG32(VM_L2_CNTL2, 0); 215 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 216 /* Setup TLB control */ 217 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 218 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 219 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 220 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 221 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 222 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 223 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 224 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 225 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 226 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 227 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 228 for (i = 0; i < 7; i++) 229 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 230 } 231 232 static void rv770_mc_program(struct radeon_device *rdev) 233 { 234 struct rv515_mc_save save; 235 u32 tmp; 236 int i, j; 237 238 /* Initialize HDP */ 239 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 240 WREG32((0x2c14 + j), 0x00000000); 241 WREG32((0x2c18 + j), 0x00000000); 242 WREG32((0x2c1c + j), 0x00000000); 243 WREG32((0x2c20 + j), 0x00000000); 244 WREG32((0x2c24 + j), 0x00000000); 245 } 246 /* r7xx hw bug. Read from HDP_DEBUG1 rather 247 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL 248 */ 249 tmp = RREG32(HDP_DEBUG1); 250 251 rv515_mc_stop(rdev, &save); 252 if (r600_mc_wait_for_idle(rdev)) { 253 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 254 } 255 /* Lockout access through VGA aperture*/ 256 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 257 /* Update configuration */ 258 if (rdev->flags & RADEON_IS_AGP) { 259 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 260 /* VRAM before AGP */ 261 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 262 rdev->mc.vram_start >> 12); 263 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 264 rdev->mc.gtt_end >> 12); 265 } else { 266 /* VRAM after AGP */ 267 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 268 rdev->mc.gtt_start >> 12); 269 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 270 rdev->mc.vram_end >> 12); 271 } 272 } else { 273 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 274 rdev->mc.vram_start >> 12); 275 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 276 rdev->mc.vram_end >> 12); 277 } 278 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 279 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 280 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 281 WREG32(MC_VM_FB_LOCATION, tmp); 282 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 283 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 284 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 285 if (rdev->flags & RADEON_IS_AGP) { 286 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 287 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 288 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 289 } else { 290 WREG32(MC_VM_AGP_BASE, 0); 291 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 292 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 293 } 294 if (r600_mc_wait_for_idle(rdev)) { 295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 296 } 297 rv515_mc_resume(rdev, &save); 298 /* we need to own VRAM, so turn off the VGA renderer here 299 * to stop it overwriting our objects */ 300 rv515_vga_render_disable(rdev); 301 } 302 303 304 /* 305 * CP. 306 */ 307 void r700_cp_stop(struct radeon_device *rdev) 308 { 309 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 310 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 311 WREG32(SCRATCH_UMSK, 0); 312 } 313 314 static int rv770_cp_load_microcode(struct radeon_device *rdev) 315 { 316 const __be32 *fw_data; 317 int i; 318 319 if (!rdev->me_fw || !rdev->pfp_fw) 320 return -EINVAL; 321 322 r700_cp_stop(rdev); 323 WREG32(CP_RB_CNTL, 324 #ifdef __BIG_ENDIAN 325 BUF_SWAP_32BIT | 326 #endif 327 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 328 329 /* Reset cp */ 330 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 331 RREG32(GRBM_SOFT_RESET); 332 mdelay(15); 333 WREG32(GRBM_SOFT_RESET, 0); 334 335 fw_data = (const __be32 *)rdev->pfp_fw->data; 336 WREG32(CP_PFP_UCODE_ADDR, 0); 337 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 338 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 339 WREG32(CP_PFP_UCODE_ADDR, 0); 340 341 fw_data = (const __be32 *)rdev->me_fw->data; 342 WREG32(CP_ME_RAM_WADDR, 0); 343 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 344 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 345 346 WREG32(CP_PFP_UCODE_ADDR, 0); 347 WREG32(CP_ME_RAM_WADDR, 0); 348 WREG32(CP_ME_RAM_RADDR, 0); 349 return 0; 350 } 351 352 void r700_cp_fini(struct radeon_device *rdev) 353 { 354 r700_cp_stop(rdev); 355 radeon_ring_fini(rdev); 356 } 357 358 /* 359 * Core functions 360 */ 361 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 362 u32 num_tile_pipes, 363 u32 num_backends, 364 u32 backend_disable_mask) 365 { 366 u32 backend_map = 0; 367 u32 enabled_backends_mask; 368 u32 enabled_backends_count; 369 u32 cur_pipe; 370 u32 swizzle_pipe[R7XX_MAX_PIPES]; 371 u32 cur_backend; 372 u32 i; 373 bool force_no_swizzle; 374 375 if (num_tile_pipes > R7XX_MAX_PIPES) 376 num_tile_pipes = R7XX_MAX_PIPES; 377 if (num_tile_pipes < 1) 378 num_tile_pipes = 1; 379 if (num_backends > R7XX_MAX_BACKENDS) 380 num_backends = R7XX_MAX_BACKENDS; 381 if (num_backends < 1) 382 num_backends = 1; 383 384 enabled_backends_mask = 0; 385 enabled_backends_count = 0; 386 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 387 if (((backend_disable_mask >> i) & 1) == 0) { 388 enabled_backends_mask |= (1 << i); 389 ++enabled_backends_count; 390 } 391 if (enabled_backends_count == num_backends) 392 break; 393 } 394 395 if (enabled_backends_count == 0) { 396 enabled_backends_mask = 1; 397 enabled_backends_count = 1; 398 } 399 400 if (enabled_backends_count != num_backends) 401 num_backends = enabled_backends_count; 402 403 switch (rdev->family) { 404 case CHIP_RV770: 405 case CHIP_RV730: 406 force_no_swizzle = false; 407 break; 408 case CHIP_RV710: 409 case CHIP_RV740: 410 default: 411 force_no_swizzle = true; 412 break; 413 } 414 415 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 416 switch (num_tile_pipes) { 417 case 1: 418 swizzle_pipe[0] = 0; 419 break; 420 case 2: 421 swizzle_pipe[0] = 0; 422 swizzle_pipe[1] = 1; 423 break; 424 case 3: 425 if (force_no_swizzle) { 426 swizzle_pipe[0] = 0; 427 swizzle_pipe[1] = 1; 428 swizzle_pipe[2] = 2; 429 } else { 430 swizzle_pipe[0] = 0; 431 swizzle_pipe[1] = 2; 432 swizzle_pipe[2] = 1; 433 } 434 break; 435 case 4: 436 if (force_no_swizzle) { 437 swizzle_pipe[0] = 0; 438 swizzle_pipe[1] = 1; 439 swizzle_pipe[2] = 2; 440 swizzle_pipe[3] = 3; 441 } else { 442 swizzle_pipe[0] = 0; 443 swizzle_pipe[1] = 2; 444 swizzle_pipe[2] = 3; 445 swizzle_pipe[3] = 1; 446 } 447 break; 448 case 5: 449 if (force_no_swizzle) { 450 swizzle_pipe[0] = 0; 451 swizzle_pipe[1] = 1; 452 swizzle_pipe[2] = 2; 453 swizzle_pipe[3] = 3; 454 swizzle_pipe[4] = 4; 455 } else { 456 swizzle_pipe[0] = 0; 457 swizzle_pipe[1] = 2; 458 swizzle_pipe[2] = 4; 459 swizzle_pipe[3] = 1; 460 swizzle_pipe[4] = 3; 461 } 462 break; 463 case 6: 464 if (force_no_swizzle) { 465 swizzle_pipe[0] = 0; 466 swizzle_pipe[1] = 1; 467 swizzle_pipe[2] = 2; 468 swizzle_pipe[3] = 3; 469 swizzle_pipe[4] = 4; 470 swizzle_pipe[5] = 5; 471 } else { 472 swizzle_pipe[0] = 0; 473 swizzle_pipe[1] = 2; 474 swizzle_pipe[2] = 4; 475 swizzle_pipe[3] = 5; 476 swizzle_pipe[4] = 3; 477 swizzle_pipe[5] = 1; 478 } 479 break; 480 case 7: 481 if (force_no_swizzle) { 482 swizzle_pipe[0] = 0; 483 swizzle_pipe[1] = 1; 484 swizzle_pipe[2] = 2; 485 swizzle_pipe[3] = 3; 486 swizzle_pipe[4] = 4; 487 swizzle_pipe[5] = 5; 488 swizzle_pipe[6] = 6; 489 } else { 490 swizzle_pipe[0] = 0; 491 swizzle_pipe[1] = 2; 492 swizzle_pipe[2] = 4; 493 swizzle_pipe[3] = 6; 494 swizzle_pipe[4] = 3; 495 swizzle_pipe[5] = 1; 496 swizzle_pipe[6] = 5; 497 } 498 break; 499 case 8: 500 if (force_no_swizzle) { 501 swizzle_pipe[0] = 0; 502 swizzle_pipe[1] = 1; 503 swizzle_pipe[2] = 2; 504 swizzle_pipe[3] = 3; 505 swizzle_pipe[4] = 4; 506 swizzle_pipe[5] = 5; 507 swizzle_pipe[6] = 6; 508 swizzle_pipe[7] = 7; 509 } else { 510 swizzle_pipe[0] = 0; 511 swizzle_pipe[1] = 2; 512 swizzle_pipe[2] = 4; 513 swizzle_pipe[3] = 6; 514 swizzle_pipe[4] = 3; 515 swizzle_pipe[5] = 1; 516 swizzle_pipe[6] = 7; 517 swizzle_pipe[7] = 5; 518 } 519 break; 520 } 521 522 cur_backend = 0; 523 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 524 while (((1 << cur_backend) & enabled_backends_mask) == 0) 525 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 526 527 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 528 529 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 530 } 531 532 return backend_map; 533 } 534 535 static void rv770_gpu_init(struct radeon_device *rdev) 536 { 537 int i, j, num_qd_pipes; 538 u32 ta_aux_cntl; 539 u32 sx_debug_1; 540 u32 smx_dc_ctl0; 541 u32 db_debug3; 542 u32 num_gs_verts_per_thread; 543 u32 vgt_gs_per_es; 544 u32 gs_prim_buffer_depth = 0; 545 u32 sq_ms_fifo_sizes; 546 u32 sq_config; 547 u32 sq_thread_resource_mgmt; 548 u32 hdp_host_path_cntl; 549 u32 sq_dyn_gpr_size_simd_ab_0; 550 u32 backend_map; 551 u32 gb_tiling_config = 0; 552 u32 cc_rb_backend_disable = 0; 553 u32 cc_gc_shader_pipe_config = 0; 554 u32 mc_arb_ramcfg; 555 u32 db_debug4; 556 557 /* setup chip specs */ 558 switch (rdev->family) { 559 case CHIP_RV770: 560 rdev->config.rv770.max_pipes = 4; 561 rdev->config.rv770.max_tile_pipes = 8; 562 rdev->config.rv770.max_simds = 10; 563 rdev->config.rv770.max_backends = 4; 564 rdev->config.rv770.max_gprs = 256; 565 rdev->config.rv770.max_threads = 248; 566 rdev->config.rv770.max_stack_entries = 512; 567 rdev->config.rv770.max_hw_contexts = 8; 568 rdev->config.rv770.max_gs_threads = 16 * 2; 569 rdev->config.rv770.sx_max_export_size = 128; 570 rdev->config.rv770.sx_max_export_pos_size = 16; 571 rdev->config.rv770.sx_max_export_smx_size = 112; 572 rdev->config.rv770.sq_num_cf_insts = 2; 573 574 rdev->config.rv770.sx_num_of_sets = 7; 575 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 576 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 577 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 578 break; 579 case CHIP_RV730: 580 rdev->config.rv770.max_pipes = 2; 581 rdev->config.rv770.max_tile_pipes = 4; 582 rdev->config.rv770.max_simds = 8; 583 rdev->config.rv770.max_backends = 2; 584 rdev->config.rv770.max_gprs = 128; 585 rdev->config.rv770.max_threads = 248; 586 rdev->config.rv770.max_stack_entries = 256; 587 rdev->config.rv770.max_hw_contexts = 8; 588 rdev->config.rv770.max_gs_threads = 16 * 2; 589 rdev->config.rv770.sx_max_export_size = 256; 590 rdev->config.rv770.sx_max_export_pos_size = 32; 591 rdev->config.rv770.sx_max_export_smx_size = 224; 592 rdev->config.rv770.sq_num_cf_insts = 2; 593 594 rdev->config.rv770.sx_num_of_sets = 7; 595 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 596 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 597 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 598 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 599 rdev->config.rv770.sx_max_export_pos_size -= 16; 600 rdev->config.rv770.sx_max_export_smx_size += 16; 601 } 602 break; 603 case CHIP_RV710: 604 rdev->config.rv770.max_pipes = 2; 605 rdev->config.rv770.max_tile_pipes = 2; 606 rdev->config.rv770.max_simds = 2; 607 rdev->config.rv770.max_backends = 1; 608 rdev->config.rv770.max_gprs = 256; 609 rdev->config.rv770.max_threads = 192; 610 rdev->config.rv770.max_stack_entries = 256; 611 rdev->config.rv770.max_hw_contexts = 4; 612 rdev->config.rv770.max_gs_threads = 8 * 2; 613 rdev->config.rv770.sx_max_export_size = 128; 614 rdev->config.rv770.sx_max_export_pos_size = 16; 615 rdev->config.rv770.sx_max_export_smx_size = 112; 616 rdev->config.rv770.sq_num_cf_insts = 1; 617 618 rdev->config.rv770.sx_num_of_sets = 7; 619 rdev->config.rv770.sc_prim_fifo_size = 0x40; 620 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 621 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 622 break; 623 case CHIP_RV740: 624 rdev->config.rv770.max_pipes = 4; 625 rdev->config.rv770.max_tile_pipes = 4; 626 rdev->config.rv770.max_simds = 8; 627 rdev->config.rv770.max_backends = 4; 628 rdev->config.rv770.max_gprs = 256; 629 rdev->config.rv770.max_threads = 248; 630 rdev->config.rv770.max_stack_entries = 512; 631 rdev->config.rv770.max_hw_contexts = 8; 632 rdev->config.rv770.max_gs_threads = 16 * 2; 633 rdev->config.rv770.sx_max_export_size = 256; 634 rdev->config.rv770.sx_max_export_pos_size = 32; 635 rdev->config.rv770.sx_max_export_smx_size = 224; 636 rdev->config.rv770.sq_num_cf_insts = 2; 637 638 rdev->config.rv770.sx_num_of_sets = 7; 639 rdev->config.rv770.sc_prim_fifo_size = 0x100; 640 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 641 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 642 643 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 644 rdev->config.rv770.sx_max_export_pos_size -= 16; 645 rdev->config.rv770.sx_max_export_smx_size += 16; 646 } 647 break; 648 default: 649 break; 650 } 651 652 /* Initialize HDP */ 653 j = 0; 654 for (i = 0; i < 32; i++) { 655 WREG32((0x2c14 + j), 0x00000000); 656 WREG32((0x2c18 + j), 0x00000000); 657 WREG32((0x2c1c + j), 0x00000000); 658 WREG32((0x2c20 + j), 0x00000000); 659 WREG32((0x2c24 + j), 0x00000000); 660 j += 0x18; 661 } 662 663 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 664 665 /* setup tiling, simd, pipe config */ 666 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 667 668 switch (rdev->config.rv770.max_tile_pipes) { 669 case 1: 670 default: 671 gb_tiling_config |= PIPE_TILING(0); 672 break; 673 case 2: 674 gb_tiling_config |= PIPE_TILING(1); 675 break; 676 case 4: 677 gb_tiling_config |= PIPE_TILING(2); 678 break; 679 case 8: 680 gb_tiling_config |= PIPE_TILING(3); 681 break; 682 } 683 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 684 685 if (rdev->family == CHIP_RV770) 686 gb_tiling_config |= BANK_TILING(1); 687 else 688 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 689 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 690 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 691 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) 692 rdev->config.rv770.tiling_group_size = 512; 693 else 694 rdev->config.rv770.tiling_group_size = 256; 695 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 696 gb_tiling_config |= ROW_TILING(3); 697 gb_tiling_config |= SAMPLE_SPLIT(3); 698 } else { 699 gb_tiling_config |= 700 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 701 gb_tiling_config |= 702 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 703 } 704 705 gb_tiling_config |= BANK_SWAPS(1); 706 707 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 708 cc_rb_backend_disable |= 709 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 710 711 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 712 cc_gc_shader_pipe_config |= 713 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 714 cc_gc_shader_pipe_config |= 715 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 716 717 if (rdev->family == CHIP_RV740) 718 backend_map = 0x28; 719 else 720 backend_map = r700_get_tile_pipe_to_backend_map(rdev, 721 rdev->config.rv770.max_tile_pipes, 722 (R7XX_MAX_BACKENDS - 723 r600_count_pipe_bits((cc_rb_backend_disable & 724 R7XX_MAX_BACKENDS_MASK) >> 16)), 725 (cc_rb_backend_disable >> 16)); 726 727 rdev->config.rv770.tile_config = gb_tiling_config; 728 rdev->config.rv770.backend_map = backend_map; 729 gb_tiling_config |= BACKEND_MAP(backend_map); 730 731 WREG32(GB_TILING_CONFIG, gb_tiling_config); 732 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 733 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 734 735 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 736 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 737 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 738 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 739 740 WREG32(CGTS_SYS_TCC_DISABLE, 0); 741 WREG32(CGTS_TCC_DISABLE, 0); 742 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 743 WREG32(CGTS_USER_TCC_DISABLE, 0); 744 745 num_qd_pipes = 746 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 747 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 748 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 749 750 /* set HW defaults for 3D engine */ 751 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 752 ROQ_IB2_START(0x2b))); 753 754 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 755 756 ta_aux_cntl = RREG32(TA_CNTL_AUX); 757 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 758 759 sx_debug_1 = RREG32(SX_DEBUG_1); 760 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 761 WREG32(SX_DEBUG_1, sx_debug_1); 762 763 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 764 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 765 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 766 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 767 768 if (rdev->family != CHIP_RV740) 769 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 770 GS_FLUSH_CTL(4) | 771 ACK_FLUSH_CTL(3) | 772 SYNC_FLUSH_CTL)); 773 774 db_debug3 = RREG32(DB_DEBUG3); 775 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 776 switch (rdev->family) { 777 case CHIP_RV770: 778 case CHIP_RV740: 779 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 780 break; 781 case CHIP_RV710: 782 case CHIP_RV730: 783 default: 784 db_debug3 |= DB_CLK_OFF_DELAY(2); 785 break; 786 } 787 WREG32(DB_DEBUG3, db_debug3); 788 789 if (rdev->family != CHIP_RV770) { 790 db_debug4 = RREG32(DB_DEBUG4); 791 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 792 WREG32(DB_DEBUG4, db_debug4); 793 } 794 795 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 796 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 797 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 798 799 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 800 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 801 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 802 803 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 804 805 WREG32(VGT_NUM_INSTANCES, 1); 806 807 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 808 809 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 810 811 WREG32(CP_PERFMON_CNTL, 0); 812 813 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 814 DONE_FIFO_HIWATER(0xe0) | 815 ALU_UPDATE_FIFO_HIWATER(0x8)); 816 switch (rdev->family) { 817 case CHIP_RV770: 818 case CHIP_RV730: 819 case CHIP_RV710: 820 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 821 break; 822 case CHIP_RV740: 823 default: 824 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 825 break; 826 } 827 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 828 829 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 830 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 831 */ 832 sq_config = RREG32(SQ_CONFIG); 833 sq_config &= ~(PS_PRIO(3) | 834 VS_PRIO(3) | 835 GS_PRIO(3) | 836 ES_PRIO(3)); 837 sq_config |= (DX9_CONSTS | 838 VC_ENABLE | 839 EXPORT_SRC_C | 840 PS_PRIO(0) | 841 VS_PRIO(1) | 842 GS_PRIO(2) | 843 ES_PRIO(3)); 844 if (rdev->family == CHIP_RV710) 845 /* no vertex cache */ 846 sq_config &= ~VC_ENABLE; 847 848 WREG32(SQ_CONFIG, sq_config); 849 850 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 851 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 852 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 853 854 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 855 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 856 857 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 858 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 859 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 860 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 861 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 862 else 863 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 864 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 865 866 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 867 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 868 869 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 870 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 871 872 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 873 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 874 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 875 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 876 877 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 878 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 879 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 880 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 881 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 882 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 883 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 884 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 885 886 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 887 FORCE_EOV_MAX_REZ_CNT(255))); 888 889 if (rdev->family == CHIP_RV710) 890 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 891 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 892 else 893 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 894 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 895 896 switch (rdev->family) { 897 case CHIP_RV770: 898 case CHIP_RV730: 899 case CHIP_RV740: 900 gs_prim_buffer_depth = 384; 901 break; 902 case CHIP_RV710: 903 gs_prim_buffer_depth = 128; 904 break; 905 default: 906 break; 907 } 908 909 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 910 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 911 /* Max value for this is 256 */ 912 if (vgt_gs_per_es > 256) 913 vgt_gs_per_es = 256; 914 915 WREG32(VGT_ES_PER_GS, 128); 916 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 917 WREG32(VGT_GS_PER_VS, 2); 918 919 /* more default values. 2D/3D driver should adjust as needed */ 920 WREG32(VGT_GS_VERTEX_REUSE, 16); 921 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 922 WREG32(VGT_STRMOUT_EN, 0); 923 WREG32(SX_MISC, 0); 924 WREG32(PA_SC_MODE_CNTL, 0); 925 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 926 WREG32(PA_SC_AA_CONFIG, 0); 927 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 928 WREG32(PA_SC_LINE_STIPPLE, 0); 929 WREG32(SPI_INPUT_Z, 0); 930 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 931 WREG32(CB_COLOR7_FRAG, 0); 932 933 /* clear render buffer base addresses */ 934 WREG32(CB_COLOR0_BASE, 0); 935 WREG32(CB_COLOR1_BASE, 0); 936 WREG32(CB_COLOR2_BASE, 0); 937 WREG32(CB_COLOR3_BASE, 0); 938 WREG32(CB_COLOR4_BASE, 0); 939 WREG32(CB_COLOR5_BASE, 0); 940 WREG32(CB_COLOR6_BASE, 0); 941 WREG32(CB_COLOR7_BASE, 0); 942 943 WREG32(TCP_CNTL, 0); 944 945 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 946 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 947 948 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 949 950 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 951 NUM_CLIP_SEQ(3))); 952 953 } 954 955 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 956 { 957 u64 size_bf, size_af; 958 959 if (mc->mc_vram_size > 0xE0000000) { 960 /* leave room for at least 512M GTT */ 961 dev_warn(rdev->dev, "limiting VRAM\n"); 962 mc->real_vram_size = 0xE0000000; 963 mc->mc_vram_size = 0xE0000000; 964 } 965 if (rdev->flags & RADEON_IS_AGP) { 966 size_bf = mc->gtt_start; 967 size_af = 0xFFFFFFFF - mc->gtt_end + 1; 968 if (size_bf > size_af) { 969 if (mc->mc_vram_size > size_bf) { 970 dev_warn(rdev->dev, "limiting VRAM\n"); 971 mc->real_vram_size = size_bf; 972 mc->mc_vram_size = size_bf; 973 } 974 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 975 } else { 976 if (mc->mc_vram_size > size_af) { 977 dev_warn(rdev->dev, "limiting VRAM\n"); 978 mc->real_vram_size = size_af; 979 mc->mc_vram_size = size_af; 980 } 981 mc->vram_start = mc->gtt_end; 982 } 983 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 984 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 985 mc->mc_vram_size >> 20, mc->vram_start, 986 mc->vram_end, mc->real_vram_size >> 20); 987 } else { 988 radeon_vram_location(rdev, &rdev->mc, 0); 989 rdev->mc.gtt_base_align = 0; 990 radeon_gtt_location(rdev, mc); 991 } 992 } 993 994 int rv770_mc_init(struct radeon_device *rdev) 995 { 996 u32 tmp; 997 int chansize, numchan; 998 999 /* Get VRAM informations */ 1000 rdev->mc.vram_is_ddr = true; 1001 tmp = RREG32(MC_ARB_RAMCFG); 1002 if (tmp & CHANSIZE_OVERRIDE) { 1003 chansize = 16; 1004 } else if (tmp & CHANSIZE_MASK) { 1005 chansize = 64; 1006 } else { 1007 chansize = 32; 1008 } 1009 tmp = RREG32(MC_SHARED_CHMAP); 1010 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1011 case 0: 1012 default: 1013 numchan = 1; 1014 break; 1015 case 1: 1016 numchan = 2; 1017 break; 1018 case 2: 1019 numchan = 4; 1020 break; 1021 case 3: 1022 numchan = 8; 1023 break; 1024 } 1025 rdev->mc.vram_width = numchan * chansize; 1026 /* Could aper size report 0 ? */ 1027 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 1028 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 1029 /* Setup GPU memory space */ 1030 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1031 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1032 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1033 r700_vram_gtt_location(rdev, &rdev->mc); 1034 radeon_update_bandwidth_info(rdev); 1035 1036 return 0; 1037 } 1038 1039 static int rv770_startup(struct radeon_device *rdev) 1040 { 1041 int r; 1042 1043 /* enable pcie gen2 link */ 1044 rv770_pcie_gen2_enable(rdev); 1045 1046 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1047 r = r600_init_microcode(rdev); 1048 if (r) { 1049 DRM_ERROR("Failed to load firmware!\n"); 1050 return r; 1051 } 1052 } 1053 1054 r = r600_vram_scratch_init(rdev); 1055 if (r) 1056 return r; 1057 1058 rv770_mc_program(rdev); 1059 if (rdev->flags & RADEON_IS_AGP) { 1060 rv770_agp_enable(rdev); 1061 } else { 1062 r = rv770_pcie_gart_enable(rdev); 1063 if (r) 1064 return r; 1065 } 1066 1067 rv770_gpu_init(rdev); 1068 r = r600_blit_init(rdev); 1069 if (r) { 1070 r600_blit_fini(rdev); 1071 rdev->asic->copy = NULL; 1072 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1073 } 1074 1075 /* allocate wb buffer */ 1076 r = radeon_wb_init(rdev); 1077 if (r) 1078 return r; 1079 1080 /* Enable IRQ */ 1081 r = r600_irq_init(rdev); 1082 if (r) { 1083 DRM_ERROR("radeon: IH init failed (%d).\n", r); 1084 radeon_irq_kms_fini(rdev); 1085 return r; 1086 } 1087 r600_irq_set(rdev); 1088 1089 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1090 if (r) 1091 return r; 1092 r = rv770_cp_load_microcode(rdev); 1093 if (r) 1094 return r; 1095 r = r600_cp_resume(rdev); 1096 if (r) 1097 return r; 1098 1099 return 0; 1100 } 1101 1102 int rv770_resume(struct radeon_device *rdev) 1103 { 1104 int r; 1105 1106 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1107 * posting will perform necessary task to bring back GPU into good 1108 * shape. 1109 */ 1110 /* post card */ 1111 atom_asic_init(rdev->mode_info.atom_context); 1112 1113 r = rv770_startup(rdev); 1114 if (r) { 1115 DRM_ERROR("r600 startup failed on resume\n"); 1116 return r; 1117 } 1118 1119 r = r600_ib_test(rdev); 1120 if (r) { 1121 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 1122 return r; 1123 } 1124 1125 r = r600_audio_init(rdev); 1126 if (r) { 1127 dev_err(rdev->dev, "radeon: audio init failed\n"); 1128 return r; 1129 } 1130 1131 return r; 1132 1133 } 1134 1135 int rv770_suspend(struct radeon_device *rdev) 1136 { 1137 r600_audio_fini(rdev); 1138 /* FIXME: we should wait for ring to be empty */ 1139 r700_cp_stop(rdev); 1140 rdev->cp.ready = false; 1141 r600_irq_suspend(rdev); 1142 radeon_wb_disable(rdev); 1143 rv770_pcie_gart_disable(rdev); 1144 r600_blit_suspend(rdev); 1145 1146 return 0; 1147 } 1148 1149 /* Plan is to move initialization in that function and use 1150 * helper function so that radeon_device_init pretty much 1151 * do nothing more than calling asic specific function. This 1152 * should also allow to remove a bunch of callback function 1153 * like vram_info. 1154 */ 1155 int rv770_init(struct radeon_device *rdev) 1156 { 1157 int r; 1158 1159 /* This don't do much */ 1160 r = radeon_gem_init(rdev); 1161 if (r) 1162 return r; 1163 /* Read BIOS */ 1164 if (!radeon_get_bios(rdev)) { 1165 if (ASIC_IS_AVIVO(rdev)) 1166 return -EINVAL; 1167 } 1168 /* Must be an ATOMBIOS */ 1169 if (!rdev->is_atom_bios) { 1170 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1171 return -EINVAL; 1172 } 1173 r = radeon_atombios_init(rdev); 1174 if (r) 1175 return r; 1176 /* Post card if necessary */ 1177 if (!radeon_card_posted(rdev)) { 1178 if (!rdev->bios) { 1179 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1180 return -EINVAL; 1181 } 1182 DRM_INFO("GPU not posted. posting now...\n"); 1183 atom_asic_init(rdev->mode_info.atom_context); 1184 } 1185 /* Initialize scratch registers */ 1186 r600_scratch_init(rdev); 1187 /* Initialize surface registers */ 1188 radeon_surface_init(rdev); 1189 /* Initialize clocks */ 1190 radeon_get_clock_info(rdev->ddev); 1191 /* Fence driver */ 1192 r = radeon_fence_driver_init(rdev); 1193 if (r) 1194 return r; 1195 /* initialize AGP */ 1196 if (rdev->flags & RADEON_IS_AGP) { 1197 r = radeon_agp_init(rdev); 1198 if (r) 1199 radeon_agp_disable(rdev); 1200 } 1201 r = rv770_mc_init(rdev); 1202 if (r) 1203 return r; 1204 /* Memory manager */ 1205 r = radeon_bo_init(rdev); 1206 if (r) 1207 return r; 1208 1209 r = radeon_irq_kms_init(rdev); 1210 if (r) 1211 return r; 1212 1213 rdev->cp.ring_obj = NULL; 1214 r600_ring_init(rdev, 1024 * 1024); 1215 1216 rdev->ih.ring_obj = NULL; 1217 r600_ih_ring_init(rdev, 64 * 1024); 1218 1219 r = r600_pcie_gart_init(rdev); 1220 if (r) 1221 return r; 1222 1223 rdev->accel_working = true; 1224 r = rv770_startup(rdev); 1225 if (r) { 1226 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1227 r700_cp_fini(rdev); 1228 r600_irq_fini(rdev); 1229 radeon_wb_fini(rdev); 1230 radeon_irq_kms_fini(rdev); 1231 rv770_pcie_gart_fini(rdev); 1232 rdev->accel_working = false; 1233 } 1234 if (rdev->accel_working) { 1235 r = radeon_ib_pool_init(rdev); 1236 if (r) { 1237 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1238 rdev->accel_working = false; 1239 } else { 1240 r = r600_ib_test(rdev); 1241 if (r) { 1242 dev_err(rdev->dev, "IB test failed (%d).\n", r); 1243 rdev->accel_working = false; 1244 } 1245 } 1246 } 1247 1248 r = r600_audio_init(rdev); 1249 if (r) { 1250 dev_err(rdev->dev, "radeon: audio init failed\n"); 1251 return r; 1252 } 1253 1254 return 0; 1255 } 1256 1257 void rv770_fini(struct radeon_device *rdev) 1258 { 1259 r600_blit_fini(rdev); 1260 r700_cp_fini(rdev); 1261 r600_irq_fini(rdev); 1262 radeon_wb_fini(rdev); 1263 radeon_ib_pool_fini(rdev); 1264 radeon_irq_kms_fini(rdev); 1265 rv770_pcie_gart_fini(rdev); 1266 r600_vram_scratch_fini(rdev); 1267 radeon_gem_fini(rdev); 1268 radeon_fence_driver_fini(rdev); 1269 radeon_agp_fini(rdev); 1270 radeon_bo_fini(rdev); 1271 radeon_atombios_fini(rdev); 1272 kfree(rdev->bios); 1273 rdev->bios = NULL; 1274 } 1275 1276 static void rv770_pcie_gen2_enable(struct radeon_device *rdev) 1277 { 1278 u32 link_width_cntl, lanes, speed_cntl, tmp; 1279 u16 link_cntl2; 1280 1281 if (radeon_pcie_gen2 == 0) 1282 return; 1283 1284 if (rdev->flags & RADEON_IS_IGP) 1285 return; 1286 1287 if (!(rdev->flags & RADEON_IS_PCIE)) 1288 return; 1289 1290 /* x2 cards have a special sequence */ 1291 if (ASIC_IS_X2(rdev)) 1292 return; 1293 1294 /* advertise upconfig capability */ 1295 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1296 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1297 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1298 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1299 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 1300 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 1301 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 1302 LC_RECONFIG_ARC_MISSING_ESCAPE); 1303 link_width_cntl |= lanes | LC_RECONFIG_NOW | 1304 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; 1305 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1306 } else { 1307 link_width_cntl |= LC_UPCONFIGURE_DIS; 1308 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1309 } 1310 1311 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1312 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 1313 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 1314 1315 tmp = RREG32(0x541c); 1316 WREG32(0x541c, tmp | 0x8); 1317 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 1318 link_cntl2 = RREG16(0x4088); 1319 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 1320 link_cntl2 |= 0x2; 1321 WREG16(0x4088, link_cntl2); 1322 WREG32(MM_CFGREGS_CNTL, 0); 1323 1324 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1325 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 1326 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1327 1328 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1329 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 1330 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1331 1332 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1333 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 1334 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1335 1336 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 1337 speed_cntl |= LC_GEN2_EN_STRAP; 1338 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 1339 1340 } else { 1341 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 1342 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 1343 if (1) 1344 link_width_cntl |= LC_UPCONFIGURE_DIS; 1345 else 1346 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 1347 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1348 } 1349 } 1350