1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 #include "drmP.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "radeon_drm.h" 35 #include "rv770d.h" 36 #include "atom.h" 37 #include "avivod.h" 38 39 #define R700_PFP_UCODE_SIZE 848 40 #define R700_PM4_UCODE_SIZE 1360 41 42 static void rv770_gpu_init(struct radeon_device *rdev); 43 void rv770_fini(struct radeon_device *rdev); 44 45 void rv770_pm_misc(struct radeon_device *rdev) 46 { 47 int req_ps_idx = rdev->pm.requested_power_state_index; 48 int req_cm_idx = rdev->pm.requested_clock_mode_index; 49 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 50 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 51 52 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 53 if (voltage->voltage != rdev->pm.current_vddc) { 54 radeon_atom_set_voltage(rdev, voltage->voltage); 55 rdev->pm.current_vddc = voltage->voltage; 56 DRM_DEBUG("Setting: v: %d\n", voltage->voltage); 57 } 58 } 59 } 60 61 /* 62 * GART 63 */ 64 int rv770_pcie_gart_enable(struct radeon_device *rdev) 65 { 66 u32 tmp; 67 int r, i; 68 69 if (rdev->gart.table.vram.robj == NULL) { 70 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 71 return -EINVAL; 72 } 73 r = radeon_gart_table_vram_pin(rdev); 74 if (r) 75 return r; 76 radeon_gart_restore(rdev); 77 /* Setup L2 cache */ 78 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 79 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 80 EFFECTIVE_L2_QUEUE_SIZE(7)); 81 WREG32(VM_L2_CNTL2, 0); 82 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 83 /* Setup TLB control */ 84 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 85 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 86 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 87 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 88 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 89 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 90 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 91 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 92 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 93 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 94 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 95 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 96 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 97 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 98 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 99 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 100 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 101 (u32)(rdev->dummy_page.addr >> 12)); 102 for (i = 1; i < 7; i++) 103 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 104 105 r600_pcie_gart_tlb_flush(rdev); 106 rdev->gart.ready = true; 107 return 0; 108 } 109 110 void rv770_pcie_gart_disable(struct radeon_device *rdev) 111 { 112 u32 tmp; 113 int i, r; 114 115 /* Disable all tables */ 116 for (i = 0; i < 7; i++) 117 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 118 119 /* Setup L2 cache */ 120 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 121 EFFECTIVE_L2_QUEUE_SIZE(7)); 122 WREG32(VM_L2_CNTL2, 0); 123 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 124 /* Setup TLB control */ 125 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 126 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 127 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 128 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 129 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 130 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 131 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 132 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 133 if (rdev->gart.table.vram.robj) { 134 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 135 if (likely(r == 0)) { 136 radeon_bo_kunmap(rdev->gart.table.vram.robj); 137 radeon_bo_unpin(rdev->gart.table.vram.robj); 138 radeon_bo_unreserve(rdev->gart.table.vram.robj); 139 } 140 } 141 } 142 143 void rv770_pcie_gart_fini(struct radeon_device *rdev) 144 { 145 radeon_gart_fini(rdev); 146 rv770_pcie_gart_disable(rdev); 147 radeon_gart_table_vram_free(rdev); 148 } 149 150 151 void rv770_agp_enable(struct radeon_device *rdev) 152 { 153 u32 tmp; 154 int i; 155 156 /* Setup L2 cache */ 157 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 158 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 159 EFFECTIVE_L2_QUEUE_SIZE(7)); 160 WREG32(VM_L2_CNTL2, 0); 161 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 162 /* Setup TLB control */ 163 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 164 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 165 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 166 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 167 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 168 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 169 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 170 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 171 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 172 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 173 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 174 for (i = 0; i < 7; i++) 175 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 176 } 177 178 static void rv770_mc_program(struct radeon_device *rdev) 179 { 180 struct rv515_mc_save save; 181 u32 tmp; 182 int i, j; 183 184 /* Initialize HDP */ 185 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 186 WREG32((0x2c14 + j), 0x00000000); 187 WREG32((0x2c18 + j), 0x00000000); 188 WREG32((0x2c1c + j), 0x00000000); 189 WREG32((0x2c20 + j), 0x00000000); 190 WREG32((0x2c24 + j), 0x00000000); 191 } 192 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 193 194 rv515_mc_stop(rdev, &save); 195 if (r600_mc_wait_for_idle(rdev)) { 196 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 197 } 198 /* Lockout access through VGA aperture*/ 199 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 200 /* Update configuration */ 201 if (rdev->flags & RADEON_IS_AGP) { 202 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 203 /* VRAM before AGP */ 204 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 205 rdev->mc.vram_start >> 12); 206 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 207 rdev->mc.gtt_end >> 12); 208 } else { 209 /* VRAM after AGP */ 210 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 211 rdev->mc.gtt_start >> 12); 212 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 213 rdev->mc.vram_end >> 12); 214 } 215 } else { 216 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 217 rdev->mc.vram_start >> 12); 218 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 219 rdev->mc.vram_end >> 12); 220 } 221 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 222 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 223 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 224 WREG32(MC_VM_FB_LOCATION, tmp); 225 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 226 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 227 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); 228 if (rdev->flags & RADEON_IS_AGP) { 229 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 230 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 231 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 232 } else { 233 WREG32(MC_VM_AGP_BASE, 0); 234 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 235 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 236 } 237 if (r600_mc_wait_for_idle(rdev)) { 238 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 239 } 240 rv515_mc_resume(rdev, &save); 241 /* we need to own VRAM, so turn off the VGA renderer here 242 * to stop it overwriting our objects */ 243 rv515_vga_render_disable(rdev); 244 } 245 246 247 /* 248 * CP. 249 */ 250 void r700_cp_stop(struct radeon_device *rdev) 251 { 252 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 253 } 254 255 static int rv770_cp_load_microcode(struct radeon_device *rdev) 256 { 257 const __be32 *fw_data; 258 int i; 259 260 if (!rdev->me_fw || !rdev->pfp_fw) 261 return -EINVAL; 262 263 r700_cp_stop(rdev); 264 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 265 266 /* Reset cp */ 267 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 268 RREG32(GRBM_SOFT_RESET); 269 mdelay(15); 270 WREG32(GRBM_SOFT_RESET, 0); 271 272 fw_data = (const __be32 *)rdev->pfp_fw->data; 273 WREG32(CP_PFP_UCODE_ADDR, 0); 274 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 275 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 276 WREG32(CP_PFP_UCODE_ADDR, 0); 277 278 fw_data = (const __be32 *)rdev->me_fw->data; 279 WREG32(CP_ME_RAM_WADDR, 0); 280 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 281 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 282 283 WREG32(CP_PFP_UCODE_ADDR, 0); 284 WREG32(CP_ME_RAM_WADDR, 0); 285 WREG32(CP_ME_RAM_RADDR, 0); 286 return 0; 287 } 288 289 void r700_cp_fini(struct radeon_device *rdev) 290 { 291 r700_cp_stop(rdev); 292 radeon_ring_fini(rdev); 293 } 294 295 /* 296 * Core functions 297 */ 298 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 299 u32 num_tile_pipes, 300 u32 num_backends, 301 u32 backend_disable_mask) 302 { 303 u32 backend_map = 0; 304 u32 enabled_backends_mask; 305 u32 enabled_backends_count; 306 u32 cur_pipe; 307 u32 swizzle_pipe[R7XX_MAX_PIPES]; 308 u32 cur_backend; 309 u32 i; 310 bool force_no_swizzle; 311 312 if (num_tile_pipes > R7XX_MAX_PIPES) 313 num_tile_pipes = R7XX_MAX_PIPES; 314 if (num_tile_pipes < 1) 315 num_tile_pipes = 1; 316 if (num_backends > R7XX_MAX_BACKENDS) 317 num_backends = R7XX_MAX_BACKENDS; 318 if (num_backends < 1) 319 num_backends = 1; 320 321 enabled_backends_mask = 0; 322 enabled_backends_count = 0; 323 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 324 if (((backend_disable_mask >> i) & 1) == 0) { 325 enabled_backends_mask |= (1 << i); 326 ++enabled_backends_count; 327 } 328 if (enabled_backends_count == num_backends) 329 break; 330 } 331 332 if (enabled_backends_count == 0) { 333 enabled_backends_mask = 1; 334 enabled_backends_count = 1; 335 } 336 337 if (enabled_backends_count != num_backends) 338 num_backends = enabled_backends_count; 339 340 switch (rdev->family) { 341 case CHIP_RV770: 342 case CHIP_RV730: 343 force_no_swizzle = false; 344 break; 345 case CHIP_RV710: 346 case CHIP_RV740: 347 default: 348 force_no_swizzle = true; 349 break; 350 } 351 352 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 353 switch (num_tile_pipes) { 354 case 1: 355 swizzle_pipe[0] = 0; 356 break; 357 case 2: 358 swizzle_pipe[0] = 0; 359 swizzle_pipe[1] = 1; 360 break; 361 case 3: 362 if (force_no_swizzle) { 363 swizzle_pipe[0] = 0; 364 swizzle_pipe[1] = 1; 365 swizzle_pipe[2] = 2; 366 } else { 367 swizzle_pipe[0] = 0; 368 swizzle_pipe[1] = 2; 369 swizzle_pipe[2] = 1; 370 } 371 break; 372 case 4: 373 if (force_no_swizzle) { 374 swizzle_pipe[0] = 0; 375 swizzle_pipe[1] = 1; 376 swizzle_pipe[2] = 2; 377 swizzle_pipe[3] = 3; 378 } else { 379 swizzle_pipe[0] = 0; 380 swizzle_pipe[1] = 2; 381 swizzle_pipe[2] = 3; 382 swizzle_pipe[3] = 1; 383 } 384 break; 385 case 5: 386 if (force_no_swizzle) { 387 swizzle_pipe[0] = 0; 388 swizzle_pipe[1] = 1; 389 swizzle_pipe[2] = 2; 390 swizzle_pipe[3] = 3; 391 swizzle_pipe[4] = 4; 392 } else { 393 swizzle_pipe[0] = 0; 394 swizzle_pipe[1] = 2; 395 swizzle_pipe[2] = 4; 396 swizzle_pipe[3] = 1; 397 swizzle_pipe[4] = 3; 398 } 399 break; 400 case 6: 401 if (force_no_swizzle) { 402 swizzle_pipe[0] = 0; 403 swizzle_pipe[1] = 1; 404 swizzle_pipe[2] = 2; 405 swizzle_pipe[3] = 3; 406 swizzle_pipe[4] = 4; 407 swizzle_pipe[5] = 5; 408 } else { 409 swizzle_pipe[0] = 0; 410 swizzle_pipe[1] = 2; 411 swizzle_pipe[2] = 4; 412 swizzle_pipe[3] = 5; 413 swizzle_pipe[4] = 3; 414 swizzle_pipe[5] = 1; 415 } 416 break; 417 case 7: 418 if (force_no_swizzle) { 419 swizzle_pipe[0] = 0; 420 swizzle_pipe[1] = 1; 421 swizzle_pipe[2] = 2; 422 swizzle_pipe[3] = 3; 423 swizzle_pipe[4] = 4; 424 swizzle_pipe[5] = 5; 425 swizzle_pipe[6] = 6; 426 } else { 427 swizzle_pipe[0] = 0; 428 swizzle_pipe[1] = 2; 429 swizzle_pipe[2] = 4; 430 swizzle_pipe[3] = 6; 431 swizzle_pipe[4] = 3; 432 swizzle_pipe[5] = 1; 433 swizzle_pipe[6] = 5; 434 } 435 break; 436 case 8: 437 if (force_no_swizzle) { 438 swizzle_pipe[0] = 0; 439 swizzle_pipe[1] = 1; 440 swizzle_pipe[2] = 2; 441 swizzle_pipe[3] = 3; 442 swizzle_pipe[4] = 4; 443 swizzle_pipe[5] = 5; 444 swizzle_pipe[6] = 6; 445 swizzle_pipe[7] = 7; 446 } else { 447 swizzle_pipe[0] = 0; 448 swizzle_pipe[1] = 2; 449 swizzle_pipe[2] = 4; 450 swizzle_pipe[3] = 6; 451 swizzle_pipe[4] = 3; 452 swizzle_pipe[5] = 1; 453 swizzle_pipe[6] = 7; 454 swizzle_pipe[7] = 5; 455 } 456 break; 457 } 458 459 cur_backend = 0; 460 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 461 while (((1 << cur_backend) & enabled_backends_mask) == 0) 462 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 463 464 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 465 466 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 467 } 468 469 return backend_map; 470 } 471 472 static void rv770_gpu_init(struct radeon_device *rdev) 473 { 474 int i, j, num_qd_pipes; 475 u32 ta_aux_cntl; 476 u32 sx_debug_1; 477 u32 smx_dc_ctl0; 478 u32 db_debug3; 479 u32 num_gs_verts_per_thread; 480 u32 vgt_gs_per_es; 481 u32 gs_prim_buffer_depth = 0; 482 u32 sq_ms_fifo_sizes; 483 u32 sq_config; 484 u32 sq_thread_resource_mgmt; 485 u32 hdp_host_path_cntl; 486 u32 sq_dyn_gpr_size_simd_ab_0; 487 u32 backend_map; 488 u32 gb_tiling_config = 0; 489 u32 cc_rb_backend_disable = 0; 490 u32 cc_gc_shader_pipe_config = 0; 491 u32 mc_arb_ramcfg; 492 u32 db_debug4; 493 494 /* setup chip specs */ 495 switch (rdev->family) { 496 case CHIP_RV770: 497 rdev->config.rv770.max_pipes = 4; 498 rdev->config.rv770.max_tile_pipes = 8; 499 rdev->config.rv770.max_simds = 10; 500 rdev->config.rv770.max_backends = 4; 501 rdev->config.rv770.max_gprs = 256; 502 rdev->config.rv770.max_threads = 248; 503 rdev->config.rv770.max_stack_entries = 512; 504 rdev->config.rv770.max_hw_contexts = 8; 505 rdev->config.rv770.max_gs_threads = 16 * 2; 506 rdev->config.rv770.sx_max_export_size = 128; 507 rdev->config.rv770.sx_max_export_pos_size = 16; 508 rdev->config.rv770.sx_max_export_smx_size = 112; 509 rdev->config.rv770.sq_num_cf_insts = 2; 510 511 rdev->config.rv770.sx_num_of_sets = 7; 512 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 513 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 514 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 515 break; 516 case CHIP_RV730: 517 rdev->config.rv770.max_pipes = 2; 518 rdev->config.rv770.max_tile_pipes = 4; 519 rdev->config.rv770.max_simds = 8; 520 rdev->config.rv770.max_backends = 2; 521 rdev->config.rv770.max_gprs = 128; 522 rdev->config.rv770.max_threads = 248; 523 rdev->config.rv770.max_stack_entries = 256; 524 rdev->config.rv770.max_hw_contexts = 8; 525 rdev->config.rv770.max_gs_threads = 16 * 2; 526 rdev->config.rv770.sx_max_export_size = 256; 527 rdev->config.rv770.sx_max_export_pos_size = 32; 528 rdev->config.rv770.sx_max_export_smx_size = 224; 529 rdev->config.rv770.sq_num_cf_insts = 2; 530 531 rdev->config.rv770.sx_num_of_sets = 7; 532 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 533 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 534 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 535 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 536 rdev->config.rv770.sx_max_export_pos_size -= 16; 537 rdev->config.rv770.sx_max_export_smx_size += 16; 538 } 539 break; 540 case CHIP_RV710: 541 rdev->config.rv770.max_pipes = 2; 542 rdev->config.rv770.max_tile_pipes = 2; 543 rdev->config.rv770.max_simds = 2; 544 rdev->config.rv770.max_backends = 1; 545 rdev->config.rv770.max_gprs = 256; 546 rdev->config.rv770.max_threads = 192; 547 rdev->config.rv770.max_stack_entries = 256; 548 rdev->config.rv770.max_hw_contexts = 4; 549 rdev->config.rv770.max_gs_threads = 8 * 2; 550 rdev->config.rv770.sx_max_export_size = 128; 551 rdev->config.rv770.sx_max_export_pos_size = 16; 552 rdev->config.rv770.sx_max_export_smx_size = 112; 553 rdev->config.rv770.sq_num_cf_insts = 1; 554 555 rdev->config.rv770.sx_num_of_sets = 7; 556 rdev->config.rv770.sc_prim_fifo_size = 0x40; 557 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 558 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 559 break; 560 case CHIP_RV740: 561 rdev->config.rv770.max_pipes = 4; 562 rdev->config.rv770.max_tile_pipes = 4; 563 rdev->config.rv770.max_simds = 8; 564 rdev->config.rv770.max_backends = 4; 565 rdev->config.rv770.max_gprs = 256; 566 rdev->config.rv770.max_threads = 248; 567 rdev->config.rv770.max_stack_entries = 512; 568 rdev->config.rv770.max_hw_contexts = 8; 569 rdev->config.rv770.max_gs_threads = 16 * 2; 570 rdev->config.rv770.sx_max_export_size = 256; 571 rdev->config.rv770.sx_max_export_pos_size = 32; 572 rdev->config.rv770.sx_max_export_smx_size = 224; 573 rdev->config.rv770.sq_num_cf_insts = 2; 574 575 rdev->config.rv770.sx_num_of_sets = 7; 576 rdev->config.rv770.sc_prim_fifo_size = 0x100; 577 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 578 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 579 580 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 581 rdev->config.rv770.sx_max_export_pos_size -= 16; 582 rdev->config.rv770.sx_max_export_smx_size += 16; 583 } 584 break; 585 default: 586 break; 587 } 588 589 /* Initialize HDP */ 590 j = 0; 591 for (i = 0; i < 32; i++) { 592 WREG32((0x2c14 + j), 0x00000000); 593 WREG32((0x2c18 + j), 0x00000000); 594 WREG32((0x2c1c + j), 0x00000000); 595 WREG32((0x2c20 + j), 0x00000000); 596 WREG32((0x2c24 + j), 0x00000000); 597 j += 0x18; 598 } 599 600 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 601 602 /* setup tiling, simd, pipe config */ 603 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 604 605 switch (rdev->config.rv770.max_tile_pipes) { 606 case 1: 607 default: 608 gb_tiling_config |= PIPE_TILING(0); 609 break; 610 case 2: 611 gb_tiling_config |= PIPE_TILING(1); 612 break; 613 case 4: 614 gb_tiling_config |= PIPE_TILING(2); 615 break; 616 case 8: 617 gb_tiling_config |= PIPE_TILING(3); 618 break; 619 } 620 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; 621 622 if (rdev->family == CHIP_RV770) 623 gb_tiling_config |= BANK_TILING(1); 624 else 625 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 626 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); 627 628 gb_tiling_config |= GROUP_SIZE(0); 629 rdev->config.rv770.tiling_group_size = 256; 630 631 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { 632 gb_tiling_config |= ROW_TILING(3); 633 gb_tiling_config |= SAMPLE_SPLIT(3); 634 } else { 635 gb_tiling_config |= 636 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 637 gb_tiling_config |= 638 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 639 } 640 641 gb_tiling_config |= BANK_SWAPS(1); 642 643 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 644 cc_rb_backend_disable |= 645 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 646 647 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 648 cc_gc_shader_pipe_config |= 649 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 650 cc_gc_shader_pipe_config |= 651 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 652 653 if (rdev->family == CHIP_RV740) 654 backend_map = 0x28; 655 else 656 backend_map = r700_get_tile_pipe_to_backend_map(rdev, 657 rdev->config.rv770.max_tile_pipes, 658 (R7XX_MAX_BACKENDS - 659 r600_count_pipe_bits((cc_rb_backend_disable & 660 R7XX_MAX_BACKENDS_MASK) >> 16)), 661 (cc_rb_backend_disable >> 16)); 662 gb_tiling_config |= BACKEND_MAP(backend_map); 663 664 665 WREG32(GB_TILING_CONFIG, gb_tiling_config); 666 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 667 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 668 669 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 670 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 671 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 672 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 673 674 WREG32(CGTS_SYS_TCC_DISABLE, 0); 675 WREG32(CGTS_TCC_DISABLE, 0); 676 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 677 WREG32(CGTS_USER_TCC_DISABLE, 0); 678 679 num_qd_pipes = 680 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 681 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 682 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 683 684 /* set HW defaults for 3D engine */ 685 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 686 ROQ_IB2_START(0x2b))); 687 688 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 689 690 ta_aux_cntl = RREG32(TA_CNTL_AUX); 691 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO); 692 693 sx_debug_1 = RREG32(SX_DEBUG_1); 694 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 695 WREG32(SX_DEBUG_1, sx_debug_1); 696 697 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 698 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 699 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 700 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 701 702 if (rdev->family != CHIP_RV740) 703 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 704 GS_FLUSH_CTL(4) | 705 ACK_FLUSH_CTL(3) | 706 SYNC_FLUSH_CTL)); 707 708 db_debug3 = RREG32(DB_DEBUG3); 709 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 710 switch (rdev->family) { 711 case CHIP_RV770: 712 case CHIP_RV740: 713 db_debug3 |= DB_CLK_OFF_DELAY(0x1f); 714 break; 715 case CHIP_RV710: 716 case CHIP_RV730: 717 default: 718 db_debug3 |= DB_CLK_OFF_DELAY(2); 719 break; 720 } 721 WREG32(DB_DEBUG3, db_debug3); 722 723 if (rdev->family != CHIP_RV770) { 724 db_debug4 = RREG32(DB_DEBUG4); 725 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 726 WREG32(DB_DEBUG4, db_debug4); 727 } 728 729 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 730 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 731 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 732 733 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 734 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 735 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 736 737 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 738 739 WREG32(VGT_NUM_INSTANCES, 1); 740 741 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 742 743 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 744 745 WREG32(CP_PERFMON_CNTL, 0); 746 747 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 748 DONE_FIFO_HIWATER(0xe0) | 749 ALU_UPDATE_FIFO_HIWATER(0x8)); 750 switch (rdev->family) { 751 case CHIP_RV770: 752 case CHIP_RV730: 753 case CHIP_RV710: 754 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 755 break; 756 case CHIP_RV740: 757 default: 758 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 759 break; 760 } 761 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 762 763 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 764 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 765 */ 766 sq_config = RREG32(SQ_CONFIG); 767 sq_config &= ~(PS_PRIO(3) | 768 VS_PRIO(3) | 769 GS_PRIO(3) | 770 ES_PRIO(3)); 771 sq_config |= (DX9_CONSTS | 772 VC_ENABLE | 773 EXPORT_SRC_C | 774 PS_PRIO(0) | 775 VS_PRIO(1) | 776 GS_PRIO(2) | 777 ES_PRIO(3)); 778 if (rdev->family == CHIP_RV710) 779 /* no vertex cache */ 780 sq_config &= ~VC_ENABLE; 781 782 WREG32(SQ_CONFIG, sq_config); 783 784 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 785 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 786 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 787 788 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 789 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 790 791 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 792 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 793 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 794 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 795 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 796 else 797 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 798 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 799 800 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 801 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 802 803 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 804 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 805 806 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 807 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 808 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 809 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 810 811 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 812 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 813 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 814 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 815 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 816 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 817 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 818 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 819 820 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 821 FORCE_EOV_MAX_REZ_CNT(255))); 822 823 if (rdev->family == CHIP_RV710) 824 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 825 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 826 else 827 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 828 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 829 830 switch (rdev->family) { 831 case CHIP_RV770: 832 case CHIP_RV730: 833 case CHIP_RV740: 834 gs_prim_buffer_depth = 384; 835 break; 836 case CHIP_RV710: 837 gs_prim_buffer_depth = 128; 838 break; 839 default: 840 break; 841 } 842 843 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 844 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 845 /* Max value for this is 256 */ 846 if (vgt_gs_per_es > 256) 847 vgt_gs_per_es = 256; 848 849 WREG32(VGT_ES_PER_GS, 128); 850 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 851 WREG32(VGT_GS_PER_VS, 2); 852 853 /* more default values. 2D/3D driver should adjust as needed */ 854 WREG32(VGT_GS_VERTEX_REUSE, 16); 855 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 856 WREG32(VGT_STRMOUT_EN, 0); 857 WREG32(SX_MISC, 0); 858 WREG32(PA_SC_MODE_CNTL, 0); 859 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 860 WREG32(PA_SC_AA_CONFIG, 0); 861 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 862 WREG32(PA_SC_LINE_STIPPLE, 0); 863 WREG32(SPI_INPUT_Z, 0); 864 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 865 WREG32(CB_COLOR7_FRAG, 0); 866 867 /* clear render buffer base addresses */ 868 WREG32(CB_COLOR0_BASE, 0); 869 WREG32(CB_COLOR1_BASE, 0); 870 WREG32(CB_COLOR2_BASE, 0); 871 WREG32(CB_COLOR3_BASE, 0); 872 WREG32(CB_COLOR4_BASE, 0); 873 WREG32(CB_COLOR5_BASE, 0); 874 WREG32(CB_COLOR6_BASE, 0); 875 WREG32(CB_COLOR7_BASE, 0); 876 877 WREG32(TCP_CNTL, 0); 878 879 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 880 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 881 882 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 883 884 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 885 NUM_CLIP_SEQ(3))); 886 887 } 888 889 int rv770_mc_init(struct radeon_device *rdev) 890 { 891 u32 tmp; 892 int chansize, numchan; 893 894 /* Get VRAM informations */ 895 rdev->mc.vram_is_ddr = true; 896 tmp = RREG32(MC_ARB_RAMCFG); 897 if (tmp & CHANSIZE_OVERRIDE) { 898 chansize = 16; 899 } else if (tmp & CHANSIZE_MASK) { 900 chansize = 64; 901 } else { 902 chansize = 32; 903 } 904 tmp = RREG32(MC_SHARED_CHMAP); 905 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 906 case 0: 907 default: 908 numchan = 1; 909 break; 910 case 1: 911 numchan = 2; 912 break; 913 case 2: 914 numchan = 4; 915 break; 916 case 3: 917 numchan = 8; 918 break; 919 } 920 rdev->mc.vram_width = numchan * chansize; 921 /* Could aper size report 0 ? */ 922 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 923 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 924 /* Setup GPU memory space */ 925 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 926 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 927 rdev->mc.visible_vram_size = rdev->mc.aper_size; 928 r600_vram_gtt_location(rdev, &rdev->mc); 929 radeon_update_bandwidth_info(rdev); 930 931 return 0; 932 } 933 934 static int rv770_startup(struct radeon_device *rdev) 935 { 936 int r; 937 938 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 939 r = r600_init_microcode(rdev); 940 if (r) { 941 DRM_ERROR("Failed to load firmware!\n"); 942 return r; 943 } 944 } 945 946 rv770_mc_program(rdev); 947 if (rdev->flags & RADEON_IS_AGP) { 948 rv770_agp_enable(rdev); 949 } else { 950 r = rv770_pcie_gart_enable(rdev); 951 if (r) 952 return r; 953 } 954 rv770_gpu_init(rdev); 955 r = r600_blit_init(rdev); 956 if (r) { 957 r600_blit_fini(rdev); 958 rdev->asic->copy = NULL; 959 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 960 } 961 /* pin copy shader into vram */ 962 if (rdev->r600_blit.shader_obj) { 963 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 964 if (unlikely(r != 0)) 965 return r; 966 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 967 &rdev->r600_blit.shader_gpu_addr); 968 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 969 if (r) { 970 DRM_ERROR("failed to pin blit object %d\n", r); 971 return r; 972 } 973 } 974 /* Enable IRQ */ 975 r = r600_irq_init(rdev); 976 if (r) { 977 DRM_ERROR("radeon: IH init failed (%d).\n", r); 978 radeon_irq_kms_fini(rdev); 979 return r; 980 } 981 r600_irq_set(rdev); 982 983 r = radeon_ring_init(rdev, rdev->cp.ring_size); 984 if (r) 985 return r; 986 r = rv770_cp_load_microcode(rdev); 987 if (r) 988 return r; 989 r = r600_cp_resume(rdev); 990 if (r) 991 return r; 992 /* write back buffer are not vital so don't worry about failure */ 993 r600_wb_enable(rdev); 994 return 0; 995 } 996 997 int rv770_resume(struct radeon_device *rdev) 998 { 999 int r; 1000 1001 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 1002 * posting will perform necessary task to bring back GPU into good 1003 * shape. 1004 */ 1005 /* post card */ 1006 atom_asic_init(rdev->mode_info.atom_context); 1007 /* Initialize clocks */ 1008 r = radeon_clocks_init(rdev); 1009 if (r) { 1010 return r; 1011 } 1012 1013 r = rv770_startup(rdev); 1014 if (r) { 1015 DRM_ERROR("r600 startup failed on resume\n"); 1016 return r; 1017 } 1018 1019 r = r600_ib_test(rdev); 1020 if (r) { 1021 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1022 return r; 1023 } 1024 1025 r = r600_audio_init(rdev); 1026 if (r) { 1027 dev_err(rdev->dev, "radeon: audio init failed\n"); 1028 return r; 1029 } 1030 1031 return r; 1032 1033 } 1034 1035 int rv770_suspend(struct radeon_device *rdev) 1036 { 1037 int r; 1038 1039 r600_audio_fini(rdev); 1040 /* FIXME: we should wait for ring to be empty */ 1041 r700_cp_stop(rdev); 1042 rdev->cp.ready = false; 1043 r600_irq_suspend(rdev); 1044 r600_wb_disable(rdev); 1045 rv770_pcie_gart_disable(rdev); 1046 /* unpin shaders bo */ 1047 if (rdev->r600_blit.shader_obj) { 1048 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1049 if (likely(r == 0)) { 1050 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1051 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1052 } 1053 } 1054 return 0; 1055 } 1056 1057 /* Plan is to move initialization in that function and use 1058 * helper function so that radeon_device_init pretty much 1059 * do nothing more than calling asic specific function. This 1060 * should also allow to remove a bunch of callback function 1061 * like vram_info. 1062 */ 1063 int rv770_init(struct radeon_device *rdev) 1064 { 1065 int r; 1066 1067 r = radeon_dummy_page_init(rdev); 1068 if (r) 1069 return r; 1070 /* This don't do much */ 1071 r = radeon_gem_init(rdev); 1072 if (r) 1073 return r; 1074 /* Read BIOS */ 1075 if (!radeon_get_bios(rdev)) { 1076 if (ASIC_IS_AVIVO(rdev)) 1077 return -EINVAL; 1078 } 1079 /* Must be an ATOMBIOS */ 1080 if (!rdev->is_atom_bios) { 1081 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 1082 return -EINVAL; 1083 } 1084 r = radeon_atombios_init(rdev); 1085 if (r) 1086 return r; 1087 /* Post card if necessary */ 1088 if (!r600_card_posted(rdev)) { 1089 if (!rdev->bios) { 1090 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 1091 return -EINVAL; 1092 } 1093 DRM_INFO("GPU not posted. posting now...\n"); 1094 atom_asic_init(rdev->mode_info.atom_context); 1095 } 1096 /* Initialize scratch registers */ 1097 r600_scratch_init(rdev); 1098 /* Initialize surface registers */ 1099 radeon_surface_init(rdev); 1100 /* Initialize clocks */ 1101 radeon_get_clock_info(rdev->ddev); 1102 r = radeon_clocks_init(rdev); 1103 if (r) 1104 return r; 1105 /* Fence driver */ 1106 r = radeon_fence_driver_init(rdev); 1107 if (r) 1108 return r; 1109 /* initialize AGP */ 1110 if (rdev->flags & RADEON_IS_AGP) { 1111 r = radeon_agp_init(rdev); 1112 if (r) 1113 radeon_agp_disable(rdev); 1114 } 1115 r = rv770_mc_init(rdev); 1116 if (r) 1117 return r; 1118 /* Memory manager */ 1119 r = radeon_bo_init(rdev); 1120 if (r) 1121 return r; 1122 1123 r = radeon_irq_kms_init(rdev); 1124 if (r) 1125 return r; 1126 1127 rdev->cp.ring_obj = NULL; 1128 r600_ring_init(rdev, 1024 * 1024); 1129 1130 rdev->ih.ring_obj = NULL; 1131 r600_ih_ring_init(rdev, 64 * 1024); 1132 1133 r = r600_pcie_gart_init(rdev); 1134 if (r) 1135 return r; 1136 1137 rdev->accel_working = true; 1138 r = rv770_startup(rdev); 1139 if (r) { 1140 dev_err(rdev->dev, "disabling GPU acceleration\n"); 1141 r700_cp_fini(rdev); 1142 r600_wb_fini(rdev); 1143 r600_irq_fini(rdev); 1144 radeon_irq_kms_fini(rdev); 1145 rv770_pcie_gart_fini(rdev); 1146 rdev->accel_working = false; 1147 } 1148 if (rdev->accel_working) { 1149 r = radeon_ib_pool_init(rdev); 1150 if (r) { 1151 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1152 rdev->accel_working = false; 1153 } else { 1154 r = r600_ib_test(rdev); 1155 if (r) { 1156 dev_err(rdev->dev, "IB test failed (%d).\n", r); 1157 rdev->accel_working = false; 1158 } 1159 } 1160 } 1161 1162 r = r600_audio_init(rdev); 1163 if (r) { 1164 dev_err(rdev->dev, "radeon: audio init failed\n"); 1165 return r; 1166 } 1167 1168 return 0; 1169 } 1170 1171 void rv770_fini(struct radeon_device *rdev) 1172 { 1173 r600_blit_fini(rdev); 1174 r700_cp_fini(rdev); 1175 r600_wb_fini(rdev); 1176 r600_irq_fini(rdev); 1177 radeon_irq_kms_fini(rdev); 1178 rv770_pcie_gart_fini(rdev); 1179 radeon_gem_fini(rdev); 1180 radeon_fence_driver_fini(rdev); 1181 radeon_clocks_fini(rdev); 1182 radeon_agp_fini(rdev); 1183 radeon_bo_fini(rdev); 1184 radeon_atombios_fini(rdev); 1185 kfree(rdev->bios); 1186 rdev->bios = NULL; 1187 radeon_dummy_page_fini(rdev); 1188 } 1189