1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/firmware.h> 29 #include <linux/platform_device.h> 30 #include "drmP.h" 31 #include "radeon.h" 32 #include "radeon_drm.h" 33 #include "rv770d.h" 34 #include "avivod.h" 35 #include "atom.h" 36 37 #define R700_PFP_UCODE_SIZE 848 38 #define R700_PM4_UCODE_SIZE 1360 39 40 static void rv770_gpu_init(struct radeon_device *rdev); 41 void rv770_fini(struct radeon_device *rdev); 42 43 44 /* 45 * GART 46 */ 47 int rv770_pcie_gart_enable(struct radeon_device *rdev) 48 { 49 u32 tmp; 50 int r, i; 51 52 if (rdev->gart.table.vram.robj == NULL) { 53 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 54 return -EINVAL; 55 } 56 r = radeon_gart_table_vram_pin(rdev); 57 if (r) 58 return r; 59 /* Setup L2 cache */ 60 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 61 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 62 EFFECTIVE_L2_QUEUE_SIZE(7)); 63 WREG32(VM_L2_CNTL2, 0); 64 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 65 /* Setup TLB control */ 66 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 67 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 68 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 69 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 70 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 71 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 72 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 73 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 74 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 75 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 76 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 77 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 78 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12); 79 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 80 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 81 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 82 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 83 (u32)(rdev->dummy_page.addr >> 12)); 84 for (i = 1; i < 7; i++) 85 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 86 87 r600_pcie_gart_tlb_flush(rdev); 88 rdev->gart.ready = true; 89 return 0; 90 } 91 92 void rv770_pcie_gart_disable(struct radeon_device *rdev) 93 { 94 u32 tmp; 95 int i; 96 97 /* Disable all tables */ 98 for (i = 0; i < 7; i++) 99 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 100 101 /* Setup L2 cache */ 102 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 103 EFFECTIVE_L2_QUEUE_SIZE(7)); 104 WREG32(VM_L2_CNTL2, 0); 105 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 106 /* Setup TLB control */ 107 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 108 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 109 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 110 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 111 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 112 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 113 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 114 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 115 if (rdev->gart.table.vram.robj) { 116 radeon_object_kunmap(rdev->gart.table.vram.robj); 117 radeon_object_unpin(rdev->gart.table.vram.robj); 118 } 119 } 120 121 void rv770_pcie_gart_fini(struct radeon_device *rdev) 122 { 123 rv770_pcie_gart_disable(rdev); 124 radeon_gart_table_vram_free(rdev); 125 radeon_gart_fini(rdev); 126 } 127 128 129 /* 130 * MC 131 */ 132 static void rv770_mc_resume(struct radeon_device *rdev) 133 { 134 u32 d1vga_control, d2vga_control; 135 u32 vga_render_control, vga_hdp_control; 136 u32 d1crtc_control, d2crtc_control; 137 u32 new_d1grph_primary, new_d1grph_secondary; 138 u32 new_d2grph_primary, new_d2grph_secondary; 139 u64 old_vram_start; 140 u32 tmp; 141 int i, j; 142 143 /* Initialize HDP */ 144 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 145 WREG32((0x2c14 + j), 0x00000000); 146 WREG32((0x2c18 + j), 0x00000000); 147 WREG32((0x2c1c + j), 0x00000000); 148 WREG32((0x2c20 + j), 0x00000000); 149 WREG32((0x2c24 + j), 0x00000000); 150 } 151 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 152 153 d1vga_control = RREG32(D1VGA_CONTROL); 154 d2vga_control = RREG32(D2VGA_CONTROL); 155 vga_render_control = RREG32(VGA_RENDER_CONTROL); 156 vga_hdp_control = RREG32(VGA_HDP_CONTROL); 157 d1crtc_control = RREG32(D1CRTC_CONTROL); 158 d2crtc_control = RREG32(D2CRTC_CONTROL); 159 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; 160 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS); 161 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS); 162 new_d1grph_primary += rdev->mc.vram_start - old_vram_start; 163 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start; 164 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS); 165 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS); 166 new_d2grph_primary += rdev->mc.vram_start - old_vram_start; 167 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start; 168 169 /* Stop all video */ 170 WREG32(D1VGA_CONTROL, 0); 171 WREG32(D2VGA_CONTROL, 0); 172 WREG32(VGA_RENDER_CONTROL, 0); 173 WREG32(D1CRTC_UPDATE_LOCK, 1); 174 WREG32(D2CRTC_UPDATE_LOCK, 1); 175 WREG32(D1CRTC_CONTROL, 0); 176 WREG32(D2CRTC_CONTROL, 0); 177 WREG32(D1CRTC_UPDATE_LOCK, 0); 178 WREG32(D2CRTC_UPDATE_LOCK, 0); 179 180 mdelay(1); 181 if (r600_mc_wait_for_idle(rdev)) { 182 printk(KERN_WARNING "[drm] MC not idle !\n"); 183 } 184 185 /* Lockout access through VGA aperture*/ 186 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 187 188 /* Update configuration */ 189 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 190 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12); 191 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 192 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16; 193 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 194 WREG32(MC_VM_FB_LOCATION, tmp); 195 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 196 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 197 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); 198 if (rdev->flags & RADEON_IS_AGP) { 199 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16); 200 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 201 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 202 } else { 203 WREG32(MC_VM_AGP_BASE, 0); 204 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 205 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 206 } 207 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary); 208 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary); 209 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary); 210 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary); 211 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); 212 213 /* Unlock host access */ 214 WREG32(VGA_HDP_CONTROL, vga_hdp_control); 215 216 mdelay(1); 217 if (r600_mc_wait_for_idle(rdev)) { 218 printk(KERN_WARNING "[drm] MC not idle !\n"); 219 } 220 221 /* Restore video state */ 222 WREG32(D1CRTC_UPDATE_LOCK, 1); 223 WREG32(D2CRTC_UPDATE_LOCK, 1); 224 WREG32(D1CRTC_CONTROL, d1crtc_control); 225 WREG32(D2CRTC_CONTROL, d2crtc_control); 226 WREG32(D1CRTC_UPDATE_LOCK, 0); 227 WREG32(D2CRTC_UPDATE_LOCK, 0); 228 WREG32(D1VGA_CONTROL, d1vga_control); 229 WREG32(D2VGA_CONTROL, d2vga_control); 230 WREG32(VGA_RENDER_CONTROL, vga_render_control); 231 232 /* we need to own VRAM, so turn off the VGA renderer here 233 * to stop it overwriting our objects */ 234 radeon_avivo_vga_render_disable(rdev); 235 } 236 237 238 /* 239 * CP. 240 */ 241 void r700_cp_stop(struct radeon_device *rdev) 242 { 243 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); 244 } 245 246 247 static int rv770_cp_load_microcode(struct radeon_device *rdev) 248 { 249 const __be32 *fw_data; 250 int i; 251 252 if (!rdev->me_fw || !rdev->pfp_fw) 253 return -EINVAL; 254 255 r700_cp_stop(rdev); 256 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 257 258 /* Reset cp */ 259 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 260 RREG32(GRBM_SOFT_RESET); 261 mdelay(15); 262 WREG32(GRBM_SOFT_RESET, 0); 263 264 fw_data = (const __be32 *)rdev->pfp_fw->data; 265 WREG32(CP_PFP_UCODE_ADDR, 0); 266 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 267 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 268 WREG32(CP_PFP_UCODE_ADDR, 0); 269 270 fw_data = (const __be32 *)rdev->me_fw->data; 271 WREG32(CP_ME_RAM_WADDR, 0); 272 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 273 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 274 275 WREG32(CP_PFP_UCODE_ADDR, 0); 276 WREG32(CP_ME_RAM_WADDR, 0); 277 WREG32(CP_ME_RAM_RADDR, 0); 278 return 0; 279 } 280 281 282 /* 283 * Core functions 284 */ 285 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 286 u32 num_backends, 287 u32 backend_disable_mask) 288 { 289 u32 backend_map = 0; 290 u32 enabled_backends_mask; 291 u32 enabled_backends_count; 292 u32 cur_pipe; 293 u32 swizzle_pipe[R7XX_MAX_PIPES]; 294 u32 cur_backend; 295 u32 i; 296 297 if (num_tile_pipes > R7XX_MAX_PIPES) 298 num_tile_pipes = R7XX_MAX_PIPES; 299 if (num_tile_pipes < 1) 300 num_tile_pipes = 1; 301 if (num_backends > R7XX_MAX_BACKENDS) 302 num_backends = R7XX_MAX_BACKENDS; 303 if (num_backends < 1) 304 num_backends = 1; 305 306 enabled_backends_mask = 0; 307 enabled_backends_count = 0; 308 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 309 if (((backend_disable_mask >> i) & 1) == 0) { 310 enabled_backends_mask |= (1 << i); 311 ++enabled_backends_count; 312 } 313 if (enabled_backends_count == num_backends) 314 break; 315 } 316 317 if (enabled_backends_count == 0) { 318 enabled_backends_mask = 1; 319 enabled_backends_count = 1; 320 } 321 322 if (enabled_backends_count != num_backends) 323 num_backends = enabled_backends_count; 324 325 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 326 switch (num_tile_pipes) { 327 case 1: 328 swizzle_pipe[0] = 0; 329 break; 330 case 2: 331 swizzle_pipe[0] = 0; 332 swizzle_pipe[1] = 1; 333 break; 334 case 3: 335 swizzle_pipe[0] = 0; 336 swizzle_pipe[1] = 2; 337 swizzle_pipe[2] = 1; 338 break; 339 case 4: 340 swizzle_pipe[0] = 0; 341 swizzle_pipe[1] = 2; 342 swizzle_pipe[2] = 3; 343 swizzle_pipe[3] = 1; 344 break; 345 case 5: 346 swizzle_pipe[0] = 0; 347 swizzle_pipe[1] = 2; 348 swizzle_pipe[2] = 4; 349 swizzle_pipe[3] = 1; 350 swizzle_pipe[4] = 3; 351 break; 352 case 6: 353 swizzle_pipe[0] = 0; 354 swizzle_pipe[1] = 2; 355 swizzle_pipe[2] = 4; 356 swizzle_pipe[3] = 5; 357 swizzle_pipe[4] = 3; 358 swizzle_pipe[5] = 1; 359 break; 360 case 7: 361 swizzle_pipe[0] = 0; 362 swizzle_pipe[1] = 2; 363 swizzle_pipe[2] = 4; 364 swizzle_pipe[3] = 6; 365 swizzle_pipe[4] = 3; 366 swizzle_pipe[5] = 1; 367 swizzle_pipe[6] = 5; 368 break; 369 case 8: 370 swizzle_pipe[0] = 0; 371 swizzle_pipe[1] = 2; 372 swizzle_pipe[2] = 4; 373 swizzle_pipe[3] = 6; 374 swizzle_pipe[4] = 3; 375 swizzle_pipe[5] = 1; 376 swizzle_pipe[6] = 7; 377 swizzle_pipe[7] = 5; 378 break; 379 } 380 381 cur_backend = 0; 382 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 383 while (((1 << cur_backend) & enabled_backends_mask) == 0) 384 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 385 386 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 387 388 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 389 } 390 391 return backend_map; 392 } 393 394 static void rv770_gpu_init(struct radeon_device *rdev) 395 { 396 int i, j, num_qd_pipes; 397 u32 sx_debug_1; 398 u32 smx_dc_ctl0; 399 u32 num_gs_verts_per_thread; 400 u32 vgt_gs_per_es; 401 u32 gs_prim_buffer_depth = 0; 402 u32 sq_ms_fifo_sizes; 403 u32 sq_config; 404 u32 sq_thread_resource_mgmt; 405 u32 hdp_host_path_cntl; 406 u32 sq_dyn_gpr_size_simd_ab_0; 407 u32 backend_map; 408 u32 gb_tiling_config = 0; 409 u32 cc_rb_backend_disable = 0; 410 u32 cc_gc_shader_pipe_config = 0; 411 u32 mc_arb_ramcfg; 412 u32 db_debug4; 413 414 /* setup chip specs */ 415 switch (rdev->family) { 416 case CHIP_RV770: 417 rdev->config.rv770.max_pipes = 4; 418 rdev->config.rv770.max_tile_pipes = 8; 419 rdev->config.rv770.max_simds = 10; 420 rdev->config.rv770.max_backends = 4; 421 rdev->config.rv770.max_gprs = 256; 422 rdev->config.rv770.max_threads = 248; 423 rdev->config.rv770.max_stack_entries = 512; 424 rdev->config.rv770.max_hw_contexts = 8; 425 rdev->config.rv770.max_gs_threads = 16 * 2; 426 rdev->config.rv770.sx_max_export_size = 128; 427 rdev->config.rv770.sx_max_export_pos_size = 16; 428 rdev->config.rv770.sx_max_export_smx_size = 112; 429 rdev->config.rv770.sq_num_cf_insts = 2; 430 431 rdev->config.rv770.sx_num_of_sets = 7; 432 rdev->config.rv770.sc_prim_fifo_size = 0xF9; 433 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 434 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 435 break; 436 case CHIP_RV730: 437 rdev->config.rv770.max_pipes = 2; 438 rdev->config.rv770.max_tile_pipes = 4; 439 rdev->config.rv770.max_simds = 8; 440 rdev->config.rv770.max_backends = 2; 441 rdev->config.rv770.max_gprs = 128; 442 rdev->config.rv770.max_threads = 248; 443 rdev->config.rv770.max_stack_entries = 256; 444 rdev->config.rv770.max_hw_contexts = 8; 445 rdev->config.rv770.max_gs_threads = 16 * 2; 446 rdev->config.rv770.sx_max_export_size = 256; 447 rdev->config.rv770.sx_max_export_pos_size = 32; 448 rdev->config.rv770.sx_max_export_smx_size = 224; 449 rdev->config.rv770.sq_num_cf_insts = 2; 450 451 rdev->config.rv770.sx_num_of_sets = 7; 452 rdev->config.rv770.sc_prim_fifo_size = 0xf9; 453 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 454 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 455 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 456 rdev->config.rv770.sx_max_export_pos_size -= 16; 457 rdev->config.rv770.sx_max_export_smx_size += 16; 458 } 459 break; 460 case CHIP_RV710: 461 rdev->config.rv770.max_pipes = 2; 462 rdev->config.rv770.max_tile_pipes = 2; 463 rdev->config.rv770.max_simds = 2; 464 rdev->config.rv770.max_backends = 1; 465 rdev->config.rv770.max_gprs = 256; 466 rdev->config.rv770.max_threads = 192; 467 rdev->config.rv770.max_stack_entries = 256; 468 rdev->config.rv770.max_hw_contexts = 4; 469 rdev->config.rv770.max_gs_threads = 8 * 2; 470 rdev->config.rv770.sx_max_export_size = 128; 471 rdev->config.rv770.sx_max_export_pos_size = 16; 472 rdev->config.rv770.sx_max_export_smx_size = 112; 473 rdev->config.rv770.sq_num_cf_insts = 1; 474 475 rdev->config.rv770.sx_num_of_sets = 7; 476 rdev->config.rv770.sc_prim_fifo_size = 0x40; 477 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 478 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 479 break; 480 case CHIP_RV740: 481 rdev->config.rv770.max_pipes = 4; 482 rdev->config.rv770.max_tile_pipes = 4; 483 rdev->config.rv770.max_simds = 8; 484 rdev->config.rv770.max_backends = 4; 485 rdev->config.rv770.max_gprs = 256; 486 rdev->config.rv770.max_threads = 248; 487 rdev->config.rv770.max_stack_entries = 512; 488 rdev->config.rv770.max_hw_contexts = 8; 489 rdev->config.rv770.max_gs_threads = 16 * 2; 490 rdev->config.rv770.sx_max_export_size = 256; 491 rdev->config.rv770.sx_max_export_pos_size = 32; 492 rdev->config.rv770.sx_max_export_smx_size = 224; 493 rdev->config.rv770.sq_num_cf_insts = 2; 494 495 rdev->config.rv770.sx_num_of_sets = 7; 496 rdev->config.rv770.sc_prim_fifo_size = 0x100; 497 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; 498 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; 499 500 if (rdev->config.rv770.sx_max_export_pos_size > 16) { 501 rdev->config.rv770.sx_max_export_pos_size -= 16; 502 rdev->config.rv770.sx_max_export_smx_size += 16; 503 } 504 break; 505 default: 506 break; 507 } 508 509 /* Initialize HDP */ 510 j = 0; 511 for (i = 0; i < 32; i++) { 512 WREG32((0x2c14 + j), 0x00000000); 513 WREG32((0x2c18 + j), 0x00000000); 514 WREG32((0x2c1c + j), 0x00000000); 515 WREG32((0x2c20 + j), 0x00000000); 516 WREG32((0x2c24 + j), 0x00000000); 517 j += 0x18; 518 } 519 520 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 521 522 /* setup tiling, simd, pipe config */ 523 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 524 525 switch (rdev->config.rv770.max_tile_pipes) { 526 case 1: 527 gb_tiling_config |= PIPE_TILING(0); 528 break; 529 case 2: 530 gb_tiling_config |= PIPE_TILING(1); 531 break; 532 case 4: 533 gb_tiling_config |= PIPE_TILING(2); 534 break; 535 case 8: 536 gb_tiling_config |= PIPE_TILING(3); 537 break; 538 default: 539 break; 540 } 541 542 if (rdev->family == CHIP_RV770) 543 gb_tiling_config |= BANK_TILING(1); 544 else 545 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK); 546 547 gb_tiling_config |= GROUP_SIZE(0); 548 549 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) { 550 gb_tiling_config |= ROW_TILING(3); 551 gb_tiling_config |= SAMPLE_SPLIT(3); 552 } else { 553 gb_tiling_config |= 554 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 555 gb_tiling_config |= 556 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); 557 } 558 559 gb_tiling_config |= BANK_SWAPS(1); 560 561 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, 562 rdev->config.rv770.max_backends, 563 (0xff << rdev->config.rv770.max_backends) & 0xff); 564 gb_tiling_config |= BACKEND_MAP(backend_map); 565 566 cc_gc_shader_pipe_config = 567 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); 568 cc_gc_shader_pipe_config |= 569 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); 570 571 cc_rb_backend_disable = 572 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); 573 574 WREG32(GB_TILING_CONFIG, gb_tiling_config); 575 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 576 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 577 578 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 579 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 580 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 581 582 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 583 WREG32(CGTS_SYS_TCC_DISABLE, 0); 584 WREG32(CGTS_TCC_DISABLE, 0); 585 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 586 WREG32(CGTS_USER_TCC_DISABLE, 0); 587 588 num_qd_pipes = 589 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); 590 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); 591 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); 592 593 /* set HW defaults for 3D engine */ 594 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 595 ROQ_IB2_START(0x2b))); 596 597 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 598 599 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 600 SYNC_GRADIENT | 601 SYNC_WALKER | 602 SYNC_ALIGNER)); 603 604 sx_debug_1 = RREG32(SX_DEBUG_1); 605 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 606 WREG32(SX_DEBUG_1, sx_debug_1); 607 608 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 609 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); 610 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); 611 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 612 613 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 614 GS_FLUSH_CTL(4) | 615 ACK_FLUSH_CTL(3) | 616 SYNC_FLUSH_CTL)); 617 618 if (rdev->family == CHIP_RV770) 619 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); 620 else { 621 db_debug4 = RREG32(DB_DEBUG4); 622 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; 623 WREG32(DB_DEBUG4, db_debug4); 624 } 625 626 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 627 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 628 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 629 630 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 631 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 632 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 633 634 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 635 636 WREG32(VGT_NUM_INSTANCES, 1); 637 638 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 639 640 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 641 642 WREG32(CP_PERFMON_CNTL, 0); 643 644 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | 645 DONE_FIFO_HIWATER(0xe0) | 646 ALU_UPDATE_FIFO_HIWATER(0x8)); 647 switch (rdev->family) { 648 case CHIP_RV770: 649 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); 650 break; 651 case CHIP_RV730: 652 case CHIP_RV710: 653 case CHIP_RV740: 654 default: 655 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); 656 break; 657 } 658 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 659 660 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 661 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 662 */ 663 sq_config = RREG32(SQ_CONFIG); 664 sq_config &= ~(PS_PRIO(3) | 665 VS_PRIO(3) | 666 GS_PRIO(3) | 667 ES_PRIO(3)); 668 sq_config |= (DX9_CONSTS | 669 VC_ENABLE | 670 EXPORT_SRC_C | 671 PS_PRIO(0) | 672 VS_PRIO(1) | 673 GS_PRIO(2) | 674 ES_PRIO(3)); 675 if (rdev->family == CHIP_RV710) 676 /* no vertex cache */ 677 sq_config &= ~VC_ENABLE; 678 679 WREG32(SQ_CONFIG, sq_config); 680 681 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 682 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | 683 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); 684 685 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | 686 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); 687 688 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | 689 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | 690 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); 691 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) 692 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); 693 else 694 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); 695 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 696 697 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 698 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 699 700 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | 701 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); 702 703 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | 704 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | 705 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | 706 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); 707 708 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 709 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 710 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 711 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 712 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 713 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 714 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 715 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 716 717 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 718 FORCE_EOV_MAX_REZ_CNT(255))); 719 720 if (rdev->family == CHIP_RV710) 721 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | 722 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 723 else 724 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | 725 AUTO_INVLD_EN(ES_AND_GS_AUTO))); 726 727 switch (rdev->family) { 728 case CHIP_RV770: 729 case CHIP_RV730: 730 case CHIP_RV740: 731 gs_prim_buffer_depth = 384; 732 break; 733 case CHIP_RV710: 734 gs_prim_buffer_depth = 128; 735 break; 736 default: 737 break; 738 } 739 740 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; 741 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 742 /* Max value for this is 256 */ 743 if (vgt_gs_per_es > 256) 744 vgt_gs_per_es = 256; 745 746 WREG32(VGT_ES_PER_GS, 128); 747 WREG32(VGT_GS_PER_ES, vgt_gs_per_es); 748 WREG32(VGT_GS_PER_VS, 2); 749 750 /* more default values. 2D/3D driver should adjust as needed */ 751 WREG32(VGT_GS_VERTEX_REUSE, 16); 752 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 753 WREG32(VGT_STRMOUT_EN, 0); 754 WREG32(SX_MISC, 0); 755 WREG32(PA_SC_MODE_CNTL, 0); 756 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); 757 WREG32(PA_SC_AA_CONFIG, 0); 758 WREG32(PA_SC_CLIPRECT_RULE, 0xffff); 759 WREG32(PA_SC_LINE_STIPPLE, 0); 760 WREG32(SPI_INPUT_Z, 0); 761 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 762 WREG32(CB_COLOR7_FRAG, 0); 763 764 /* clear render buffer base addresses */ 765 WREG32(CB_COLOR0_BASE, 0); 766 WREG32(CB_COLOR1_BASE, 0); 767 WREG32(CB_COLOR2_BASE, 0); 768 WREG32(CB_COLOR3_BASE, 0); 769 WREG32(CB_COLOR4_BASE, 0); 770 WREG32(CB_COLOR5_BASE, 0); 771 WREG32(CB_COLOR6_BASE, 0); 772 WREG32(CB_COLOR7_BASE, 0); 773 774 WREG32(TCP_CNTL, 0); 775 776 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 777 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 778 779 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 780 781 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 782 NUM_CLIP_SEQ(3))); 783 784 } 785 786 int rv770_mc_init(struct radeon_device *rdev) 787 { 788 fixed20_12 a; 789 u32 tmp; 790 int r; 791 792 /* Get VRAM informations */ 793 /* FIXME: Don't know how to determine vram width, need to check 794 * vram_width usage 795 */ 796 rdev->mc.vram_width = 128; 797 rdev->mc.vram_is_ddr = true; 798 /* Could aper size report 0 ? */ 799 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 800 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 801 /* Setup GPU memory space */ 802 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 803 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 804 if (rdev->flags & RADEON_IS_AGP) { 805 r = radeon_agp_init(rdev); 806 if (r) 807 return r; 808 /* gtt_size is setup by radeon_agp_init */ 809 rdev->mc.gtt_location = rdev->mc.agp_base; 810 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 811 /* Try to put vram before or after AGP because we 812 * we want SYSTEM_APERTURE to cover both VRAM and 813 * AGP so that GPU can catch out of VRAM/AGP access 814 */ 815 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { 816 /* Enought place before */ 817 rdev->mc.vram_location = rdev->mc.gtt_location - 818 rdev->mc.mc_vram_size; 819 } else if (tmp > rdev->mc.mc_vram_size) { 820 /* Enought place after */ 821 rdev->mc.vram_location = rdev->mc.gtt_location + 822 rdev->mc.gtt_size; 823 } else { 824 /* Try to setup VRAM then AGP might not 825 * not work on some card 826 */ 827 rdev->mc.vram_location = 0x00000000UL; 828 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 829 } 830 } else { 831 rdev->mc.vram_location = 0x00000000UL; 832 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 833 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 834 } 835 rdev->mc.vram_start = rdev->mc.vram_location; 836 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size; 837 rdev->mc.gtt_start = rdev->mc.gtt_location; 838 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size; 839 /* FIXME: we should enforce default clock in case GPU is not in 840 * default setup 841 */ 842 a.full = rfixed_const(100); 843 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 844 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 845 return 0; 846 } 847 int rv770_gpu_reset(struct radeon_device *rdev) 848 { 849 /* FIXME: implement any rv770 specific bits */ 850 return r600_gpu_reset(rdev); 851 } 852 853 static int rv770_startup(struct radeon_device *rdev) 854 { 855 int r; 856 857 radeon_gpu_reset(rdev); 858 rv770_mc_resume(rdev); 859 r = rv770_pcie_gart_enable(rdev); 860 if (r) 861 return r; 862 rv770_gpu_init(rdev); 863 864 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, 865 &rdev->r600_blit.shader_gpu_addr); 866 if (r) { 867 DRM_ERROR("failed to pin blit object %d\n", r); 868 return r; 869 } 870 871 r = radeon_ring_init(rdev, rdev->cp.ring_size); 872 if (r) 873 return r; 874 r = rv770_cp_load_microcode(rdev); 875 if (r) 876 return r; 877 r = r600_cp_resume(rdev); 878 if (r) 879 return r; 880 r = r600_wb_init(rdev); 881 if (r) 882 return r; 883 return 0; 884 } 885 886 int rv770_resume(struct radeon_device *rdev) 887 { 888 int r; 889 890 if (radeon_gpu_reset(rdev)) { 891 /* FIXME: what do we want to do here ? */ 892 } 893 /* post card */ 894 if (rdev->is_atom_bios) { 895 atom_asic_init(rdev->mode_info.atom_context); 896 } else { 897 radeon_combios_asic_init(rdev->ddev); 898 } 899 /* Initialize clocks */ 900 r = radeon_clocks_init(rdev); 901 if (r) { 902 return r; 903 } 904 905 r = rv770_startup(rdev); 906 if (r) { 907 DRM_ERROR("r600 startup failed on resume\n"); 908 return r; 909 } 910 911 r = radeon_ib_test(rdev); 912 if (r) { 913 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 914 return r; 915 } 916 return r; 917 918 } 919 920 int rv770_suspend(struct radeon_device *rdev) 921 { 922 /* FIXME: we should wait for ring to be empty */ 923 r700_cp_stop(rdev); 924 rdev->cp.ready = false; 925 rv770_pcie_gart_disable(rdev); 926 927 /* unpin shaders bo */ 928 radeon_object_unpin(rdev->r600_blit.shader_obj); 929 return 0; 930 } 931 932 /* Plan is to move initialization in that function and use 933 * helper function so that radeon_device_init pretty much 934 * do nothing more than calling asic specific function. This 935 * should also allow to remove a bunch of callback function 936 * like vram_info. 937 */ 938 int rv770_init(struct radeon_device *rdev) 939 { 940 int r; 941 942 rdev->new_init_path = true; 943 r = radeon_dummy_page_init(rdev); 944 if (r) 945 return r; 946 /* This don't do much */ 947 r = radeon_gem_init(rdev); 948 if (r) 949 return r; 950 /* Read BIOS */ 951 if (!radeon_get_bios(rdev)) { 952 if (ASIC_IS_AVIVO(rdev)) 953 return -EINVAL; 954 } 955 /* Must be an ATOMBIOS */ 956 if (!rdev->is_atom_bios) 957 return -EINVAL; 958 r = radeon_atombios_init(rdev); 959 if (r) 960 return r; 961 /* Post card if necessary */ 962 if (!r600_card_posted(rdev) && rdev->bios) { 963 DRM_INFO("GPU not posted. posting now...\n"); 964 atom_asic_init(rdev->mode_info.atom_context); 965 } 966 /* Initialize scratch registers */ 967 r600_scratch_init(rdev); 968 /* Initialize surface registers */ 969 radeon_surface_init(rdev); 970 radeon_get_clock_info(rdev->ddev); 971 r = radeon_clocks_init(rdev); 972 if (r) 973 return r; 974 /* Fence driver */ 975 r = radeon_fence_driver_init(rdev); 976 if (r) 977 return r; 978 r = rv770_mc_init(rdev); 979 if (r) { 980 if (rdev->flags & RADEON_IS_AGP) { 981 /* Retry with disabling AGP */ 982 rv770_fini(rdev); 983 rdev->flags &= ~RADEON_IS_AGP; 984 return rv770_init(rdev); 985 } 986 return r; 987 } 988 /* Memory manager */ 989 r = radeon_object_init(rdev); 990 if (r) 991 return r; 992 rdev->cp.ring_obj = NULL; 993 r600_ring_init(rdev, 1024 * 1024); 994 995 if (!rdev->me_fw || !rdev->pfp_fw) { 996 r = r600_cp_init_microcode(rdev); 997 if (r) { 998 DRM_ERROR("Failed to load firmware!\n"); 999 return r; 1000 } 1001 } 1002 1003 r = r600_pcie_gart_init(rdev); 1004 if (r) 1005 return r; 1006 1007 rdev->accel_working = true; 1008 r = r600_blit_init(rdev); 1009 if (r) { 1010 DRM_ERROR("radeon: failled blitter (%d).\n", r); 1011 rdev->accel_working = false; 1012 } 1013 1014 r = rv770_startup(rdev); 1015 if (r) { 1016 if (rdev->flags & RADEON_IS_AGP) { 1017 /* Retry with disabling AGP */ 1018 rv770_fini(rdev); 1019 rdev->flags &= ~RADEON_IS_AGP; 1020 return rv770_init(rdev); 1021 } 1022 rdev->accel_working = false; 1023 } 1024 if (rdev->accel_working) { 1025 r = radeon_ib_pool_init(rdev); 1026 if (r) { 1027 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); 1028 rdev->accel_working = false; 1029 } 1030 r = radeon_ib_test(rdev); 1031 if (r) { 1032 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1033 rdev->accel_working = false; 1034 } 1035 } 1036 return 0; 1037 } 1038 1039 void rv770_fini(struct radeon_device *rdev) 1040 { 1041 rv770_suspend(rdev); 1042 1043 r600_blit_fini(rdev); 1044 radeon_ring_fini(rdev); 1045 rv770_pcie_gart_fini(rdev); 1046 radeon_gem_fini(rdev); 1047 radeon_fence_driver_fini(rdev); 1048 radeon_clocks_fini(rdev); 1049 #if __OS_HAS_AGP 1050 if (rdev->flags & RADEON_IS_AGP) 1051 radeon_agp_fini(rdev); 1052 #endif 1053 radeon_object_fini(rdev); 1054 if (rdev->is_atom_bios) { 1055 radeon_atombios_fini(rdev); 1056 } else { 1057 radeon_combios_fini(rdev); 1058 } 1059 kfree(rdev->bios); 1060 rdev->bios = NULL; 1061 radeon_dummy_page_fini(rdev); 1062 } 1063