1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __RS780D_H__ 24 #define __RS780D_H__ 25 26 #define CG_SPLL_FUNC_CNTL 0x600 27 # define SPLL_RESET (1 << 0) 28 # define SPLL_SLEEP (1 << 1) 29 # define SPLL_REF_DIV(x) ((x) << 2) 30 # define SPLL_REF_DIV_MASK (7 << 2) 31 # define SPLL_FB_DIV(x) ((x) << 5) 32 # define SPLL_FB_DIV_MASK (0xff << 2) 33 # define SPLL_FB_DIV_SHIFT 2 34 # define SPLL_PULSEEN (1 << 13) 35 # define SPLL_PULSENUM(x) ((x) << 14) 36 # define SPLL_PULSENUM_MASK (3 << 14) 37 # define SPLL_SW_HILEN(x) ((x) << 16) 38 # define SPLL_SW_HILEN_MASK (0xf << 16) 39 # define SPLL_SW_LOLEN(x) ((x) << 20) 40 # define SPLL_SW_LOLEN_MASK (0xf << 20) 41 # define SPLL_DIVEN (1 << 24) 42 # define SPLL_BYPASS_EN (1 << 25) 43 # define SPLL_CHG_STATUS (1 << 29) 44 # define SPLL_CTLREQ (1 << 30) 45 # define SPLL_CTLACK (1 << 31) 46 47 /* RS780/RS880 PM */ 48 #define FVTHROT_CNTRL_REG 0x3000 49 #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) 50 #define MINIMUM_CIP(x) ((x) << 1) 51 #define MINIMUM_CIP_SHIFT 1 52 #define MINIMUM_CIP_MASK 0x1fffffe 53 #define REFRESH_RATE_DIVISOR(x) ((x) << 25) 54 #define REFRESH_RATE_DIVISOR_SHIFT 25 55 #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) 56 #define ENABLE_FV_THROT (1 << 27) 57 #define ENABLE_FV_UPDATE (1 << 28) 58 #define TREND_SEL_MODE (1 << 29) 59 #define FORCE_TREND_SEL (1 << 30) 60 #define ENABLE_FV_THROT_IO (1 << 31) 61 #define FVTHROT_TARGET_REG 0x3004 62 #define TARGET_IDLE_COUNT(x) ((x) << 0) 63 #define TARGET_IDLE_COUNT_MASK 0xffffff 64 #define TARGET_IDLE_COUNT_SHIFT 0 65 #define FVTHROT_CB1 0x3008 66 #define FVTHROT_CB2 0x300c 67 #define FVTHROT_CB3 0x3010 68 #define FVTHROT_CB4 0x3014 69 #define FVTHROT_UTC0 0x3018 70 #define FVTHROT_UTC1 0x301c 71 #define FVTHROT_UTC2 0x3020 72 #define FVTHROT_UTC3 0x3024 73 #define FVTHROT_UTC4 0x3028 74 #define FVTHROT_DTC0 0x302c 75 #define FVTHROT_DTC1 0x3030 76 #define FVTHROT_DTC2 0x3034 77 #define FVTHROT_DTC3 0x3038 78 #define FVTHROT_DTC4 0x303c 79 #define FVTHROT_FBDIV_REG0 0x3040 80 #define MIN_FEEDBACK_DIV(x) ((x) << 0) 81 #define MIN_FEEDBACK_DIV_MASK 0xfff 82 #define MIN_FEEDBACK_DIV_SHIFT 0 83 #define MAX_FEEDBACK_DIV(x) ((x) << 12) 84 #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) 85 #define MAX_FEEDBACK_DIV_SHIFT 12 86 #define FVTHROT_FBDIV_REG1 0x3044 87 #define MAX_FEEDBACK_STEP(x) ((x) << 0) 88 #define MAX_FEEDBACK_STEP_MASK 0xfff 89 #define MAX_FEEDBACK_STEP_SHIFT 0 90 #define STARTING_FEEDBACK_DIV(x) ((x) << 12) 91 #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) 92 #define STARTING_FEEDBACK_DIV_SHIFT 12 93 #define FORCE_FEEDBACK_DIV (1 << 24) 94 #define FVTHROT_FBDIV_REG2 0x3048 95 #define FORCED_FEEDBACK_DIV(x) ((x) << 0) 96 #define FORCED_FEEDBACK_DIV_MASK 0xfff 97 #define FORCED_FEEDBACK_DIV_SHIFT 0 98 #define FB_DIV_TIMER_VAL(x) ((x) << 12) 99 #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) 100 #define FB_DIV_TIMER_VAL_SHIFT 12 101 #define FVTHROT_FB_US_REG0 0x304c 102 #define FVTHROT_FB_US_REG1 0x3050 103 #define FVTHROT_FB_DS_REG0 0x3054 104 #define FVTHROT_FB_DS_REG1 0x3058 105 #define FVTHROT_PWM_CTRL_REG0 0x305c 106 #define STARTING_PWM_HIGHTIME(x) ((x) << 0) 107 #define STARTING_PWM_HIGHTIME_MASK 0xfff 108 #define STARTING_PWM_HIGHTIME_SHIFT 0 109 #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) 110 #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) 111 #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 112 #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) 113 #define INVERT_PWM_WAVEFORM (1 << 25) 114 #define FVTHROT_PWM_CTRL_REG1 0x3060 115 #define MIN_PWM_HIGHTIME(x) ((x) << 0) 116 #define MIN_PWM_HIGHTIME_MASK 0xfff 117 #define MIN_PWM_HIGHTIME_SHIFT 0 118 #define MAX_PWM_HIGHTIME(x) ((x) << 12) 119 #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) 120 #define MAX_PWM_HIGHTIME_SHIFT 12 121 #define FVTHROT_PWM_US_REG0 0x3064 122 #define FVTHROT_PWM_US_REG1 0x3068 123 #define FVTHROT_PWM_DS_REG0 0x306c 124 #define FVTHROT_PWM_DS_REG1 0x3070 125 #define FVTHROT_STATUS_REG0 0x3074 126 #define CURRENT_FEEDBACK_DIV_MASK 0xfff 127 #define CURRENT_FEEDBACK_DIV_SHIFT 0 128 #define FVTHROT_STATUS_REG1 0x3078 129 #define FVTHROT_STATUS_REG2 0x307c 130 #define CG_INTGFX_MISC 0x3080 131 #define FVTHROT_VBLANK_SEL (1 << 9) 132 #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c 133 #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) 134 #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff 135 #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 136 #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) 137 #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 138 #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) 139 #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff 140 #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 141 #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) 142 #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) 143 #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 144 #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 145 #define RANGE0_PWM(x) ((x) << 0) 146 #define RANGE0_PWM_MASK 0xfff 147 #define RANGE0_PWM_SHIFT 0 148 #define RANGE1_PWM(x) ((x) << 12) 149 #define RANGE1_PWM_MASK (0xfff << 12) 150 #define RANGE1_PWM_SHIFT 12 151 #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 152 #define RANGE2_PWM(x) ((x) << 0) 153 #define RANGE2_PWM_MASK 0xfff 154 #define RANGE2_PWM_SHIFT 0 155 #define RANGE3_PWM(x) ((x) << 12) 156 #define RANGE3_PWM_MASK (0xfff << 12) 157 #define RANGE3_PWM_SHIFT 12 158 #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac 159 #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) 160 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff 161 #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 162 #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) 163 164 #define GFX_MACRO_BYPASS_CNTL 0x30c0 165 #define SPLL_BYPASS_CNTL (1 << 0) 166 #define UPLL_BYPASS_CNTL (1 << 1) 167 168 #endif 169