1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon.h" 30 #include "radeon_asic.h" 31 #include "atom.h" 32 #include "rs690d.h" 33 34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev) 35 { 36 unsigned i; 37 uint32_t tmp; 38 39 for (i = 0; i < rdev->usec_timeout; i++) { 40 /* read MC_STATUS */ 41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 42 if (G_000090_MC_SYSTEM_IDLE(tmp)) 43 return 0; 44 udelay(1); 45 } 46 return -1; 47 } 48 49 static void rs690_gpu_init(struct radeon_device *rdev) 50 { 51 /* FIXME: HDP same place on rs690 ? */ 52 r100_hdp_reset(rdev); 53 /* FIXME: is this correct ? */ 54 r420_pipes_init(rdev); 55 if (rs690_mc_wait_for_idle(rdev)) { 56 printk(KERN_WARNING "Failed to wait MC idle while " 57 "programming pipes. Bad things might happen.\n"); 58 } 59 } 60 61 void rs690_pm_info(struct radeon_device *rdev) 62 { 63 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 64 struct _ATOM_INTEGRATED_SYSTEM_INFO *info; 65 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2; 66 void *ptr; 67 uint16_t data_offset; 68 uint8_t frev, crev; 69 fixed20_12 tmp; 70 71 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 72 &frev, &crev, &data_offset); 73 ptr = rdev->mode_info.atom_context->bios + data_offset; 74 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr; 75 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr; 76 /* Get various system informations from bios */ 77 switch (crev) { 78 case 1: 79 tmp.full = rfixed_const(100); 80 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock); 81 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 82 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock)); 83 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock)); 84 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth); 85 break; 86 case 2: 87 tmp.full = rfixed_const(100); 88 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock); 89 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp); 90 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock); 91 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 92 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq); 93 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp); 94 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth)); 95 break; 96 default: 97 tmp.full = rfixed_const(100); 98 /* We assume the slower possible clock ie worst case */ 99 /* DDR 333Mhz */ 100 rdev->pm.igp_sideport_mclk.full = rfixed_const(333); 101 /* FIXME: system clock ? */ 102 rdev->pm.igp_system_mclk.full = rfixed_const(100); 103 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp); 104 rdev->pm.igp_ht_link_clk.full = rfixed_const(200); 105 rdev->pm.igp_ht_link_width.full = rfixed_const(8); 106 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 107 break; 108 } 109 /* Compute various bandwidth */ 110 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 111 tmp.full = rfixed_const(4); 112 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp); 113 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 114 * = ht_clk * ht_width / 5 115 */ 116 tmp.full = rfixed_const(5); 117 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk, 118 rdev->pm.igp_ht_link_width); 119 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp); 120 if (tmp.full < rdev->pm.max_bandwidth.full) { 121 /* HT link is a limiting factor */ 122 rdev->pm.max_bandwidth.full = tmp.full; 123 } 124 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 125 * = (sideport_clk * 14) / 10 126 */ 127 tmp.full = rfixed_const(14); 128 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 129 tmp.full = rfixed_const(10); 130 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp); 131 } 132 133 void rs690_mc_init(struct radeon_device *rdev) 134 { 135 fixed20_12 a; 136 u64 base; 137 138 rs400_gart_adjust_size(rdev); 139 rdev->mc.vram_is_ddr = true; 140 rdev->mc.vram_width = 128; 141 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 142 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 143 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 144 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 145 rdev->mc.visible_vram_size = rdev->mc.aper_size; 146 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 147 base = G_000100_MC_FB_START(base) << 16; 148 rs690_pm_info(rdev); 149 /* FIXME: we should enforce default clock in case GPU is not in 150 * default setup 151 */ 152 a.full = rfixed_const(100); 153 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 154 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 155 a.full = rfixed_const(16); 156 /* core_bandwidth = sclk(Mhz) * 16 */ 157 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a); 158 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 159 radeon_vram_location(rdev, &rdev->mc, base); 160 radeon_gtt_location(rdev, &rdev->mc); 161 } 162 163 void rs690_line_buffer_adjust(struct radeon_device *rdev, 164 struct drm_display_mode *mode1, 165 struct drm_display_mode *mode2) 166 { 167 u32 tmp; 168 169 /* 170 * Line Buffer Setup 171 * There is a single line buffer shared by both display controllers. 172 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 173 * the display controllers. The paritioning can either be done 174 * manually or via one of four preset allocations specified in bits 1:0: 175 * 0 - line buffer is divided in half and shared between crtc 176 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 177 * 2 - D1 gets the whole buffer 178 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 179 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 180 * allocation mode. In manual allocation mode, D1 always starts at 0, 181 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 182 */ 183 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 184 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 185 /* auto */ 186 if (mode1 && mode2) { 187 if (mode1->hdisplay > mode2->hdisplay) { 188 if (mode1->hdisplay > 2560) 189 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 190 else 191 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 192 } else if (mode2->hdisplay > mode1->hdisplay) { 193 if (mode2->hdisplay > 2560) 194 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 195 else 196 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 197 } else 198 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 199 } else if (mode1) { 200 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 201 } else if (mode2) { 202 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 203 } 204 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 205 } 206 207 struct rs690_watermark { 208 u32 lb_request_fifo_depth; 209 fixed20_12 num_line_pair; 210 fixed20_12 estimated_width; 211 fixed20_12 worst_case_latency; 212 fixed20_12 consumption_rate; 213 fixed20_12 active_time; 214 fixed20_12 dbpp; 215 fixed20_12 priority_mark_max; 216 fixed20_12 priority_mark; 217 fixed20_12 sclk; 218 }; 219 220 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 221 struct radeon_crtc *crtc, 222 struct rs690_watermark *wm) 223 { 224 struct drm_display_mode *mode = &crtc->base.mode; 225 fixed20_12 a, b, c; 226 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 227 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 228 /* FIXME: detect IGP with sideport memory, i don't think there is any 229 * such product available 230 */ 231 bool sideport = false; 232 233 if (!crtc->base.enabled) { 234 /* FIXME: wouldn't it better to set priority mark to maximum */ 235 wm->lb_request_fifo_depth = 4; 236 return; 237 } 238 239 if (crtc->vsc.full > rfixed_const(2)) 240 wm->num_line_pair.full = rfixed_const(2); 241 else 242 wm->num_line_pair.full = rfixed_const(1); 243 244 b.full = rfixed_const(mode->crtc_hdisplay); 245 c.full = rfixed_const(256); 246 a.full = rfixed_div(b, c); 247 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair); 248 request_fifo_depth.full = rfixed_ceil(request_fifo_depth); 249 if (a.full < rfixed_const(4)) { 250 wm->lb_request_fifo_depth = 4; 251 } else { 252 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth); 253 } 254 255 /* Determine consumption rate 256 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 257 * vtaps = number of vertical taps, 258 * vsc = vertical scaling ratio, defined as source/destination 259 * hsc = horizontal scaling ration, defined as source/destination 260 */ 261 a.full = rfixed_const(mode->clock); 262 b.full = rfixed_const(1000); 263 a.full = rfixed_div(a, b); 264 pclk.full = rfixed_div(b, a); 265 if (crtc->rmx_type != RMX_OFF) { 266 b.full = rfixed_const(2); 267 if (crtc->vsc.full > b.full) 268 b.full = crtc->vsc.full; 269 b.full = rfixed_mul(b, crtc->hsc); 270 c.full = rfixed_const(2); 271 b.full = rfixed_div(b, c); 272 consumption_time.full = rfixed_div(pclk, b); 273 } else { 274 consumption_time.full = pclk.full; 275 } 276 a.full = rfixed_const(1); 277 wm->consumption_rate.full = rfixed_div(a, consumption_time); 278 279 280 /* Determine line time 281 * LineTime = total time for one line of displayhtotal 282 * LineTime = total number of horizontal pixels 283 * pclk = pixel clock period(ns) 284 */ 285 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 286 line_time.full = rfixed_mul(a, pclk); 287 288 /* Determine active time 289 * ActiveTime = time of active region of display within one line, 290 * hactive = total number of horizontal active pixels 291 * htotal = total number of horizontal pixels 292 */ 293 a.full = rfixed_const(crtc->base.mode.crtc_htotal); 294 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 295 wm->active_time.full = rfixed_mul(line_time, b); 296 wm->active_time.full = rfixed_div(wm->active_time, a); 297 298 /* Maximun bandwidth is the minimun bandwidth of all component */ 299 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 300 if (sideport) { 301 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 302 rdev->pm.sideport_bandwidth.full) 303 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 304 read_delay_latency.full = rfixed_const(370 * 800 * 1000); 305 read_delay_latency.full = rfixed_div(read_delay_latency, 306 rdev->pm.igp_sideport_mclk); 307 } else { 308 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 309 rdev->pm.k8_bandwidth.full) 310 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; 311 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 312 rdev->pm.ht_bandwidth.full) 313 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 314 read_delay_latency.full = rfixed_const(5000); 315 } 316 317 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 318 a.full = rfixed_const(16); 319 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a); 320 a.full = rfixed_const(1000); 321 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk); 322 /* Determine chunk time 323 * ChunkTime = the time it takes the DCP to send one chunk of data 324 * to the LB which consists of pipeline delay and inter chunk gap 325 * sclk = system clock(ns) 326 */ 327 a.full = rfixed_const(256 * 13); 328 chunk_time.full = rfixed_mul(rdev->pm.sclk, a); 329 a.full = rfixed_const(10); 330 chunk_time.full = rfixed_div(chunk_time, a); 331 332 /* Determine the worst case latency 333 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 334 * WorstCaseLatency = worst case time from urgent to when the MC starts 335 * to return data 336 * READ_DELAY_IDLE_MAX = constant of 1us 337 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 338 * which consists of pipeline delay and inter chunk gap 339 */ 340 if (rfixed_trunc(wm->num_line_pair) > 1) { 341 a.full = rfixed_const(3); 342 wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 343 wm->worst_case_latency.full += read_delay_latency.full; 344 } else { 345 a.full = rfixed_const(2); 346 wm->worst_case_latency.full = rfixed_mul(a, chunk_time); 347 wm->worst_case_latency.full += read_delay_latency.full; 348 } 349 350 /* Determine the tolerable latency 351 * TolerableLatency = Any given request has only 1 line time 352 * for the data to be returned 353 * LBRequestFifoDepth = Number of chunk requests the LB can 354 * put into the request FIFO for a display 355 * LineTime = total time for one line of display 356 * ChunkTime = the time it takes the DCP to send one chunk 357 * of data to the LB which consists of 358 * pipeline delay and inter chunk gap 359 */ 360 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) { 361 tolerable_latency.full = line_time.full; 362 } else { 363 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2); 364 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 365 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time); 366 tolerable_latency.full = line_time.full - tolerable_latency.full; 367 } 368 /* We assume worst case 32bits (4 bytes) */ 369 wm->dbpp.full = rfixed_const(4 * 8); 370 371 /* Determine the maximum priority mark 372 * width = viewport width in pixels 373 */ 374 a.full = rfixed_const(16); 375 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay); 376 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a); 377 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max); 378 379 /* Determine estimated width */ 380 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 381 estimated_width.full = rfixed_div(estimated_width, consumption_time); 382 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 383 wm->priority_mark.full = rfixed_const(10); 384 } else { 385 a.full = rfixed_const(16); 386 wm->priority_mark.full = rfixed_div(estimated_width, a); 387 wm->priority_mark.full = rfixed_ceil(wm->priority_mark); 388 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 389 } 390 } 391 392 void rs690_bandwidth_update(struct radeon_device *rdev) 393 { 394 struct drm_display_mode *mode0 = NULL; 395 struct drm_display_mode *mode1 = NULL; 396 struct rs690_watermark wm0; 397 struct rs690_watermark wm1; 398 u32 tmp; 399 fixed20_12 priority_mark02, priority_mark12, fill_rate; 400 fixed20_12 a, b; 401 402 if (rdev->mode_info.crtcs[0]->base.enabled) 403 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 404 if (rdev->mode_info.crtcs[1]->base.enabled) 405 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 406 /* 407 * Set display0/1 priority up in the memory controller for 408 * modes if the user specifies HIGH for displaypriority 409 * option. 410 */ 411 if (rdev->disp_priority == 2) { 412 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 413 tmp &= C_000104_MC_DISP0R_INIT_LAT; 414 tmp &= C_000104_MC_DISP1R_INIT_LAT; 415 if (mode0) 416 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 417 if (mode1) 418 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 419 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 420 } 421 rs690_line_buffer_adjust(rdev, mode0, mode1); 422 423 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 424 WREG32(R_006C9C_DCP_CONTROL, 0); 425 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 426 WREG32(R_006C9C_DCP_CONTROL, 2); 427 428 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 429 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 430 431 tmp = (wm0.lb_request_fifo_depth - 1); 432 tmp |= (wm1.lb_request_fifo_depth - 1) << 16; 433 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 434 435 if (mode0 && mode1) { 436 if (rfixed_trunc(wm0.dbpp) > 64) 437 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); 438 else 439 a.full = wm0.num_line_pair.full; 440 if (rfixed_trunc(wm1.dbpp) > 64) 441 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); 442 else 443 b.full = wm1.num_line_pair.full; 444 a.full += b.full; 445 fill_rate.full = rfixed_div(wm0.sclk, a); 446 if (wm0.consumption_rate.full > fill_rate.full) { 447 b.full = wm0.consumption_rate.full - fill_rate.full; 448 b.full = rfixed_mul(b, wm0.active_time); 449 a.full = rfixed_mul(wm0.worst_case_latency, 450 wm0.consumption_rate); 451 a.full = a.full + b.full; 452 b.full = rfixed_const(16 * 1000); 453 priority_mark02.full = rfixed_div(a, b); 454 } else { 455 a.full = rfixed_mul(wm0.worst_case_latency, 456 wm0.consumption_rate); 457 b.full = rfixed_const(16 * 1000); 458 priority_mark02.full = rfixed_div(a, b); 459 } 460 if (wm1.consumption_rate.full > fill_rate.full) { 461 b.full = wm1.consumption_rate.full - fill_rate.full; 462 b.full = rfixed_mul(b, wm1.active_time); 463 a.full = rfixed_mul(wm1.worst_case_latency, 464 wm1.consumption_rate); 465 a.full = a.full + b.full; 466 b.full = rfixed_const(16 * 1000); 467 priority_mark12.full = rfixed_div(a, b); 468 } else { 469 a.full = rfixed_mul(wm1.worst_case_latency, 470 wm1.consumption_rate); 471 b.full = rfixed_const(16 * 1000); 472 priority_mark12.full = rfixed_div(a, b); 473 } 474 if (wm0.priority_mark.full > priority_mark02.full) 475 priority_mark02.full = wm0.priority_mark.full; 476 if (rfixed_trunc(priority_mark02) < 0) 477 priority_mark02.full = 0; 478 if (wm0.priority_mark_max.full > priority_mark02.full) 479 priority_mark02.full = wm0.priority_mark_max.full; 480 if (wm1.priority_mark.full > priority_mark12.full) 481 priority_mark12.full = wm1.priority_mark.full; 482 if (rfixed_trunc(priority_mark12) < 0) 483 priority_mark12.full = 0; 484 if (wm1.priority_mark_max.full > priority_mark12.full) 485 priority_mark12.full = wm1.priority_mark_max.full; 486 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 487 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 488 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 489 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 490 } else if (mode0) { 491 if (rfixed_trunc(wm0.dbpp) > 64) 492 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); 493 else 494 a.full = wm0.num_line_pair.full; 495 fill_rate.full = rfixed_div(wm0.sclk, a); 496 if (wm0.consumption_rate.full > fill_rate.full) { 497 b.full = wm0.consumption_rate.full - fill_rate.full; 498 b.full = rfixed_mul(b, wm0.active_time); 499 a.full = rfixed_mul(wm0.worst_case_latency, 500 wm0.consumption_rate); 501 a.full = a.full + b.full; 502 b.full = rfixed_const(16 * 1000); 503 priority_mark02.full = rfixed_div(a, b); 504 } else { 505 a.full = rfixed_mul(wm0.worst_case_latency, 506 wm0.consumption_rate); 507 b.full = rfixed_const(16 * 1000); 508 priority_mark02.full = rfixed_div(a, b); 509 } 510 if (wm0.priority_mark.full > priority_mark02.full) 511 priority_mark02.full = wm0.priority_mark.full; 512 if (rfixed_trunc(priority_mark02) < 0) 513 priority_mark02.full = 0; 514 if (wm0.priority_mark_max.full > priority_mark02.full) 515 priority_mark02.full = wm0.priority_mark_max.full; 516 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 517 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 518 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, 519 S_006D48_D2MODE_PRIORITY_A_OFF(1)); 520 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, 521 S_006D4C_D2MODE_PRIORITY_B_OFF(1)); 522 } else { 523 if (rfixed_trunc(wm1.dbpp) > 64) 524 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); 525 else 526 a.full = wm1.num_line_pair.full; 527 fill_rate.full = rfixed_div(wm1.sclk, a); 528 if (wm1.consumption_rate.full > fill_rate.full) { 529 b.full = wm1.consumption_rate.full - fill_rate.full; 530 b.full = rfixed_mul(b, wm1.active_time); 531 a.full = rfixed_mul(wm1.worst_case_latency, 532 wm1.consumption_rate); 533 a.full = a.full + b.full; 534 b.full = rfixed_const(16 * 1000); 535 priority_mark12.full = rfixed_div(a, b); 536 } else { 537 a.full = rfixed_mul(wm1.worst_case_latency, 538 wm1.consumption_rate); 539 b.full = rfixed_const(16 * 1000); 540 priority_mark12.full = rfixed_div(a, b); 541 } 542 if (wm1.priority_mark.full > priority_mark12.full) 543 priority_mark12.full = wm1.priority_mark.full; 544 if (rfixed_trunc(priority_mark12) < 0) 545 priority_mark12.full = 0; 546 if (wm1.priority_mark_max.full > priority_mark12.full) 547 priority_mark12.full = wm1.priority_mark_max.full; 548 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, 549 S_006548_D1MODE_PRIORITY_A_OFF(1)); 550 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, 551 S_00654C_D1MODE_PRIORITY_B_OFF(1)); 552 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 553 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 554 } 555 } 556 557 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 558 { 559 uint32_t r; 560 561 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 562 r = RREG32(R_00007C_MC_DATA); 563 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 564 return r; 565 } 566 567 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 568 { 569 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 570 S_000078_MC_IND_WR_EN(1)); 571 WREG32(R_00007C_MC_DATA, v); 572 WREG32(R_000078_MC_INDEX, 0x7F); 573 } 574 575 void rs690_mc_program(struct radeon_device *rdev) 576 { 577 struct rv515_mc_save save; 578 579 /* Stops all mc clients */ 580 rv515_mc_stop(rdev, &save); 581 582 /* Wait for mc idle */ 583 if (rs690_mc_wait_for_idle(rdev)) 584 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 585 /* Program MC, should be a 32bits limited address space */ 586 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 587 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 588 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 589 WREG32(R_000134_HDP_FB_LOCATION, 590 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 591 592 rv515_mc_resume(rdev, &save); 593 } 594 595 static int rs690_startup(struct radeon_device *rdev) 596 { 597 int r; 598 599 rs690_mc_program(rdev); 600 /* Resume clock */ 601 rv515_clock_startup(rdev); 602 /* Initialize GPU configuration (# pipes, ...) */ 603 rs690_gpu_init(rdev); 604 /* Initialize GART (initialize after TTM so we can allocate 605 * memory through TTM but finalize after TTM) */ 606 r = rs400_gart_enable(rdev); 607 if (r) 608 return r; 609 /* Enable IRQ */ 610 rs600_irq_set(rdev); 611 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 612 /* 1M ring buffer */ 613 r = r100_cp_init(rdev, 1024 * 1024); 614 if (r) { 615 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 616 return r; 617 } 618 r = r100_wb_init(rdev); 619 if (r) 620 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 621 r = r100_ib_init(rdev); 622 if (r) { 623 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 624 return r; 625 } 626 return 0; 627 } 628 629 int rs690_resume(struct radeon_device *rdev) 630 { 631 /* Make sur GART are not working */ 632 rs400_gart_disable(rdev); 633 /* Resume clock before doing reset */ 634 rv515_clock_startup(rdev); 635 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 636 if (radeon_gpu_reset(rdev)) { 637 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 638 RREG32(R_000E40_RBBM_STATUS), 639 RREG32(R_0007C0_CP_STAT)); 640 } 641 /* post */ 642 atom_asic_init(rdev->mode_info.atom_context); 643 /* Resume clock after posting */ 644 rv515_clock_startup(rdev); 645 /* Initialize surface registers */ 646 radeon_surface_init(rdev); 647 return rs690_startup(rdev); 648 } 649 650 int rs690_suspend(struct radeon_device *rdev) 651 { 652 r100_cp_disable(rdev); 653 r100_wb_disable(rdev); 654 rs600_irq_disable(rdev); 655 rs400_gart_disable(rdev); 656 return 0; 657 } 658 659 void rs690_fini(struct radeon_device *rdev) 660 { 661 r100_cp_fini(rdev); 662 r100_wb_fini(rdev); 663 r100_ib_fini(rdev); 664 radeon_gem_fini(rdev); 665 rs400_gart_fini(rdev); 666 radeon_irq_kms_fini(rdev); 667 radeon_fence_driver_fini(rdev); 668 radeon_bo_fini(rdev); 669 radeon_atombios_fini(rdev); 670 kfree(rdev->bios); 671 rdev->bios = NULL; 672 } 673 674 int rs690_init(struct radeon_device *rdev) 675 { 676 int r; 677 678 /* Disable VGA */ 679 rv515_vga_render_disable(rdev); 680 /* Initialize scratch registers */ 681 radeon_scratch_init(rdev); 682 /* Initialize surface registers */ 683 radeon_surface_init(rdev); 684 /* TODO: disable VGA need to use VGA request */ 685 /* BIOS*/ 686 if (!radeon_get_bios(rdev)) { 687 if (ASIC_IS_AVIVO(rdev)) 688 return -EINVAL; 689 } 690 if (rdev->is_atom_bios) { 691 r = radeon_atombios_init(rdev); 692 if (r) 693 return r; 694 } else { 695 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 696 return -EINVAL; 697 } 698 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 699 if (radeon_gpu_reset(rdev)) { 700 dev_warn(rdev->dev, 701 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 702 RREG32(R_000E40_RBBM_STATUS), 703 RREG32(R_0007C0_CP_STAT)); 704 } 705 /* check if cards are posted or not */ 706 if (radeon_boot_test_post_card(rdev) == false) 707 return -EINVAL; 708 709 /* Initialize clocks */ 710 radeon_get_clock_info(rdev->ddev); 711 /* Initialize power management */ 712 radeon_pm_init(rdev); 713 /* initialize memory controller */ 714 rs690_mc_init(rdev); 715 rv515_debugfs(rdev); 716 /* Fence driver */ 717 r = radeon_fence_driver_init(rdev); 718 if (r) 719 return r; 720 r = radeon_irq_kms_init(rdev); 721 if (r) 722 return r; 723 /* Memory manager */ 724 r = radeon_bo_init(rdev); 725 if (r) 726 return r; 727 r = rs400_gart_init(rdev); 728 if (r) 729 return r; 730 rs600_set_safe_registers(rdev); 731 rdev->accel_working = true; 732 r = rs690_startup(rdev); 733 if (r) { 734 /* Somethings want wront with the accel init stop accel */ 735 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 736 r100_cp_fini(rdev); 737 r100_wb_fini(rdev); 738 r100_ib_fini(rdev); 739 rs400_gart_fini(rdev); 740 radeon_irq_kms_fini(rdev); 741 rdev->accel_working = false; 742 } 743 return 0; 744 } 745