1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include <linux/slab.h> 30 #include <drm/drmP.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "rs400d.h" 34 35 /* This files gather functions specifics to : rs400,rs480 */ 36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 37 38 void rs400_gart_adjust_size(struct radeon_device *rdev) 39 { 40 /* Check gart size */ 41 switch (rdev->mc.gtt_size/(1024*1024)) { 42 case 32: 43 case 64: 44 case 128: 45 case 256: 46 case 512: 47 case 1024: 48 case 2048: 49 break; 50 default: 51 DRM_ERROR("Unable to use IGP GART size %uM\n", 52 (unsigned)(rdev->mc.gtt_size >> 20)); 53 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 54 DRM_ERROR("Forcing to 32M GART size\n"); 55 rdev->mc.gtt_size = 32 * 1024 * 1024; 56 return; 57 } 58 } 59 60 void rs400_gart_tlb_flush(struct radeon_device *rdev) 61 { 62 uint32_t tmp; 63 unsigned int timeout = rdev->usec_timeout; 64 65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 66 do { 67 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 68 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 69 break; 70 DRM_UDELAY(1); 71 timeout--; 72 } while (timeout > 0); 73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 74 } 75 76 int rs400_gart_init(struct radeon_device *rdev) 77 { 78 int r; 79 80 if (rdev->gart.ptr) { 81 WARN(1, "RS400 GART already initialized\n"); 82 return 0; 83 } 84 /* Check gart size */ 85 switch(rdev->mc.gtt_size / (1024 * 1024)) { 86 case 32: 87 case 64: 88 case 128: 89 case 256: 90 case 512: 91 case 1024: 92 case 2048: 93 break; 94 default: 95 return -EINVAL; 96 } 97 /* Initialize common gart structure */ 98 r = radeon_gart_init(rdev); 99 if (r) 100 return r; 101 if (rs400_debugfs_pcie_gart_info_init(rdev)) 102 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 104 return radeon_gart_table_ram_alloc(rdev); 105 } 106 107 int rs400_gart_enable(struct radeon_device *rdev) 108 { 109 uint32_t size_reg; 110 uint32_t tmp; 111 112 radeon_gart_restore(rdev); 113 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 114 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 115 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 116 /* Check gart size */ 117 switch(rdev->mc.gtt_size / (1024 * 1024)) { 118 case 32: 119 size_reg = RS480_VA_SIZE_32MB; 120 break; 121 case 64: 122 size_reg = RS480_VA_SIZE_64MB; 123 break; 124 case 128: 125 size_reg = RS480_VA_SIZE_128MB; 126 break; 127 case 256: 128 size_reg = RS480_VA_SIZE_256MB; 129 break; 130 case 512: 131 size_reg = RS480_VA_SIZE_512MB; 132 break; 133 case 1024: 134 size_reg = RS480_VA_SIZE_1GB; 135 break; 136 case 2048: 137 size_reg = RS480_VA_SIZE_2GB; 138 break; 139 default: 140 return -EINVAL; 141 } 142 /* It should be fine to program it to max value */ 143 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 144 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 145 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 146 } else { 147 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 148 WREG32(RS480_AGP_BASE_2, 0); 149 } 150 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 151 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 152 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 153 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 154 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 155 WREG32(RADEON_BUS_CNTL, tmp); 156 } else { 157 WREG32(RADEON_MC_AGP_LOCATION, tmp); 158 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 159 WREG32(RADEON_BUS_CNTL, tmp); 160 } 161 /* Table should be in 32bits address space so ignore bits above. */ 162 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 163 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 164 165 WREG32_MC(RS480_GART_BASE, tmp); 166 /* TODO: more tweaking here */ 167 WREG32_MC(RS480_GART_FEATURE_ID, 168 (RS480_TLB_ENABLE | 169 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 170 /* Disable snooping */ 171 WREG32_MC(RS480_AGP_MODE_CNTL, 172 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 173 /* Disable AGP mode */ 174 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 175 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 176 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 177 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 178 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 179 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 180 } else { 181 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 182 tmp |= RS480_GART_INDEX_REG_EN; 183 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 184 } 185 /* Enable gart */ 186 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 187 rs400_gart_tlb_flush(rdev); 188 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 189 (unsigned)(rdev->mc.gtt_size >> 20), 190 (unsigned long long)rdev->gart.table_addr); 191 rdev->gart.ready = true; 192 return 0; 193 } 194 195 void rs400_gart_disable(struct radeon_device *rdev) 196 { 197 uint32_t tmp; 198 199 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 200 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 201 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 202 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 203 } 204 205 void rs400_gart_fini(struct radeon_device *rdev) 206 { 207 radeon_gart_fini(rdev); 208 rs400_gart_disable(rdev); 209 radeon_gart_table_ram_free(rdev); 210 } 211 212 #define RS400_PTE_WRITEABLE (1 << 2) 213 #define RS400_PTE_READABLE (1 << 3) 214 215 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, uint64_t addr) 216 { 217 uint32_t entry; 218 u32 *gtt = rdev->gart.ptr; 219 220 entry = (lower_32_bits(addr) & PAGE_MASK) | 221 ((upper_32_bits(addr) & 0xff) << 4) | 222 RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 223 entry = cpu_to_le32(entry); 224 gtt[i] = entry; 225 } 226 227 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 228 { 229 unsigned i; 230 uint32_t tmp; 231 232 for (i = 0; i < rdev->usec_timeout; i++) { 233 /* read MC_STATUS */ 234 tmp = RREG32(RADEON_MC_STATUS); 235 if (tmp & RADEON_MC_IDLE) { 236 return 0; 237 } 238 DRM_UDELAY(1); 239 } 240 return -1; 241 } 242 243 static void rs400_gpu_init(struct radeon_device *rdev) 244 { 245 /* FIXME: is this correct ? */ 246 r420_pipes_init(rdev); 247 if (rs400_mc_wait_for_idle(rdev)) { 248 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 249 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 250 } 251 } 252 253 static void rs400_mc_init(struct radeon_device *rdev) 254 { 255 u64 base; 256 257 rs400_gart_adjust_size(rdev); 258 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 259 /* DDR for all card after R300 & IGP */ 260 rdev->mc.vram_is_ddr = true; 261 rdev->mc.vram_width = 128; 262 r100_vram_init_sizes(rdev); 263 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 264 radeon_vram_location(rdev, &rdev->mc, base); 265 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 266 radeon_gtt_location(rdev, &rdev->mc); 267 radeon_update_bandwidth_info(rdev); 268 } 269 270 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 271 { 272 unsigned long flags; 273 uint32_t r; 274 275 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 276 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 277 r = RREG32(RS480_NB_MC_DATA); 278 WREG32(RS480_NB_MC_INDEX, 0xff); 279 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 280 return r; 281 } 282 283 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 284 { 285 unsigned long flags; 286 287 spin_lock_irqsave(&rdev->mc_idx_lock, flags); 288 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 289 WREG32(RS480_NB_MC_DATA, (v)); 290 WREG32(RS480_NB_MC_INDEX, 0xff); 291 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); 292 } 293 294 #if defined(CONFIG_DEBUG_FS) 295 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 296 { 297 struct drm_info_node *node = (struct drm_info_node *) m->private; 298 struct drm_device *dev = node->minor->dev; 299 struct radeon_device *rdev = dev->dev_private; 300 uint32_t tmp; 301 302 tmp = RREG32(RADEON_HOST_PATH_CNTL); 303 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 304 tmp = RREG32(RADEON_BUS_CNTL); 305 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 306 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 307 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 308 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 309 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 310 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 311 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 312 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 313 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 314 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 315 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 316 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 317 tmp = RREG32(RS690_HDP_FB_LOCATION); 318 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 319 } else { 320 tmp = RREG32(RADEON_AGP_BASE); 321 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 322 tmp = RREG32(RS480_AGP_BASE_2); 323 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 324 tmp = RREG32(RADEON_MC_AGP_LOCATION); 325 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 326 } 327 tmp = RREG32_MC(RS480_GART_BASE); 328 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 329 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 330 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 331 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 332 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 333 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 334 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 335 tmp = RREG32_MC(0x5F); 336 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 337 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 338 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 339 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 340 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 341 tmp = RREG32_MC(0x3B); 342 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 343 tmp = RREG32_MC(0x3C); 344 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 345 tmp = RREG32_MC(0x30); 346 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 347 tmp = RREG32_MC(0x31); 348 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 349 tmp = RREG32_MC(0x32); 350 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 351 tmp = RREG32_MC(0x33); 352 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 353 tmp = RREG32_MC(0x34); 354 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x35); 356 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 357 tmp = RREG32_MC(0x36); 358 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 359 tmp = RREG32_MC(0x37); 360 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 361 return 0; 362 } 363 364 static struct drm_info_list rs400_gart_info_list[] = { 365 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 366 }; 367 #endif 368 369 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 370 { 371 #if defined(CONFIG_DEBUG_FS) 372 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 373 #else 374 return 0; 375 #endif 376 } 377 378 static void rs400_mc_program(struct radeon_device *rdev) 379 { 380 struct r100_mc_save save; 381 382 /* Stops all mc clients */ 383 r100_mc_stop(rdev, &save); 384 385 /* Wait for mc idle */ 386 if (rs400_mc_wait_for_idle(rdev)) 387 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 388 WREG32(R_000148_MC_FB_LOCATION, 389 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 390 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 391 392 r100_mc_resume(rdev, &save); 393 } 394 395 static int rs400_startup(struct radeon_device *rdev) 396 { 397 int r; 398 399 r100_set_common_regs(rdev); 400 401 rs400_mc_program(rdev); 402 /* Resume clock */ 403 r300_clock_startup(rdev); 404 /* Initialize GPU configuration (# pipes, ...) */ 405 rs400_gpu_init(rdev); 406 r100_enable_bm(rdev); 407 /* Initialize GART (initialize after TTM so we can allocate 408 * memory through TTM but finalize after TTM) */ 409 r = rs400_gart_enable(rdev); 410 if (r) 411 return r; 412 413 /* allocate wb buffer */ 414 r = radeon_wb_init(rdev); 415 if (r) 416 return r; 417 418 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 419 if (r) { 420 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 421 return r; 422 } 423 424 /* Enable IRQ */ 425 if (!rdev->irq.installed) { 426 r = radeon_irq_kms_init(rdev); 427 if (r) 428 return r; 429 } 430 431 r100_irq_set(rdev); 432 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 433 /* 1M ring buffer */ 434 r = r100_cp_init(rdev, 1024 * 1024); 435 if (r) { 436 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 437 return r; 438 } 439 440 r = radeon_ib_pool_init(rdev); 441 if (r) { 442 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 443 return r; 444 } 445 446 return 0; 447 } 448 449 int rs400_resume(struct radeon_device *rdev) 450 { 451 int r; 452 453 /* Make sur GART are not working */ 454 rs400_gart_disable(rdev); 455 /* Resume clock before doing reset */ 456 r300_clock_startup(rdev); 457 /* setup MC before calling post tables */ 458 rs400_mc_program(rdev); 459 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 460 if (radeon_asic_reset(rdev)) { 461 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 462 RREG32(R_000E40_RBBM_STATUS), 463 RREG32(R_0007C0_CP_STAT)); 464 } 465 /* post */ 466 radeon_combios_asic_init(rdev->ddev); 467 /* Resume clock after posting */ 468 r300_clock_startup(rdev); 469 /* Initialize surface registers */ 470 radeon_surface_init(rdev); 471 472 rdev->accel_working = true; 473 r = rs400_startup(rdev); 474 if (r) { 475 rdev->accel_working = false; 476 } 477 return r; 478 } 479 480 int rs400_suspend(struct radeon_device *rdev) 481 { 482 radeon_pm_suspend(rdev); 483 r100_cp_disable(rdev); 484 radeon_wb_disable(rdev); 485 r100_irq_disable(rdev); 486 rs400_gart_disable(rdev); 487 return 0; 488 } 489 490 void rs400_fini(struct radeon_device *rdev) 491 { 492 radeon_pm_fini(rdev); 493 r100_cp_fini(rdev); 494 radeon_wb_fini(rdev); 495 radeon_ib_pool_fini(rdev); 496 radeon_gem_fini(rdev); 497 rs400_gart_fini(rdev); 498 radeon_irq_kms_fini(rdev); 499 radeon_fence_driver_fini(rdev); 500 radeon_bo_fini(rdev); 501 radeon_atombios_fini(rdev); 502 kfree(rdev->bios); 503 rdev->bios = NULL; 504 } 505 506 int rs400_init(struct radeon_device *rdev) 507 { 508 int r; 509 510 /* Disable VGA */ 511 r100_vga_render_disable(rdev); 512 /* Initialize scratch registers */ 513 radeon_scratch_init(rdev); 514 /* Initialize surface registers */ 515 radeon_surface_init(rdev); 516 /* TODO: disable VGA need to use VGA request */ 517 /* restore some register to sane defaults */ 518 r100_restore_sanity(rdev); 519 /* BIOS*/ 520 if (!radeon_get_bios(rdev)) { 521 if (ASIC_IS_AVIVO(rdev)) 522 return -EINVAL; 523 } 524 if (rdev->is_atom_bios) { 525 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 526 return -EINVAL; 527 } else { 528 r = radeon_combios_init(rdev); 529 if (r) 530 return r; 531 } 532 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 533 if (radeon_asic_reset(rdev)) { 534 dev_warn(rdev->dev, 535 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 536 RREG32(R_000E40_RBBM_STATUS), 537 RREG32(R_0007C0_CP_STAT)); 538 } 539 /* check if cards are posted or not */ 540 if (radeon_boot_test_post_card(rdev) == false) 541 return -EINVAL; 542 543 /* Initialize clocks */ 544 radeon_get_clock_info(rdev->ddev); 545 /* initialize memory controller */ 546 rs400_mc_init(rdev); 547 /* Fence driver */ 548 r = radeon_fence_driver_init(rdev); 549 if (r) 550 return r; 551 /* Memory manager */ 552 r = radeon_bo_init(rdev); 553 if (r) 554 return r; 555 r = rs400_gart_init(rdev); 556 if (r) 557 return r; 558 r300_set_reg_safe(rdev); 559 560 /* Initialize power management */ 561 radeon_pm_init(rdev); 562 563 rdev->accel_working = true; 564 r = rs400_startup(rdev); 565 if (r) { 566 /* Somethings want wront with the accel init stop accel */ 567 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 568 r100_cp_fini(rdev); 569 radeon_wb_fini(rdev); 570 radeon_ib_pool_fini(rdev); 571 rs400_gart_fini(rdev); 572 radeon_irq_kms_fini(rdev); 573 rdev->accel_working = false; 574 } 575 return 0; 576 } 577