1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/debugfs.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/pagemap.h> 36 #include <linux/pci.h> 37 #include <linux/seq_file.h> 38 #include <linux/slab.h> 39 #include <linux/swap.h> 40 41 #include <drm/drm_device.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_prime.h> 44 #include <drm/radeon_drm.h> 45 #include <drm/ttm/ttm_bo.h> 46 #include <drm/ttm/ttm_placement.h> 47 #include <drm/ttm/ttm_range_manager.h> 48 #include <drm/ttm/ttm_tt.h> 49 50 #include "radeon_reg.h" 51 #include "radeon.h" 52 #include "radeon_ttm.h" 53 54 static void radeon_ttm_debugfs_init(struct radeon_device *rdev); 55 56 static int radeon_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 57 struct ttm_resource *bo_mem); 58 static void radeon_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm); 59 60 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev) 61 { 62 struct radeon_mman *mman; 63 struct radeon_device *rdev; 64 65 mman = container_of(bdev, struct radeon_mman, bdev); 66 rdev = container_of(mman, struct radeon_device, mman); 67 return rdev; 68 } 69 70 static int radeon_ttm_init_vram(struct radeon_device *rdev) 71 { 72 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM, 73 false, rdev->mc.real_vram_size >> PAGE_SHIFT); 74 } 75 76 static int radeon_ttm_init_gtt(struct radeon_device *rdev) 77 { 78 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT, 79 true, rdev->mc.gtt_size >> PAGE_SHIFT); 80 } 81 82 static void radeon_evict_flags(struct ttm_buffer_object *bo, 83 struct ttm_placement *placement) 84 { 85 static const struct ttm_place placements = { 86 .fpfn = 0, 87 .lpfn = 0, 88 .mem_type = TTM_PL_SYSTEM, 89 .flags = 0 90 }; 91 92 struct radeon_bo *rbo; 93 94 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 95 placement->placement = &placements; 96 placement->num_placement = 1; 97 return; 98 } 99 rbo = container_of(bo, struct radeon_bo, tbo); 100 switch (bo->resource->mem_type) { 101 case TTM_PL_VRAM: 102 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 103 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 104 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 105 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 106 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 107 int i; 108 109 /* Try evicting to the CPU inaccessible part of VRAM 110 * first, but only set GTT as busy placement, so this 111 * BO will be evicted to GTT rather than causing other 112 * BOs to be evicted from VRAM 113 */ 114 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 115 RADEON_GEM_DOMAIN_GTT); 116 for (i = 0; i < rbo->placement.num_placement; i++) { 117 if (rbo->placements[i].mem_type == TTM_PL_VRAM) { 118 if (rbo->placements[i].fpfn < fpfn) 119 rbo->placements[i].fpfn = fpfn; 120 rbo->placements[0].flags |= TTM_PL_FLAG_DESIRED; 121 } 122 } 123 } else 124 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 125 break; 126 case TTM_PL_TT: 127 default: 128 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 129 } 130 *placement = rbo->placement; 131 } 132 133 static int radeon_move_blit(struct ttm_buffer_object *bo, 134 bool evict, 135 struct ttm_resource *new_mem, 136 struct ttm_resource *old_mem) 137 { 138 struct radeon_device *rdev; 139 uint64_t old_start, new_start; 140 struct radeon_fence *fence; 141 unsigned num_pages; 142 int r, ridx; 143 144 rdev = radeon_get_rdev(bo->bdev); 145 ridx = radeon_copy_ring_index(rdev); 146 old_start = (u64)old_mem->start << PAGE_SHIFT; 147 new_start = (u64)new_mem->start << PAGE_SHIFT; 148 149 switch (old_mem->mem_type) { 150 case TTM_PL_VRAM: 151 old_start += rdev->mc.vram_start; 152 break; 153 case TTM_PL_TT: 154 old_start += rdev->mc.gtt_start; 155 break; 156 default: 157 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 158 return -EINVAL; 159 } 160 switch (new_mem->mem_type) { 161 case TTM_PL_VRAM: 162 new_start += rdev->mc.vram_start; 163 break; 164 case TTM_PL_TT: 165 new_start += rdev->mc.gtt_start; 166 break; 167 default: 168 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 169 return -EINVAL; 170 } 171 if (!rdev->ring[ridx].ready) { 172 DRM_ERROR("Trying to move memory with ring turned off.\n"); 173 return -EINVAL; 174 } 175 176 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 177 178 num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 179 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); 180 if (IS_ERR(fence)) 181 return PTR_ERR(fence); 182 183 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem); 184 radeon_fence_unref(&fence); 185 return r; 186 } 187 188 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, 189 struct ttm_operation_ctx *ctx, 190 struct ttm_resource *new_mem, 191 struct ttm_place *hop) 192 { 193 struct ttm_resource *old_mem = bo->resource; 194 struct radeon_device *rdev; 195 int r; 196 197 if (new_mem->mem_type == TTM_PL_TT) { 198 r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem); 199 if (r) 200 return r; 201 } 202 203 r = ttm_bo_wait_ctx(bo, ctx); 204 if (r) 205 return r; 206 207 rdev = radeon_get_rdev(bo->bdev); 208 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && 209 bo->ttm == NULL)) { 210 ttm_bo_move_null(bo, new_mem); 211 goto out; 212 } 213 if (old_mem->mem_type == TTM_PL_SYSTEM && 214 new_mem->mem_type == TTM_PL_TT) { 215 ttm_bo_move_null(bo, new_mem); 216 goto out; 217 } 218 219 if (old_mem->mem_type == TTM_PL_TT && 220 new_mem->mem_type == TTM_PL_SYSTEM) { 221 radeon_ttm_tt_unbind(bo->bdev, bo->ttm); 222 ttm_bo_move_null(bo, new_mem); 223 goto out; 224 } 225 if (rdev->ring[radeon_copy_ring_index(rdev)].ready && 226 rdev->asic->copy.copy != NULL) { 227 if ((old_mem->mem_type == TTM_PL_SYSTEM && 228 new_mem->mem_type == TTM_PL_VRAM) || 229 (old_mem->mem_type == TTM_PL_VRAM && 230 new_mem->mem_type == TTM_PL_SYSTEM)) { 231 hop->fpfn = 0; 232 hop->lpfn = 0; 233 hop->mem_type = TTM_PL_TT; 234 hop->flags = 0; 235 return -EMULTIHOP; 236 } 237 238 r = radeon_move_blit(bo, evict, new_mem, old_mem); 239 } else { 240 r = -ENODEV; 241 } 242 243 if (r) { 244 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 245 if (r) 246 return r; 247 } 248 249 out: 250 /* update statistics */ 251 atomic64_add(bo->base.size, &rdev->num_bytes_moved); 252 radeon_bo_move_notify(bo); 253 return 0; 254 } 255 256 static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem) 257 { 258 struct radeon_device *rdev = radeon_get_rdev(bdev); 259 size_t bus_size = (size_t)mem->size; 260 261 switch (mem->mem_type) { 262 case TTM_PL_SYSTEM: 263 /* system memory */ 264 return 0; 265 case TTM_PL_TT: 266 #if IS_ENABLED(CONFIG_AGP) 267 if (rdev->flags & RADEON_IS_AGP) { 268 /* RADEON_IS_AGP is set only if AGP is active */ 269 mem->bus.offset = (mem->start << PAGE_SHIFT) + 270 rdev->mc.agp_base; 271 mem->bus.is_iomem = !rdev->agp->cant_use_aperture; 272 mem->bus.caching = ttm_write_combined; 273 } 274 #endif 275 break; 276 case TTM_PL_VRAM: 277 mem->bus.offset = mem->start << PAGE_SHIFT; 278 /* check if it's visible */ 279 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size) 280 return -EINVAL; 281 mem->bus.offset += rdev->mc.aper_base; 282 mem->bus.is_iomem = true; 283 mem->bus.caching = ttm_write_combined; 284 #ifdef __alpha__ 285 /* 286 * Alpha: use bus.addr to hold the ioremap() return, 287 * so we can modify bus.base below. 288 */ 289 mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size); 290 if (!mem->bus.addr) 291 return -ENOMEM; 292 293 /* 294 * Alpha: Use just the bus offset plus 295 * the hose/domain memory base for bus.base. 296 * It then can be used to build PTEs for VRAM 297 * access, as done in ttm_bo_vm_fault(). 298 */ 299 mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) + 300 rdev->hose->dense_mem_base; 301 #endif 302 break; 303 default: 304 return -EINVAL; 305 } 306 return 0; 307 } 308 309 /* 310 * TTM backend functions. 311 */ 312 struct radeon_ttm_tt { 313 struct ttm_tt ttm; 314 u64 offset; 315 316 uint64_t userptr; 317 struct mm_struct *usermm; 318 uint32_t userflags; 319 bool bound; 320 }; 321 322 /* prepare the sg table with the user pages */ 323 static int radeon_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm) 324 { 325 struct radeon_device *rdev = radeon_get_rdev(bdev); 326 struct radeon_ttm_tt *gtt = (void *)ttm; 327 unsigned pinned = 0; 328 int r; 329 330 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 331 enum dma_data_direction direction = write ? 332 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 333 334 if (current->mm != gtt->usermm) 335 return -EPERM; 336 337 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 338 /* check that we only pin down anonymous memory 339 to prevent problems with writeback */ 340 unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE; 341 struct vm_area_struct *vma; 342 vma = find_vma(gtt->usermm, gtt->userptr); 343 if (!vma || vma->vm_file || vma->vm_end < end) 344 return -EPERM; 345 } 346 347 do { 348 unsigned num_pages = ttm->num_pages - pinned; 349 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 350 struct page **pages = ttm->pages + pinned; 351 352 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, 353 pages); 354 if (r < 0) 355 goto release_pages; 356 357 pinned += r; 358 359 } while (pinned < ttm->num_pages); 360 361 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 362 (u64)ttm->num_pages << PAGE_SHIFT, 363 GFP_KERNEL); 364 if (r) 365 goto release_sg; 366 367 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0); 368 if (r) 369 goto release_sg; 370 371 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 372 ttm->num_pages); 373 374 return 0; 375 376 release_sg: 377 kfree(ttm->sg); 378 379 release_pages: 380 release_pages(ttm->pages, pinned); 381 return r; 382 } 383 384 static void radeon_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm) 385 { 386 struct radeon_device *rdev = radeon_get_rdev(bdev); 387 struct radeon_ttm_tt *gtt = (void *)ttm; 388 struct sg_page_iter sg_iter; 389 390 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 391 enum dma_data_direction direction = write ? 392 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 393 394 /* double check that we don't free the table twice */ 395 if (!ttm->sg || !ttm->sg->sgl) 396 return; 397 398 /* free the sg table and pages again */ 399 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0); 400 401 for_each_sgtable_page(ttm->sg, &sg_iter, 0) { 402 struct page *page = sg_page_iter_page(&sg_iter); 403 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) 404 set_page_dirty(page); 405 406 mark_page_accessed(page); 407 put_page(page); 408 } 409 410 sg_free_table(ttm->sg); 411 } 412 413 static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm) 414 { 415 struct radeon_ttm_tt *gtt = (void*)ttm; 416 417 return (gtt->bound); 418 } 419 420 static int radeon_ttm_backend_bind(struct ttm_device *bdev, 421 struct ttm_tt *ttm, 422 struct ttm_resource *bo_mem) 423 { 424 struct radeon_ttm_tt *gtt = (void*)ttm; 425 struct radeon_device *rdev = radeon_get_rdev(bdev); 426 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 427 RADEON_GART_PAGE_WRITE; 428 int r; 429 430 if (gtt->bound) 431 return 0; 432 433 if (gtt->userptr) { 434 radeon_ttm_tt_pin_userptr(bdev, ttm); 435 flags &= ~RADEON_GART_PAGE_WRITE; 436 } 437 438 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 439 if (!ttm->num_pages) { 440 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 441 ttm->num_pages, bo_mem, ttm); 442 } 443 if (ttm->caching == ttm_cached) 444 flags |= RADEON_GART_PAGE_SNOOP; 445 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages, 446 ttm->pages, gtt->ttm.dma_address, flags); 447 if (r) { 448 DRM_ERROR("failed to bind %u pages at 0x%08X\n", 449 ttm->num_pages, (unsigned)gtt->offset); 450 return r; 451 } 452 gtt->bound = true; 453 return 0; 454 } 455 456 static void radeon_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm) 457 { 458 struct radeon_ttm_tt *gtt = (void *)ttm; 459 struct radeon_device *rdev = radeon_get_rdev(bdev); 460 461 if (gtt->userptr) 462 radeon_ttm_tt_unpin_userptr(bdev, ttm); 463 464 if (!gtt->bound) 465 return; 466 467 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages); 468 469 gtt->bound = false; 470 } 471 472 static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm) 473 { 474 struct radeon_ttm_tt *gtt = (void *)ttm; 475 476 ttm_tt_fini(>t->ttm); 477 kfree(gtt); 478 } 479 480 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, 481 uint32_t page_flags) 482 { 483 struct radeon_ttm_tt *gtt; 484 enum ttm_caching caching; 485 struct radeon_bo *rbo; 486 #if IS_ENABLED(CONFIG_AGP) 487 struct radeon_device *rdev = radeon_get_rdev(bo->bdev); 488 489 if (rdev->flags & RADEON_IS_AGP) { 490 return ttm_agp_tt_create(bo, rdev->agp->bridge, page_flags); 491 } 492 #endif 493 rbo = container_of(bo, struct radeon_bo, tbo); 494 495 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 496 if (gtt == NULL) { 497 return NULL; 498 } 499 500 if (rbo->flags & RADEON_GEM_GTT_UC) 501 caching = ttm_uncached; 502 else if (rbo->flags & RADEON_GEM_GTT_WC) 503 caching = ttm_write_combined; 504 else 505 caching = ttm_cached; 506 507 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 508 kfree(gtt); 509 return NULL; 510 } 511 return >t->ttm; 512 } 513 514 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev, 515 struct ttm_tt *ttm) 516 { 517 #if IS_ENABLED(CONFIG_AGP) 518 if (rdev->flags & RADEON_IS_AGP) 519 return NULL; 520 #endif 521 522 if (!ttm) 523 return NULL; 524 return container_of(ttm, struct radeon_ttm_tt, ttm); 525 } 526 527 static int radeon_ttm_tt_populate(struct ttm_device *bdev, 528 struct ttm_tt *ttm, 529 struct ttm_operation_ctx *ctx) 530 { 531 struct radeon_device *rdev = radeon_get_rdev(bdev); 532 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); 533 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); 534 535 if (gtt && gtt->userptr) { 536 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 537 if (!ttm->sg) 538 return -ENOMEM; 539 540 ttm->page_flags |= TTM_TT_FLAG_EXTERNAL; 541 return 0; 542 } 543 544 if (slave && ttm->sg) { 545 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 546 ttm->num_pages); 547 return 0; 548 } 549 550 return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx); 551 } 552 553 static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm) 554 { 555 struct radeon_device *rdev = radeon_get_rdev(bdev); 556 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); 557 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL); 558 559 radeon_ttm_tt_unbind(bdev, ttm); 560 561 if (gtt && gtt->userptr) { 562 kfree(ttm->sg); 563 ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL; 564 return; 565 } 566 567 if (slave) 568 return; 569 570 return ttm_pool_free(&rdev->mman.bdev.pool, ttm); 571 } 572 573 int radeon_ttm_tt_set_userptr(struct radeon_device *rdev, 574 struct ttm_tt *ttm, uint64_t addr, 575 uint32_t flags) 576 { 577 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); 578 579 if (gtt == NULL) 580 return -EINVAL; 581 582 gtt->userptr = addr; 583 gtt->usermm = current->mm; 584 gtt->userflags = flags; 585 return 0; 586 } 587 588 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, 589 struct ttm_tt *ttm) 590 { 591 #if IS_ENABLED(CONFIG_AGP) 592 struct radeon_device *rdev = radeon_get_rdev(bdev); 593 if (rdev->flags & RADEON_IS_AGP) 594 return ttm_agp_is_bound(ttm); 595 #endif 596 return radeon_ttm_backend_is_bound(ttm); 597 } 598 599 static int radeon_ttm_tt_bind(struct ttm_device *bdev, 600 struct ttm_tt *ttm, 601 struct ttm_resource *bo_mem) 602 { 603 #if IS_ENABLED(CONFIG_AGP) 604 struct radeon_device *rdev = radeon_get_rdev(bdev); 605 #endif 606 607 if (!bo_mem) 608 return -EINVAL; 609 #if IS_ENABLED(CONFIG_AGP) 610 if (rdev->flags & RADEON_IS_AGP) 611 return ttm_agp_bind(ttm, bo_mem); 612 #endif 613 614 return radeon_ttm_backend_bind(bdev, ttm, bo_mem); 615 } 616 617 static void radeon_ttm_tt_unbind(struct ttm_device *bdev, 618 struct ttm_tt *ttm) 619 { 620 #if IS_ENABLED(CONFIG_AGP) 621 struct radeon_device *rdev = radeon_get_rdev(bdev); 622 623 if (rdev->flags & RADEON_IS_AGP) { 624 ttm_agp_unbind(ttm); 625 return; 626 } 627 #endif 628 radeon_ttm_backend_unbind(bdev, ttm); 629 } 630 631 static void radeon_ttm_tt_destroy(struct ttm_device *bdev, 632 struct ttm_tt *ttm) 633 { 634 #if IS_ENABLED(CONFIG_AGP) 635 struct radeon_device *rdev = radeon_get_rdev(bdev); 636 637 if (rdev->flags & RADEON_IS_AGP) { 638 ttm_agp_destroy(ttm); 639 return; 640 } 641 #endif 642 radeon_ttm_backend_destroy(bdev, ttm); 643 } 644 645 bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, 646 struct ttm_tt *ttm) 647 { 648 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); 649 650 if (gtt == NULL) 651 return false; 652 653 return !!gtt->userptr; 654 } 655 656 bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, 657 struct ttm_tt *ttm) 658 { 659 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm); 660 661 if (gtt == NULL) 662 return false; 663 664 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 665 } 666 667 static struct ttm_device_funcs radeon_bo_driver = { 668 .ttm_tt_create = &radeon_ttm_tt_create, 669 .ttm_tt_populate = &radeon_ttm_tt_populate, 670 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 671 .ttm_tt_destroy = &radeon_ttm_tt_destroy, 672 .eviction_valuable = ttm_bo_eviction_valuable, 673 .evict_flags = &radeon_evict_flags, 674 .move = &radeon_bo_move, 675 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 676 }; 677 678 int radeon_ttm_init(struct radeon_device *rdev) 679 { 680 int r; 681 682 /* No others user of address space so set it to 0 */ 683 r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev, 684 rdev_to_drm(rdev)->anon_inode->i_mapping, 685 rdev_to_drm(rdev)->vma_offset_manager, 686 (rdev->need_swiotlb ? 687 TTM_ALLOCATION_POOL_USE_DMA_ALLOC : 0) | 688 (dma_addressing_limited(&rdev->pdev->dev) ? 689 TTM_ALLOCATION_POOL_USE_DMA32 : 0)); 690 if (r) { 691 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 692 return r; 693 } 694 rdev->mman.initialized = true; 695 696 r = radeon_ttm_init_vram(rdev); 697 if (r) { 698 DRM_ERROR("Failed initializing VRAM heap.\n"); 699 return r; 700 } 701 /* Change the size here instead of the init above so only lpfn is affected */ 702 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 703 704 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 705 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 706 NULL, &rdev->stolen_vga_memory); 707 if (r) { 708 return r; 709 } 710 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 711 if (r) 712 return r; 713 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 714 radeon_bo_unreserve(rdev->stolen_vga_memory); 715 if (r) { 716 radeon_bo_unref(&rdev->stolen_vga_memory); 717 return r; 718 } 719 DRM_INFO("radeon: %uM of VRAM memory ready\n", 720 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 721 722 r = radeon_ttm_init_gtt(rdev); 723 if (r) { 724 DRM_ERROR("Failed initializing GTT heap.\n"); 725 return r; 726 } 727 DRM_INFO("radeon: %uM of GTT memory ready.\n", 728 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 729 730 radeon_ttm_debugfs_init(rdev); 731 732 return 0; 733 } 734 735 void radeon_ttm_fini(struct radeon_device *rdev) 736 { 737 int r; 738 739 if (!rdev->mman.initialized) 740 return; 741 742 if (rdev->stolen_vga_memory) { 743 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 744 if (r == 0) { 745 radeon_bo_unpin(rdev->stolen_vga_memory); 746 radeon_bo_unreserve(rdev->stolen_vga_memory); 747 } 748 radeon_bo_unref(&rdev->stolen_vga_memory); 749 } 750 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM); 751 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT); 752 ttm_device_fini(&rdev->mman.bdev); 753 radeon_gart_fini(rdev); 754 rdev->mman.initialized = false; 755 DRM_INFO("radeon: ttm finalized\n"); 756 } 757 758 /* this should only be called at bootup or when userspace 759 * isn't running */ 760 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 761 { 762 struct ttm_resource_manager *man; 763 764 if (!rdev->mman.initialized) 765 return; 766 767 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 768 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 769 man->size = size >> PAGE_SHIFT; 770 } 771 772 #if defined(CONFIG_DEBUG_FS) 773 774 static int radeon_ttm_page_pool_show(struct seq_file *m, void *data) 775 { 776 struct radeon_device *rdev = m->private; 777 778 return ttm_pool_debugfs(&rdev->mman.bdev.pool, m); 779 } 780 781 DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool); 782 783 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 784 { 785 struct radeon_device *rdev = inode->i_private; 786 i_size_write(inode, rdev->mc.mc_vram_size); 787 filep->private_data = inode->i_private; 788 return 0; 789 } 790 791 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 792 size_t size, loff_t *pos) 793 { 794 struct radeon_device *rdev = f->private_data; 795 ssize_t result = 0; 796 int r; 797 798 if (size & 0x3 || *pos & 0x3) 799 return -EINVAL; 800 801 while (size) { 802 unsigned long flags; 803 uint32_t value; 804 805 if (*pos >= rdev->mc.mc_vram_size) 806 return result; 807 808 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 809 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 810 if (rdev->family >= CHIP_CEDAR) 811 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 812 value = RREG32(RADEON_MM_DATA); 813 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 814 815 r = put_user(value, (uint32_t __user *)buf); 816 if (r) 817 return r; 818 819 result += 4; 820 buf += 4; 821 *pos += 4; 822 size -= 4; 823 } 824 825 return result; 826 } 827 828 static const struct file_operations radeon_ttm_vram_fops = { 829 .owner = THIS_MODULE, 830 .open = radeon_ttm_vram_open, 831 .read = radeon_ttm_vram_read, 832 .llseek = default_llseek 833 }; 834 835 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 836 { 837 struct radeon_device *rdev = inode->i_private; 838 i_size_write(inode, rdev->mc.gtt_size); 839 filep->private_data = inode->i_private; 840 return 0; 841 } 842 843 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 844 size_t size, loff_t *pos) 845 { 846 struct radeon_device *rdev = f->private_data; 847 ssize_t result = 0; 848 int r; 849 850 while (size) { 851 loff_t p = *pos / PAGE_SIZE; 852 unsigned off = *pos & ~PAGE_MASK; 853 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 854 struct page *page; 855 void *ptr; 856 857 if (p >= rdev->gart.num_cpu_pages) 858 return result; 859 860 page = rdev->gart.pages[p]; 861 if (page) { 862 ptr = kmap_local_page(page); 863 ptr += off; 864 865 r = copy_to_user(buf, ptr, cur_size); 866 kunmap_local(ptr); 867 } else 868 r = clear_user(buf, cur_size); 869 870 if (r) 871 return -EFAULT; 872 873 result += cur_size; 874 buf += cur_size; 875 *pos += cur_size; 876 size -= cur_size; 877 } 878 879 return result; 880 } 881 882 static const struct file_operations radeon_ttm_gtt_fops = { 883 .owner = THIS_MODULE, 884 .open = radeon_ttm_gtt_open, 885 .read = radeon_ttm_gtt_read, 886 .llseek = default_llseek 887 }; 888 889 #endif 890 891 static void radeon_ttm_debugfs_init(struct radeon_device *rdev) 892 { 893 #if defined(CONFIG_DEBUG_FS) 894 struct drm_minor *minor = rdev_to_drm(rdev)->primary; 895 struct dentry *root = minor->debugfs_root; 896 897 debugfs_create_file("radeon_vram", 0444, root, rdev, 898 &radeon_ttm_vram_fops); 899 debugfs_create_file("radeon_gtt", 0444, root, rdev, 900 &radeon_ttm_gtt_fops); 901 debugfs_create_file("ttm_page_pool", 0444, root, rdev, 902 &radeon_ttm_page_pool_fops); 903 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev, 904 TTM_PL_VRAM), 905 root, "radeon_vram_mm"); 906 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev, 907 TTM_PL_TT), 908 root, "radeon_gtt_mm"); 909 #endif 910 } 911