1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 #include <linux/hwmon-sysfs.h> 31 32 #define RADEON_IDLE_LOOP_MS 100 33 #define RADEON_RECLOCK_DELAY_MS 200 34 #define RADEON_WAIT_VBLANK_TIMEOUT 200 35 36 static const char *radeon_pm_state_type_name[5] = { 37 "", 38 "Powersave", 39 "Battery", 40 "Balanced", 41 "Performance", 42 }; 43 44 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 45 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 46 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 48 static void radeon_pm_update_profile(struct radeon_device *rdev); 49 static void radeon_pm_set_clocks(struct radeon_device *rdev); 50 51 int radeon_pm_get_type_index(struct radeon_device *rdev, 52 enum radeon_pm_state_type ps_type, 53 int instance) 54 { 55 int i; 56 int found_instance = -1; 57 58 for (i = 0; i < rdev->pm.num_power_states; i++) { 59 if (rdev->pm.power_state[i].type == ps_type) { 60 found_instance++; 61 if (found_instance == instance) 62 return i; 63 } 64 } 65 /* return default if no match */ 66 return rdev->pm.default_power_state_index; 67 } 68 69 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 70 { 71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 72 mutex_lock(&rdev->pm.mutex); 73 if (power_supply_is_system_supplied() > 0) 74 rdev->pm.dpm.ac_power = true; 75 else 76 rdev->pm.dpm.ac_power = false; 77 if (rdev->family == CHIP_ARUBA) { 78 if (rdev->asic->dpm.enable_bapm) 79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 80 } 81 mutex_unlock(&rdev->pm.mutex); 82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 83 if (rdev->pm.profile == PM_PROFILE_AUTO) { 84 mutex_lock(&rdev->pm.mutex); 85 radeon_pm_update_profile(rdev); 86 radeon_pm_set_clocks(rdev); 87 mutex_unlock(&rdev->pm.mutex); 88 } 89 } 90 } 91 92 static void radeon_pm_update_profile(struct radeon_device *rdev) 93 { 94 switch (rdev->pm.profile) { 95 case PM_PROFILE_DEFAULT: 96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 97 break; 98 case PM_PROFILE_AUTO: 99 if (power_supply_is_system_supplied() > 0) { 100 if (rdev->pm.active_crtc_count > 1) 101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 102 else 103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 104 } else { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 109 } 110 break; 111 case PM_PROFILE_LOW: 112 if (rdev->pm.active_crtc_count > 1) 113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 114 else 115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 116 break; 117 case PM_PROFILE_MID: 118 if (rdev->pm.active_crtc_count > 1) 119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 120 else 121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 122 break; 123 case PM_PROFILE_HIGH: 124 if (rdev->pm.active_crtc_count > 1) 125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 126 else 127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 128 break; 129 } 130 131 if (rdev->pm.active_crtc_count == 0) { 132 rdev->pm.requested_power_state_index = 133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 134 rdev->pm.requested_clock_mode_index = 135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 136 } else { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 141 } 142 } 143 144 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 145 { 146 struct radeon_bo *bo, *n; 147 148 if (list_empty(&rdev->gem.objects)) 149 return; 150 151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 153 ttm_bo_unmap_virtual(&bo->tbo); 154 } 155 } 156 157 static void radeon_sync_with_vblank(struct radeon_device *rdev) 158 { 159 if (rdev->pm.active_crtcs) { 160 rdev->pm.vblank_sync = false; 161 wait_event_timeout( 162 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 164 } 165 } 166 167 static void radeon_set_power_state(struct radeon_device *rdev) 168 { 169 u32 sclk, mclk; 170 bool misc_after = false; 171 172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 174 return; 175 176 if (radeon_gui_idle(rdev)) { 177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 178 clock_info[rdev->pm.requested_clock_mode_index].sclk; 179 if (sclk > rdev->pm.default_sclk) 180 sclk = rdev->pm.default_sclk; 181 182 /* starting with BTC, there is one state that is used for both 183 * MH and SH. Difference is that we always use the high clock index for 184 * mclk and vddci. 185 */ 186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 187 (rdev->family >= CHIP_BARTS) && 188 rdev->pm.active_crtc_count && 189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 193 else 194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 195 clock_info[rdev->pm.requested_clock_mode_index].mclk; 196 197 if (mclk > rdev->pm.default_mclk) 198 mclk = rdev->pm.default_mclk; 199 200 /* upvolt before raising clocks, downvolt after lowering clocks */ 201 if (sclk < rdev->pm.current_sclk) 202 misc_after = true; 203 204 radeon_sync_with_vblank(rdev); 205 206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 207 if (!radeon_pm_in_vbl(rdev)) 208 return; 209 } 210 211 radeon_pm_prepare(rdev); 212 213 if (!misc_after) 214 /* voltage, pcie lanes, etc.*/ 215 radeon_pm_misc(rdev); 216 217 /* set engine clock */ 218 if (sclk != rdev->pm.current_sclk) { 219 radeon_pm_debug_check_in_vbl(rdev, false); 220 radeon_set_engine_clock(rdev, sclk); 221 radeon_pm_debug_check_in_vbl(rdev, true); 222 rdev->pm.current_sclk = sclk; 223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 224 } 225 226 /* set memory clock */ 227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 228 radeon_pm_debug_check_in_vbl(rdev, false); 229 radeon_set_memory_clock(rdev, mclk); 230 radeon_pm_debug_check_in_vbl(rdev, true); 231 rdev->pm.current_mclk = mclk; 232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 233 } 234 235 if (misc_after) 236 /* voltage, pcie lanes, etc.*/ 237 radeon_pm_misc(rdev); 238 239 radeon_pm_finish(rdev); 240 241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 243 } else 244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 245 } 246 247 static void radeon_pm_set_clocks(struct radeon_device *rdev) 248 { 249 int i, r; 250 251 /* no need to take locks, etc. if nothing's going to change */ 252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 254 return; 255 256 down_write(&rdev->pm.mclk_lock); 257 mutex_lock(&rdev->ring_lock); 258 259 /* wait for the rings to drain */ 260 for (i = 0; i < RADEON_NUM_RINGS; i++) { 261 struct radeon_ring *ring = &rdev->ring[i]; 262 if (!ring->ready) { 263 continue; 264 } 265 r = radeon_fence_wait_empty(rdev, i); 266 if (r) { 267 /* needs a GPU reset dont reset here */ 268 mutex_unlock(&rdev->ring_lock); 269 up_write(&rdev->pm.mclk_lock); 270 return; 271 } 272 } 273 274 radeon_unmap_vram_bos(rdev); 275 276 if (rdev->irq.installed) { 277 for (i = 0; i < rdev->num_crtc; i++) { 278 if (rdev->pm.active_crtcs & (1 << i)) { 279 rdev->pm.req_vblank |= (1 << i); 280 drm_vblank_get(rdev->ddev, i); 281 } 282 } 283 } 284 285 radeon_set_power_state(rdev); 286 287 if (rdev->irq.installed) { 288 for (i = 0; i < rdev->num_crtc; i++) { 289 if (rdev->pm.req_vblank & (1 << i)) { 290 rdev->pm.req_vblank &= ~(1 << i); 291 drm_vblank_put(rdev->ddev, i); 292 } 293 } 294 } 295 296 /* update display watermarks based on new power state */ 297 radeon_update_bandwidth_info(rdev); 298 if (rdev->pm.active_crtc_count) 299 radeon_bandwidth_update(rdev); 300 301 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 302 303 mutex_unlock(&rdev->ring_lock); 304 up_write(&rdev->pm.mclk_lock); 305 } 306 307 static void radeon_pm_print_states(struct radeon_device *rdev) 308 { 309 int i, j; 310 struct radeon_power_state *power_state; 311 struct radeon_pm_clock_info *clock_info; 312 313 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 314 for (i = 0; i < rdev->pm.num_power_states; i++) { 315 power_state = &rdev->pm.power_state[i]; 316 DRM_DEBUG_DRIVER("State %d: %s\n", i, 317 radeon_pm_state_type_name[power_state->type]); 318 if (i == rdev->pm.default_power_state_index) 319 DRM_DEBUG_DRIVER("\tDefault"); 320 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 321 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 322 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 323 DRM_DEBUG_DRIVER("\tSingle display only\n"); 324 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 325 for (j = 0; j < power_state->num_clock_modes; j++) { 326 clock_info = &(power_state->clock_info[j]); 327 if (rdev->flags & RADEON_IS_IGP) 328 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 329 j, 330 clock_info->sclk * 10); 331 else 332 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 333 j, 334 clock_info->sclk * 10, 335 clock_info->mclk * 10, 336 clock_info->voltage.voltage); 337 } 338 } 339 } 340 341 static ssize_t radeon_get_pm_profile(struct device *dev, 342 struct device_attribute *attr, 343 char *buf) 344 { 345 struct drm_device *ddev = dev_get_drvdata(dev); 346 struct radeon_device *rdev = ddev->dev_private; 347 int cp = rdev->pm.profile; 348 349 return snprintf(buf, PAGE_SIZE, "%s\n", 350 (cp == PM_PROFILE_AUTO) ? "auto" : 351 (cp == PM_PROFILE_LOW) ? "low" : 352 (cp == PM_PROFILE_MID) ? "mid" : 353 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 354 } 355 356 static ssize_t radeon_set_pm_profile(struct device *dev, 357 struct device_attribute *attr, 358 const char *buf, 359 size_t count) 360 { 361 struct drm_device *ddev = dev_get_drvdata(dev); 362 struct radeon_device *rdev = ddev->dev_private; 363 364 /* Can't set profile when the card is off */ 365 if ((rdev->flags & RADEON_IS_PX) && 366 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 367 return -EINVAL; 368 369 mutex_lock(&rdev->pm.mutex); 370 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 371 if (strncmp("default", buf, strlen("default")) == 0) 372 rdev->pm.profile = PM_PROFILE_DEFAULT; 373 else if (strncmp("auto", buf, strlen("auto")) == 0) 374 rdev->pm.profile = PM_PROFILE_AUTO; 375 else if (strncmp("low", buf, strlen("low")) == 0) 376 rdev->pm.profile = PM_PROFILE_LOW; 377 else if (strncmp("mid", buf, strlen("mid")) == 0) 378 rdev->pm.profile = PM_PROFILE_MID; 379 else if (strncmp("high", buf, strlen("high")) == 0) 380 rdev->pm.profile = PM_PROFILE_HIGH; 381 else { 382 count = -EINVAL; 383 goto fail; 384 } 385 radeon_pm_update_profile(rdev); 386 radeon_pm_set_clocks(rdev); 387 } else 388 count = -EINVAL; 389 390 fail: 391 mutex_unlock(&rdev->pm.mutex); 392 393 return count; 394 } 395 396 static ssize_t radeon_get_pm_method(struct device *dev, 397 struct device_attribute *attr, 398 char *buf) 399 { 400 struct drm_device *ddev = dev_get_drvdata(dev); 401 struct radeon_device *rdev = ddev->dev_private; 402 int pm = rdev->pm.pm_method; 403 404 return snprintf(buf, PAGE_SIZE, "%s\n", 405 (pm == PM_METHOD_DYNPM) ? "dynpm" : 406 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 407 } 408 409 static ssize_t radeon_set_pm_method(struct device *dev, 410 struct device_attribute *attr, 411 const char *buf, 412 size_t count) 413 { 414 struct drm_device *ddev = dev_get_drvdata(dev); 415 struct radeon_device *rdev = ddev->dev_private; 416 417 /* Can't set method when the card is off */ 418 if ((rdev->flags & RADEON_IS_PX) && 419 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 420 count = -EINVAL; 421 goto fail; 422 } 423 424 /* we don't support the legacy modes with dpm */ 425 if (rdev->pm.pm_method == PM_METHOD_DPM) { 426 count = -EINVAL; 427 goto fail; 428 } 429 430 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 431 mutex_lock(&rdev->pm.mutex); 432 rdev->pm.pm_method = PM_METHOD_DYNPM; 433 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 434 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 435 mutex_unlock(&rdev->pm.mutex); 436 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 437 mutex_lock(&rdev->pm.mutex); 438 /* disable dynpm */ 439 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 440 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 441 rdev->pm.pm_method = PM_METHOD_PROFILE; 442 mutex_unlock(&rdev->pm.mutex); 443 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 444 } else { 445 count = -EINVAL; 446 goto fail; 447 } 448 radeon_pm_compute_clocks(rdev); 449 fail: 450 return count; 451 } 452 453 static ssize_t radeon_get_dpm_state(struct device *dev, 454 struct device_attribute *attr, 455 char *buf) 456 { 457 struct drm_device *ddev = dev_get_drvdata(dev); 458 struct radeon_device *rdev = ddev->dev_private; 459 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 460 461 return snprintf(buf, PAGE_SIZE, "%s\n", 462 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 463 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 464 } 465 466 static ssize_t radeon_set_dpm_state(struct device *dev, 467 struct device_attribute *attr, 468 const char *buf, 469 size_t count) 470 { 471 struct drm_device *ddev = dev_get_drvdata(dev); 472 struct radeon_device *rdev = ddev->dev_private; 473 474 mutex_lock(&rdev->pm.mutex); 475 if (strncmp("battery", buf, strlen("battery")) == 0) 476 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 477 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 479 else if (strncmp("performance", buf, strlen("performance")) == 0) 480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 481 else { 482 mutex_unlock(&rdev->pm.mutex); 483 count = -EINVAL; 484 goto fail; 485 } 486 mutex_unlock(&rdev->pm.mutex); 487 488 /* Can't set dpm state when the card is off */ 489 if (!(rdev->flags & RADEON_IS_PX) || 490 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 491 radeon_pm_compute_clocks(rdev); 492 493 fail: 494 return count; 495 } 496 497 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 498 struct device_attribute *attr, 499 char *buf) 500 { 501 struct drm_device *ddev = dev_get_drvdata(dev); 502 struct radeon_device *rdev = ddev->dev_private; 503 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 504 505 if ((rdev->flags & RADEON_IS_PX) && 506 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 507 return snprintf(buf, PAGE_SIZE, "off\n"); 508 509 return snprintf(buf, PAGE_SIZE, "%s\n", 510 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 511 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 512 } 513 514 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 515 struct device_attribute *attr, 516 const char *buf, 517 size_t count) 518 { 519 struct drm_device *ddev = dev_get_drvdata(dev); 520 struct radeon_device *rdev = ddev->dev_private; 521 enum radeon_dpm_forced_level level; 522 int ret = 0; 523 524 /* Can't force performance level when the card is off */ 525 if ((rdev->flags & RADEON_IS_PX) && 526 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 527 return -EINVAL; 528 529 mutex_lock(&rdev->pm.mutex); 530 if (strncmp("low", buf, strlen("low")) == 0) { 531 level = RADEON_DPM_FORCED_LEVEL_LOW; 532 } else if (strncmp("high", buf, strlen("high")) == 0) { 533 level = RADEON_DPM_FORCED_LEVEL_HIGH; 534 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 535 level = RADEON_DPM_FORCED_LEVEL_AUTO; 536 } else { 537 count = -EINVAL; 538 goto fail; 539 } 540 if (rdev->asic->dpm.force_performance_level) { 541 if (rdev->pm.dpm.thermal_active) { 542 count = -EINVAL; 543 goto fail; 544 } 545 ret = radeon_dpm_force_performance_level(rdev, level); 546 if (ret) 547 count = -EINVAL; 548 } 549 fail: 550 mutex_unlock(&rdev->pm.mutex); 551 552 return count; 553 } 554 555 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 556 struct device_attribute *attr, 557 char *buf) 558 { 559 struct radeon_device *rdev = dev_get_drvdata(dev); 560 u32 pwm_mode = 0; 561 562 if (rdev->asic->dpm.fan_ctrl_get_mode) 563 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 564 565 /* never 0 (full-speed), fuse or smc-controlled always */ 566 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 567 } 568 569 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 570 struct device_attribute *attr, 571 const char *buf, 572 size_t count) 573 { 574 struct radeon_device *rdev = dev_get_drvdata(dev); 575 int err; 576 int value; 577 578 if(!rdev->asic->dpm.fan_ctrl_set_mode) 579 return -EINVAL; 580 581 err = kstrtoint(buf, 10, &value); 582 if (err) 583 return err; 584 585 switch (value) { 586 case 1: /* manual, percent-based */ 587 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 588 break; 589 default: /* disable */ 590 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 591 break; 592 } 593 594 return count; 595 } 596 597 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 598 struct device_attribute *attr, 599 char *buf) 600 { 601 return sprintf(buf, "%i\n", 0); 602 } 603 604 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 605 struct device_attribute *attr, 606 char *buf) 607 { 608 return sprintf(buf, "%i\n", 255); 609 } 610 611 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 612 struct device_attribute *attr, 613 const char *buf, size_t count) 614 { 615 struct radeon_device *rdev = dev_get_drvdata(dev); 616 int err; 617 u32 value; 618 619 err = kstrtou32(buf, 10, &value); 620 if (err) 621 return err; 622 623 value = (value * 100) / 255; 624 625 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 626 if (err) 627 return err; 628 629 return count; 630 } 631 632 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 633 struct device_attribute *attr, 634 char *buf) 635 { 636 struct radeon_device *rdev = dev_get_drvdata(dev); 637 int err; 638 u32 speed; 639 640 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 641 if (err) 642 return err; 643 644 speed = (speed * 255) / 100; 645 646 return sprintf(buf, "%i\n", speed); 647 } 648 649 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 650 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 651 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 652 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 653 radeon_get_dpm_forced_performance_level, 654 radeon_set_dpm_forced_performance_level); 655 656 static ssize_t radeon_hwmon_show_temp(struct device *dev, 657 struct device_attribute *attr, 658 char *buf) 659 { 660 struct radeon_device *rdev = dev_get_drvdata(dev); 661 struct drm_device *ddev = rdev->ddev; 662 int temp; 663 664 /* Can't get temperature when the card is off */ 665 if ((rdev->flags & RADEON_IS_PX) && 666 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 667 return -EINVAL; 668 669 if (rdev->asic->pm.get_temperature) 670 temp = radeon_get_temperature(rdev); 671 else 672 temp = 0; 673 674 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 675 } 676 677 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 678 struct device_attribute *attr, 679 char *buf) 680 { 681 struct radeon_device *rdev = dev_get_drvdata(dev); 682 int hyst = to_sensor_dev_attr(attr)->index; 683 int temp; 684 685 if (hyst) 686 temp = rdev->pm.dpm.thermal.min_temp; 687 else 688 temp = rdev->pm.dpm.thermal.max_temp; 689 690 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 691 } 692 693 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 694 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 695 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 696 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 697 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 698 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 699 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 700 701 702 static struct attribute *hwmon_attributes[] = { 703 &sensor_dev_attr_temp1_input.dev_attr.attr, 704 &sensor_dev_attr_temp1_crit.dev_attr.attr, 705 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 706 &sensor_dev_attr_pwm1.dev_attr.attr, 707 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 708 &sensor_dev_attr_pwm1_min.dev_attr.attr, 709 &sensor_dev_attr_pwm1_max.dev_attr.attr, 710 NULL 711 }; 712 713 static umode_t hwmon_attributes_visible(struct kobject *kobj, 714 struct attribute *attr, int index) 715 { 716 struct device *dev = container_of(kobj, struct device, kobj); 717 struct radeon_device *rdev = dev_get_drvdata(dev); 718 umode_t effective_mode = attr->mode; 719 720 /* Skip limit attributes if DPM is not enabled */ 721 if (rdev->pm.pm_method != PM_METHOD_DPM && 722 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 723 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 724 return 0; 725 726 /* Skip fan attributes if fan is not present */ 727 if (rdev->pm.no_fan && 728 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 729 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 730 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 731 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 732 return 0; 733 734 /* mask fan attributes if we have no bindings for this asic to expose */ 735 if ((!rdev->asic->dpm.get_fan_speed_percent && 736 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 737 (!rdev->asic->dpm.fan_ctrl_get_mode && 738 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 739 effective_mode &= ~S_IRUGO; 740 741 if ((!rdev->asic->dpm.set_fan_speed_percent && 742 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 743 (!rdev->asic->dpm.fan_ctrl_set_mode && 744 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 745 effective_mode &= ~S_IWUSR; 746 747 /* hide max/min values if we can't both query and manage the fan */ 748 if ((!rdev->asic->dpm.set_fan_speed_percent && 749 !rdev->asic->dpm.get_fan_speed_percent) && 750 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 751 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 752 return 0; 753 754 return effective_mode; 755 } 756 757 static const struct attribute_group hwmon_attrgroup = { 758 .attrs = hwmon_attributes, 759 .is_visible = hwmon_attributes_visible, 760 }; 761 762 static const struct attribute_group *hwmon_groups[] = { 763 &hwmon_attrgroup, 764 NULL 765 }; 766 767 static int radeon_hwmon_init(struct radeon_device *rdev) 768 { 769 int err = 0; 770 771 switch (rdev->pm.int_thermal_type) { 772 case THERMAL_TYPE_RV6XX: 773 case THERMAL_TYPE_RV770: 774 case THERMAL_TYPE_EVERGREEN: 775 case THERMAL_TYPE_NI: 776 case THERMAL_TYPE_SUMO: 777 case THERMAL_TYPE_SI: 778 case THERMAL_TYPE_CI: 779 case THERMAL_TYPE_KV: 780 if (rdev->asic->pm.get_temperature == NULL) 781 return err; 782 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 783 "radeon", rdev, 784 hwmon_groups); 785 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 786 err = PTR_ERR(rdev->pm.int_hwmon_dev); 787 dev_err(rdev->dev, 788 "Unable to register hwmon device: %d\n", err); 789 } 790 break; 791 default: 792 break; 793 } 794 795 return err; 796 } 797 798 static void radeon_hwmon_fini(struct radeon_device *rdev) 799 { 800 if (rdev->pm.int_hwmon_dev) 801 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 802 } 803 804 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 805 { 806 struct radeon_device *rdev = 807 container_of(work, struct radeon_device, 808 pm.dpm.thermal.work); 809 /* switch to the thermal state */ 810 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 811 812 if (!rdev->pm.dpm_enabled) 813 return; 814 815 if (rdev->asic->pm.get_temperature) { 816 int temp = radeon_get_temperature(rdev); 817 818 if (temp < rdev->pm.dpm.thermal.min_temp) 819 /* switch back the user state */ 820 dpm_state = rdev->pm.dpm.user_state; 821 } else { 822 if (rdev->pm.dpm.thermal.high_to_low) 823 /* switch back the user state */ 824 dpm_state = rdev->pm.dpm.user_state; 825 } 826 mutex_lock(&rdev->pm.mutex); 827 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 828 rdev->pm.dpm.thermal_active = true; 829 else 830 rdev->pm.dpm.thermal_active = false; 831 rdev->pm.dpm.state = dpm_state; 832 mutex_unlock(&rdev->pm.mutex); 833 834 radeon_pm_compute_clocks(rdev); 835 } 836 837 static bool radeon_dpm_single_display(struct radeon_device *rdev) 838 { 839 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 840 true : false; 841 842 /* check if the vblank period is too short to adjust the mclk */ 843 if (single_display && rdev->asic->dpm.vblank_too_short) { 844 if (radeon_dpm_vblank_too_short(rdev)) 845 single_display = false; 846 } 847 848 /* 120hz tends to be problematic even if they are under the 849 * vblank limit. 850 */ 851 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 852 single_display = false; 853 854 return single_display; 855 } 856 857 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 858 enum radeon_pm_state_type dpm_state) 859 { 860 int i; 861 struct radeon_ps *ps; 862 u32 ui_class; 863 bool single_display = radeon_dpm_single_display(rdev); 864 865 /* certain older asics have a separare 3D performance state, 866 * so try that first if the user selected performance 867 */ 868 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 869 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 870 /* balanced states don't exist at the moment */ 871 if (dpm_state == POWER_STATE_TYPE_BALANCED) 872 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 873 874 restart_search: 875 /* Pick the best power state based on current conditions */ 876 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 877 ps = &rdev->pm.dpm.ps[i]; 878 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 879 switch (dpm_state) { 880 /* user states */ 881 case POWER_STATE_TYPE_BATTERY: 882 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 883 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 884 if (single_display) 885 return ps; 886 } else 887 return ps; 888 } 889 break; 890 case POWER_STATE_TYPE_BALANCED: 891 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 892 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 893 if (single_display) 894 return ps; 895 } else 896 return ps; 897 } 898 break; 899 case POWER_STATE_TYPE_PERFORMANCE: 900 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 901 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 902 if (single_display) 903 return ps; 904 } else 905 return ps; 906 } 907 break; 908 /* internal states */ 909 case POWER_STATE_TYPE_INTERNAL_UVD: 910 if (rdev->pm.dpm.uvd_ps) 911 return rdev->pm.dpm.uvd_ps; 912 else 913 break; 914 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 915 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 916 return ps; 917 break; 918 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 919 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 920 return ps; 921 break; 922 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 923 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 924 return ps; 925 break; 926 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 927 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 928 return ps; 929 break; 930 case POWER_STATE_TYPE_INTERNAL_BOOT: 931 return rdev->pm.dpm.boot_ps; 932 case POWER_STATE_TYPE_INTERNAL_THERMAL: 933 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 934 return ps; 935 break; 936 case POWER_STATE_TYPE_INTERNAL_ACPI: 937 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 938 return ps; 939 break; 940 case POWER_STATE_TYPE_INTERNAL_ULV: 941 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 942 return ps; 943 break; 944 case POWER_STATE_TYPE_INTERNAL_3DPERF: 945 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 946 return ps; 947 break; 948 default: 949 break; 950 } 951 } 952 /* use a fallback state if we didn't match */ 953 switch (dpm_state) { 954 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 956 goto restart_search; 957 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 958 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 959 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 960 if (rdev->pm.dpm.uvd_ps) { 961 return rdev->pm.dpm.uvd_ps; 962 } else { 963 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 964 goto restart_search; 965 } 966 case POWER_STATE_TYPE_INTERNAL_THERMAL: 967 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 968 goto restart_search; 969 case POWER_STATE_TYPE_INTERNAL_ACPI: 970 dpm_state = POWER_STATE_TYPE_BATTERY; 971 goto restart_search; 972 case POWER_STATE_TYPE_BATTERY: 973 case POWER_STATE_TYPE_BALANCED: 974 case POWER_STATE_TYPE_INTERNAL_3DPERF: 975 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 976 goto restart_search; 977 default: 978 break; 979 } 980 981 return NULL; 982 } 983 984 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 985 { 986 int i; 987 struct radeon_ps *ps; 988 enum radeon_pm_state_type dpm_state; 989 int ret; 990 bool single_display = radeon_dpm_single_display(rdev); 991 992 /* if dpm init failed */ 993 if (!rdev->pm.dpm_enabled) 994 return; 995 996 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 997 /* add other state override checks here */ 998 if ((!rdev->pm.dpm.thermal_active) && 999 (!rdev->pm.dpm.uvd_active)) 1000 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1001 } 1002 dpm_state = rdev->pm.dpm.state; 1003 1004 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1005 if (ps) 1006 rdev->pm.dpm.requested_ps = ps; 1007 else 1008 return; 1009 1010 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1011 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1012 /* vce just modifies an existing state so force a change */ 1013 if (ps->vce_active != rdev->pm.dpm.vce_active) 1014 goto force; 1015 /* user has made a display change (such as timing) */ 1016 if (rdev->pm.dpm.single_display != single_display) 1017 goto force; 1018 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1019 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1020 * all we need to do is update the display configuration. 1021 */ 1022 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1023 /* update display watermarks based on new power state */ 1024 radeon_bandwidth_update(rdev); 1025 /* update displays */ 1026 radeon_dpm_display_configuration_changed(rdev); 1027 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1028 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1029 } 1030 return; 1031 } else { 1032 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1033 * nothing to do, if the num crtcs is > 1 and state is the same, 1034 * update display configuration. 1035 */ 1036 if (rdev->pm.dpm.new_active_crtcs == 1037 rdev->pm.dpm.current_active_crtcs) { 1038 return; 1039 } else { 1040 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1041 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1042 /* update display watermarks based on new power state */ 1043 radeon_bandwidth_update(rdev); 1044 /* update displays */ 1045 radeon_dpm_display_configuration_changed(rdev); 1046 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1047 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1048 return; 1049 } 1050 } 1051 } 1052 } 1053 1054 force: 1055 if (radeon_dpm == 1) { 1056 printk("switching from power state:\n"); 1057 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1058 printk("switching to power state:\n"); 1059 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1060 } 1061 1062 down_write(&rdev->pm.mclk_lock); 1063 mutex_lock(&rdev->ring_lock); 1064 1065 /* update whether vce is active */ 1066 ps->vce_active = rdev->pm.dpm.vce_active; 1067 1068 ret = radeon_dpm_pre_set_power_state(rdev); 1069 if (ret) 1070 goto done; 1071 1072 /* update display watermarks based on new power state */ 1073 radeon_bandwidth_update(rdev); 1074 /* update displays */ 1075 radeon_dpm_display_configuration_changed(rdev); 1076 1077 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1078 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1079 rdev->pm.dpm.single_display = single_display; 1080 1081 /* wait for the rings to drain */ 1082 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1083 struct radeon_ring *ring = &rdev->ring[i]; 1084 if (ring->ready) 1085 radeon_fence_wait_empty(rdev, i); 1086 } 1087 1088 /* program the new power state */ 1089 radeon_dpm_set_power_state(rdev); 1090 1091 /* update current power state */ 1092 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1093 1094 radeon_dpm_post_set_power_state(rdev); 1095 1096 if (rdev->asic->dpm.force_performance_level) { 1097 if (rdev->pm.dpm.thermal_active) { 1098 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1099 /* force low perf level for thermal */ 1100 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1101 /* save the user's level */ 1102 rdev->pm.dpm.forced_level = level; 1103 } else { 1104 /* otherwise, user selected level */ 1105 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1106 } 1107 } 1108 1109 done: 1110 mutex_unlock(&rdev->ring_lock); 1111 up_write(&rdev->pm.mclk_lock); 1112 } 1113 1114 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1115 { 1116 enum radeon_pm_state_type dpm_state; 1117 1118 if (rdev->asic->dpm.powergate_uvd) { 1119 mutex_lock(&rdev->pm.mutex); 1120 /* don't powergate anything if we 1121 have active but pause streams */ 1122 enable |= rdev->pm.dpm.sd > 0; 1123 enable |= rdev->pm.dpm.hd > 0; 1124 /* enable/disable UVD */ 1125 radeon_dpm_powergate_uvd(rdev, !enable); 1126 mutex_unlock(&rdev->pm.mutex); 1127 } else { 1128 if (enable) { 1129 mutex_lock(&rdev->pm.mutex); 1130 rdev->pm.dpm.uvd_active = true; 1131 /* disable this for now */ 1132 #if 0 1133 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1134 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1135 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1136 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1137 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1138 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1139 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1140 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1141 else 1142 #endif 1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1144 rdev->pm.dpm.state = dpm_state; 1145 mutex_unlock(&rdev->pm.mutex); 1146 } else { 1147 mutex_lock(&rdev->pm.mutex); 1148 rdev->pm.dpm.uvd_active = false; 1149 mutex_unlock(&rdev->pm.mutex); 1150 } 1151 1152 radeon_pm_compute_clocks(rdev); 1153 } 1154 } 1155 1156 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1157 { 1158 if (enable) { 1159 mutex_lock(&rdev->pm.mutex); 1160 rdev->pm.dpm.vce_active = true; 1161 /* XXX select vce level based on ring/task */ 1162 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1163 mutex_unlock(&rdev->pm.mutex); 1164 } else { 1165 mutex_lock(&rdev->pm.mutex); 1166 rdev->pm.dpm.vce_active = false; 1167 mutex_unlock(&rdev->pm.mutex); 1168 } 1169 1170 radeon_pm_compute_clocks(rdev); 1171 } 1172 1173 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1174 { 1175 mutex_lock(&rdev->pm.mutex); 1176 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1177 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1178 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1179 } 1180 mutex_unlock(&rdev->pm.mutex); 1181 1182 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1183 } 1184 1185 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1186 { 1187 mutex_lock(&rdev->pm.mutex); 1188 /* disable dpm */ 1189 radeon_dpm_disable(rdev); 1190 /* reset the power state */ 1191 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1192 rdev->pm.dpm_enabled = false; 1193 mutex_unlock(&rdev->pm.mutex); 1194 } 1195 1196 void radeon_pm_suspend(struct radeon_device *rdev) 1197 { 1198 if (rdev->pm.pm_method == PM_METHOD_DPM) 1199 radeon_pm_suspend_dpm(rdev); 1200 else 1201 radeon_pm_suspend_old(rdev); 1202 } 1203 1204 static void radeon_pm_resume_old(struct radeon_device *rdev) 1205 { 1206 /* set up the default clocks if the MC ucode is loaded */ 1207 if ((rdev->family >= CHIP_BARTS) && 1208 (rdev->family <= CHIP_CAYMAN) && 1209 rdev->mc_fw) { 1210 if (rdev->pm.default_vddc) 1211 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1212 SET_VOLTAGE_TYPE_ASIC_VDDC); 1213 if (rdev->pm.default_vddci) 1214 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1215 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1216 if (rdev->pm.default_sclk) 1217 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1218 if (rdev->pm.default_mclk) 1219 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1220 } 1221 /* asic init will reset the default power state */ 1222 mutex_lock(&rdev->pm.mutex); 1223 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1224 rdev->pm.current_clock_mode_index = 0; 1225 rdev->pm.current_sclk = rdev->pm.default_sclk; 1226 rdev->pm.current_mclk = rdev->pm.default_mclk; 1227 if (rdev->pm.power_state) { 1228 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1229 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1230 } 1231 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1232 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1233 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1234 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1235 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1236 } 1237 mutex_unlock(&rdev->pm.mutex); 1238 radeon_pm_compute_clocks(rdev); 1239 } 1240 1241 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1242 { 1243 int ret; 1244 1245 /* asic init will reset to the boot state */ 1246 mutex_lock(&rdev->pm.mutex); 1247 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1248 radeon_dpm_setup_asic(rdev); 1249 ret = radeon_dpm_enable(rdev); 1250 mutex_unlock(&rdev->pm.mutex); 1251 if (ret) 1252 goto dpm_resume_fail; 1253 rdev->pm.dpm_enabled = true; 1254 return; 1255 1256 dpm_resume_fail: 1257 DRM_ERROR("radeon: dpm resume failed\n"); 1258 if ((rdev->family >= CHIP_BARTS) && 1259 (rdev->family <= CHIP_CAYMAN) && 1260 rdev->mc_fw) { 1261 if (rdev->pm.default_vddc) 1262 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1263 SET_VOLTAGE_TYPE_ASIC_VDDC); 1264 if (rdev->pm.default_vddci) 1265 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1266 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1267 if (rdev->pm.default_sclk) 1268 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1269 if (rdev->pm.default_mclk) 1270 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1271 } 1272 } 1273 1274 void radeon_pm_resume(struct radeon_device *rdev) 1275 { 1276 if (rdev->pm.pm_method == PM_METHOD_DPM) 1277 radeon_pm_resume_dpm(rdev); 1278 else 1279 radeon_pm_resume_old(rdev); 1280 } 1281 1282 static int radeon_pm_init_old(struct radeon_device *rdev) 1283 { 1284 int ret; 1285 1286 rdev->pm.profile = PM_PROFILE_DEFAULT; 1287 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1288 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1289 rdev->pm.dynpm_can_upclock = true; 1290 rdev->pm.dynpm_can_downclock = true; 1291 rdev->pm.default_sclk = rdev->clock.default_sclk; 1292 rdev->pm.default_mclk = rdev->clock.default_mclk; 1293 rdev->pm.current_sclk = rdev->clock.default_sclk; 1294 rdev->pm.current_mclk = rdev->clock.default_mclk; 1295 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1296 1297 if (rdev->bios) { 1298 if (rdev->is_atom_bios) 1299 radeon_atombios_get_power_modes(rdev); 1300 else 1301 radeon_combios_get_power_modes(rdev); 1302 radeon_pm_print_states(rdev); 1303 radeon_pm_init_profile(rdev); 1304 /* set up the default clocks if the MC ucode is loaded */ 1305 if ((rdev->family >= CHIP_BARTS) && 1306 (rdev->family <= CHIP_CAYMAN) && 1307 rdev->mc_fw) { 1308 if (rdev->pm.default_vddc) 1309 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1310 SET_VOLTAGE_TYPE_ASIC_VDDC); 1311 if (rdev->pm.default_vddci) 1312 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1313 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1314 if (rdev->pm.default_sclk) 1315 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1316 if (rdev->pm.default_mclk) 1317 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1318 } 1319 } 1320 1321 /* set up the internal thermal sensor if applicable */ 1322 ret = radeon_hwmon_init(rdev); 1323 if (ret) 1324 return ret; 1325 1326 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1327 1328 if (rdev->pm.num_power_states > 1) { 1329 if (radeon_debugfs_pm_init(rdev)) { 1330 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1331 } 1332 1333 DRM_INFO("radeon: power management initialized\n"); 1334 } 1335 1336 return 0; 1337 } 1338 1339 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1340 { 1341 int i; 1342 1343 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1344 printk("== power state %d ==\n", i); 1345 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1346 } 1347 } 1348 1349 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1350 { 1351 int ret; 1352 1353 /* default to balanced state */ 1354 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1355 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1356 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1357 rdev->pm.default_sclk = rdev->clock.default_sclk; 1358 rdev->pm.default_mclk = rdev->clock.default_mclk; 1359 rdev->pm.current_sclk = rdev->clock.default_sclk; 1360 rdev->pm.current_mclk = rdev->clock.default_mclk; 1361 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1362 1363 if (rdev->bios && rdev->is_atom_bios) 1364 radeon_atombios_get_power_modes(rdev); 1365 else 1366 return -EINVAL; 1367 1368 /* set up the internal thermal sensor if applicable */ 1369 ret = radeon_hwmon_init(rdev); 1370 if (ret) 1371 return ret; 1372 1373 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1374 mutex_lock(&rdev->pm.mutex); 1375 radeon_dpm_init(rdev); 1376 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1377 if (radeon_dpm == 1) 1378 radeon_dpm_print_power_states(rdev); 1379 radeon_dpm_setup_asic(rdev); 1380 ret = radeon_dpm_enable(rdev); 1381 mutex_unlock(&rdev->pm.mutex); 1382 if (ret) 1383 goto dpm_failed; 1384 rdev->pm.dpm_enabled = true; 1385 1386 if (radeon_debugfs_pm_init(rdev)) { 1387 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1388 } 1389 1390 DRM_INFO("radeon: dpm initialized\n"); 1391 1392 return 0; 1393 1394 dpm_failed: 1395 rdev->pm.dpm_enabled = false; 1396 if ((rdev->family >= CHIP_BARTS) && 1397 (rdev->family <= CHIP_CAYMAN) && 1398 rdev->mc_fw) { 1399 if (rdev->pm.default_vddc) 1400 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1401 SET_VOLTAGE_TYPE_ASIC_VDDC); 1402 if (rdev->pm.default_vddci) 1403 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1404 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1405 if (rdev->pm.default_sclk) 1406 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1407 if (rdev->pm.default_mclk) 1408 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1409 } 1410 DRM_ERROR("radeon: dpm initialization failed\n"); 1411 return ret; 1412 } 1413 1414 struct radeon_dpm_quirk { 1415 u32 chip_vendor; 1416 u32 chip_device; 1417 u32 subsys_vendor; 1418 u32 subsys_device; 1419 }; 1420 1421 /* cards with dpm stability problems */ 1422 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1423 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1424 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1425 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1426 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1427 { 0, 0, 0, 0 }, 1428 }; 1429 1430 int radeon_pm_init(struct radeon_device *rdev) 1431 { 1432 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1433 bool disable_dpm = false; 1434 1435 /* Apply dpm quirks */ 1436 while (p && p->chip_device != 0) { 1437 if (rdev->pdev->vendor == p->chip_vendor && 1438 rdev->pdev->device == p->chip_device && 1439 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1440 rdev->pdev->subsystem_device == p->subsys_device) { 1441 disable_dpm = true; 1442 break; 1443 } 1444 ++p; 1445 } 1446 1447 /* enable dpm on rv6xx+ */ 1448 switch (rdev->family) { 1449 case CHIP_RV610: 1450 case CHIP_RV630: 1451 case CHIP_RV620: 1452 case CHIP_RV635: 1453 case CHIP_RV670: 1454 case CHIP_RS780: 1455 case CHIP_RS880: 1456 case CHIP_RV770: 1457 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1458 if (!rdev->rlc_fw) 1459 rdev->pm.pm_method = PM_METHOD_PROFILE; 1460 else if ((rdev->family >= CHIP_RV770) && 1461 (!(rdev->flags & RADEON_IS_IGP)) && 1462 (!rdev->smc_fw)) 1463 rdev->pm.pm_method = PM_METHOD_PROFILE; 1464 else if (radeon_dpm == 1) 1465 rdev->pm.pm_method = PM_METHOD_DPM; 1466 else 1467 rdev->pm.pm_method = PM_METHOD_PROFILE; 1468 break; 1469 case CHIP_RV730: 1470 case CHIP_RV710: 1471 case CHIP_RV740: 1472 case CHIP_CEDAR: 1473 case CHIP_REDWOOD: 1474 case CHIP_JUNIPER: 1475 case CHIP_CYPRESS: 1476 case CHIP_HEMLOCK: 1477 case CHIP_PALM: 1478 case CHIP_SUMO: 1479 case CHIP_SUMO2: 1480 case CHIP_BARTS: 1481 case CHIP_TURKS: 1482 case CHIP_CAICOS: 1483 case CHIP_CAYMAN: 1484 case CHIP_ARUBA: 1485 case CHIP_TAHITI: 1486 case CHIP_PITCAIRN: 1487 case CHIP_VERDE: 1488 case CHIP_OLAND: 1489 case CHIP_HAINAN: 1490 case CHIP_BONAIRE: 1491 case CHIP_KABINI: 1492 case CHIP_KAVERI: 1493 case CHIP_HAWAII: 1494 case CHIP_MULLINS: 1495 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1496 if (!rdev->rlc_fw) 1497 rdev->pm.pm_method = PM_METHOD_PROFILE; 1498 else if ((rdev->family >= CHIP_RV770) && 1499 (!(rdev->flags & RADEON_IS_IGP)) && 1500 (!rdev->smc_fw)) 1501 rdev->pm.pm_method = PM_METHOD_PROFILE; 1502 else if (disable_dpm && (radeon_dpm == -1)) 1503 rdev->pm.pm_method = PM_METHOD_PROFILE; 1504 else if (radeon_dpm == 0) 1505 rdev->pm.pm_method = PM_METHOD_PROFILE; 1506 else 1507 rdev->pm.pm_method = PM_METHOD_DPM; 1508 break; 1509 default: 1510 /* default to profile method */ 1511 rdev->pm.pm_method = PM_METHOD_PROFILE; 1512 break; 1513 } 1514 1515 if (rdev->pm.pm_method == PM_METHOD_DPM) 1516 return radeon_pm_init_dpm(rdev); 1517 else 1518 return radeon_pm_init_old(rdev); 1519 } 1520 1521 int radeon_pm_late_init(struct radeon_device *rdev) 1522 { 1523 int ret = 0; 1524 1525 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1526 if (rdev->pm.dpm_enabled) { 1527 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1528 if (ret) 1529 DRM_ERROR("failed to create device file for dpm state\n"); 1530 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1531 if (ret) 1532 DRM_ERROR("failed to create device file for dpm state\n"); 1533 /* XXX: these are noops for dpm but are here for backwards compat */ 1534 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1535 if (ret) 1536 DRM_ERROR("failed to create device file for power profile\n"); 1537 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1538 if (ret) 1539 DRM_ERROR("failed to create device file for power method\n"); 1540 1541 mutex_lock(&rdev->pm.mutex); 1542 ret = radeon_dpm_late_enable(rdev); 1543 mutex_unlock(&rdev->pm.mutex); 1544 if (ret) { 1545 rdev->pm.dpm_enabled = false; 1546 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1547 } else { 1548 /* set the dpm state for PX since there won't be 1549 * a modeset to call this. 1550 */ 1551 radeon_pm_compute_clocks(rdev); 1552 } 1553 } 1554 } else { 1555 if (rdev->pm.num_power_states > 1) { 1556 /* where's the best place to put these? */ 1557 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1558 if (ret) 1559 DRM_ERROR("failed to create device file for power profile\n"); 1560 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1561 if (ret) 1562 DRM_ERROR("failed to create device file for power method\n"); 1563 } 1564 } 1565 return ret; 1566 } 1567 1568 static void radeon_pm_fini_old(struct radeon_device *rdev) 1569 { 1570 if (rdev->pm.num_power_states > 1) { 1571 mutex_lock(&rdev->pm.mutex); 1572 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1573 rdev->pm.profile = PM_PROFILE_DEFAULT; 1574 radeon_pm_update_profile(rdev); 1575 radeon_pm_set_clocks(rdev); 1576 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1577 /* reset default clocks */ 1578 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1579 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1580 radeon_pm_set_clocks(rdev); 1581 } 1582 mutex_unlock(&rdev->pm.mutex); 1583 1584 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1585 1586 device_remove_file(rdev->dev, &dev_attr_power_profile); 1587 device_remove_file(rdev->dev, &dev_attr_power_method); 1588 } 1589 1590 radeon_hwmon_fini(rdev); 1591 kfree(rdev->pm.power_state); 1592 } 1593 1594 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1595 { 1596 if (rdev->pm.num_power_states > 1) { 1597 mutex_lock(&rdev->pm.mutex); 1598 radeon_dpm_disable(rdev); 1599 mutex_unlock(&rdev->pm.mutex); 1600 1601 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1602 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1603 /* XXX backwards compat */ 1604 device_remove_file(rdev->dev, &dev_attr_power_profile); 1605 device_remove_file(rdev->dev, &dev_attr_power_method); 1606 } 1607 radeon_dpm_fini(rdev); 1608 1609 radeon_hwmon_fini(rdev); 1610 kfree(rdev->pm.power_state); 1611 } 1612 1613 void radeon_pm_fini(struct radeon_device *rdev) 1614 { 1615 if (rdev->pm.pm_method == PM_METHOD_DPM) 1616 radeon_pm_fini_dpm(rdev); 1617 else 1618 radeon_pm_fini_old(rdev); 1619 } 1620 1621 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1622 { 1623 struct drm_device *ddev = rdev->ddev; 1624 struct drm_crtc *crtc; 1625 struct radeon_crtc *radeon_crtc; 1626 1627 if (rdev->pm.num_power_states < 2) 1628 return; 1629 1630 mutex_lock(&rdev->pm.mutex); 1631 1632 rdev->pm.active_crtcs = 0; 1633 rdev->pm.active_crtc_count = 0; 1634 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1635 list_for_each_entry(crtc, 1636 &ddev->mode_config.crtc_list, head) { 1637 radeon_crtc = to_radeon_crtc(crtc); 1638 if (radeon_crtc->enabled) { 1639 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1640 rdev->pm.active_crtc_count++; 1641 } 1642 } 1643 } 1644 1645 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1646 radeon_pm_update_profile(rdev); 1647 radeon_pm_set_clocks(rdev); 1648 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1649 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1650 if (rdev->pm.active_crtc_count > 1) { 1651 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1652 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1653 1654 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1655 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1656 radeon_pm_get_dynpm_state(rdev); 1657 radeon_pm_set_clocks(rdev); 1658 1659 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1660 } 1661 } else if (rdev->pm.active_crtc_count == 1) { 1662 /* TODO: Increase clocks if needed for current mode */ 1663 1664 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1665 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1666 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1667 radeon_pm_get_dynpm_state(rdev); 1668 radeon_pm_set_clocks(rdev); 1669 1670 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1671 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1672 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1673 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1674 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1675 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1676 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1677 } 1678 } else { /* count == 0 */ 1679 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1680 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1681 1682 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1683 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1684 radeon_pm_get_dynpm_state(rdev); 1685 radeon_pm_set_clocks(rdev); 1686 } 1687 } 1688 } 1689 } 1690 1691 mutex_unlock(&rdev->pm.mutex); 1692 } 1693 1694 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1695 { 1696 struct drm_device *ddev = rdev->ddev; 1697 struct drm_crtc *crtc; 1698 struct radeon_crtc *radeon_crtc; 1699 1700 if (!rdev->pm.dpm_enabled) 1701 return; 1702 1703 mutex_lock(&rdev->pm.mutex); 1704 1705 /* update active crtc counts */ 1706 rdev->pm.dpm.new_active_crtcs = 0; 1707 rdev->pm.dpm.new_active_crtc_count = 0; 1708 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1709 list_for_each_entry(crtc, 1710 &ddev->mode_config.crtc_list, head) { 1711 radeon_crtc = to_radeon_crtc(crtc); 1712 if (crtc->enabled) { 1713 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1714 rdev->pm.dpm.new_active_crtc_count++; 1715 } 1716 } 1717 } 1718 1719 /* update battery/ac status */ 1720 if (power_supply_is_system_supplied() > 0) 1721 rdev->pm.dpm.ac_power = true; 1722 else 1723 rdev->pm.dpm.ac_power = false; 1724 1725 radeon_dpm_change_power_state_locked(rdev); 1726 1727 mutex_unlock(&rdev->pm.mutex); 1728 1729 } 1730 1731 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1732 { 1733 if (rdev->pm.pm_method == PM_METHOD_DPM) 1734 radeon_pm_compute_clocks_dpm(rdev); 1735 else 1736 radeon_pm_compute_clocks_old(rdev); 1737 } 1738 1739 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1740 { 1741 int crtc, vpos, hpos, vbl_status; 1742 bool in_vbl = true; 1743 1744 /* Iterate over all active crtc's. All crtc's must be in vblank, 1745 * otherwise return in_vbl == false. 1746 */ 1747 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1748 if (rdev->pm.active_crtcs & (1 << crtc)) { 1749 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, 1750 &vpos, &hpos, NULL, NULL, 1751 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1752 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1753 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1754 in_vbl = false; 1755 } 1756 } 1757 1758 return in_vbl; 1759 } 1760 1761 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1762 { 1763 u32 stat_crtc = 0; 1764 bool in_vbl = radeon_pm_in_vbl(rdev); 1765 1766 if (in_vbl == false) 1767 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1768 finish ? "exit" : "entry"); 1769 return in_vbl; 1770 } 1771 1772 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1773 { 1774 struct radeon_device *rdev; 1775 int resched; 1776 rdev = container_of(work, struct radeon_device, 1777 pm.dynpm_idle_work.work); 1778 1779 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1780 mutex_lock(&rdev->pm.mutex); 1781 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1782 int not_processed = 0; 1783 int i; 1784 1785 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1786 struct radeon_ring *ring = &rdev->ring[i]; 1787 1788 if (ring->ready) { 1789 not_processed += radeon_fence_count_emitted(rdev, i); 1790 if (not_processed >= 3) 1791 break; 1792 } 1793 } 1794 1795 if (not_processed >= 3) { /* should upclock */ 1796 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1797 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1798 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1799 rdev->pm.dynpm_can_upclock) { 1800 rdev->pm.dynpm_planned_action = 1801 DYNPM_ACTION_UPCLOCK; 1802 rdev->pm.dynpm_action_timeout = jiffies + 1803 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1804 } 1805 } else if (not_processed == 0) { /* should downclock */ 1806 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1807 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1808 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1809 rdev->pm.dynpm_can_downclock) { 1810 rdev->pm.dynpm_planned_action = 1811 DYNPM_ACTION_DOWNCLOCK; 1812 rdev->pm.dynpm_action_timeout = jiffies + 1813 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1814 } 1815 } 1816 1817 /* Note, radeon_pm_set_clocks is called with static_switch set 1818 * to false since we want to wait for vbl to avoid flicker. 1819 */ 1820 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1821 jiffies > rdev->pm.dynpm_action_timeout) { 1822 radeon_pm_get_dynpm_state(rdev); 1823 radeon_pm_set_clocks(rdev); 1824 } 1825 1826 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1827 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1828 } 1829 mutex_unlock(&rdev->pm.mutex); 1830 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1831 } 1832 1833 /* 1834 * Debugfs info 1835 */ 1836 #if defined(CONFIG_DEBUG_FS) 1837 1838 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1839 { 1840 struct drm_info_node *node = (struct drm_info_node *) m->private; 1841 struct drm_device *dev = node->minor->dev; 1842 struct radeon_device *rdev = dev->dev_private; 1843 struct drm_device *ddev = rdev->ddev; 1844 1845 if ((rdev->flags & RADEON_IS_PX) && 1846 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1847 seq_printf(m, "PX asic powered off\n"); 1848 } else if (rdev->pm.dpm_enabled) { 1849 mutex_lock(&rdev->pm.mutex); 1850 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1851 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1852 else 1853 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1854 mutex_unlock(&rdev->pm.mutex); 1855 } else { 1856 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1857 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1858 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1859 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1860 else 1861 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1862 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1863 if (rdev->asic->pm.get_memory_clock) 1864 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1865 if (rdev->pm.current_vddc) 1866 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1867 if (rdev->asic->pm.get_pcie_lanes) 1868 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1869 } 1870 1871 return 0; 1872 } 1873 1874 static struct drm_info_list radeon_pm_info_list[] = { 1875 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1876 }; 1877 #endif 1878 1879 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1880 { 1881 #if defined(CONFIG_DEBUG_FS) 1882 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1883 #else 1884 return 0; 1885 #endif 1886 } 1887