1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include "radeon_drm.h" 36 #include "radeon.h" 37 #include "radeon_trace.h" 38 39 40 int radeon_ttm_init(struct radeon_device *rdev); 41 void radeon_ttm_fini(struct radeon_device *rdev); 42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 43 44 /* 45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 46 * function are calling it. 47 */ 48 49 void radeon_bo_clear_va(struct radeon_bo *bo) 50 { 51 struct radeon_bo_va *bo_va, *tmp; 52 53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 54 /* remove from all vm address space */ 55 mutex_lock(&bo_va->vm->mutex); 56 list_del(&bo_va->vm_list); 57 mutex_unlock(&bo_va->vm->mutex); 58 list_del(&bo_va->bo_list); 59 kfree(bo_va); 60 } 61 } 62 63 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 64 { 65 struct radeon_bo *bo; 66 67 bo = container_of(tbo, struct radeon_bo, tbo); 68 mutex_lock(&bo->rdev->gem.mutex); 69 list_del_init(&bo->list); 70 mutex_unlock(&bo->rdev->gem.mutex); 71 radeon_bo_clear_surface_reg(bo); 72 radeon_bo_clear_va(bo); 73 drm_gem_object_release(&bo->gem_base); 74 kfree(bo); 75 } 76 77 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 78 { 79 if (bo->destroy == &radeon_ttm_bo_destroy) 80 return true; 81 return false; 82 } 83 84 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 85 { 86 u32 c = 0; 87 88 rbo->placement.fpfn = 0; 89 rbo->placement.lpfn = 0; 90 rbo->placement.placement = rbo->placements; 91 rbo->placement.busy_placement = rbo->placements; 92 if (domain & RADEON_GEM_DOMAIN_VRAM) 93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 94 TTM_PL_FLAG_VRAM; 95 if (domain & RADEON_GEM_DOMAIN_GTT) 96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 97 if (domain & RADEON_GEM_DOMAIN_CPU) 98 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 99 if (!c) 100 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 101 rbo->placement.num_placement = c; 102 rbo->placement.num_busy_placement = c; 103 } 104 105 int radeon_bo_create(struct radeon_device *rdev, 106 unsigned long size, int byte_align, bool kernel, u32 domain, 107 struct radeon_bo **bo_ptr) 108 { 109 struct radeon_bo *bo; 110 enum ttm_bo_type type; 111 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 112 unsigned long max_size = 0; 113 size_t acc_size; 114 int r; 115 116 size = ALIGN(size, PAGE_SIZE); 117 118 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { 119 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 120 } 121 if (kernel) { 122 type = ttm_bo_type_kernel; 123 } else { 124 type = ttm_bo_type_device; 125 } 126 *bo_ptr = NULL; 127 128 /* maximun bo size is the minimun btw visible vram and gtt size */ 129 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size); 130 if ((page_align << PAGE_SHIFT) >= max_size) { 131 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n", 132 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20); 133 return -ENOMEM; 134 } 135 136 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 137 sizeof(struct radeon_bo)); 138 139 retry: 140 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 141 if (bo == NULL) 142 return -ENOMEM; 143 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 144 if (unlikely(r)) { 145 kfree(bo); 146 return r; 147 } 148 bo->rdev = rdev; 149 bo->gem_base.driver_private = NULL; 150 bo->surface_reg = -1; 151 INIT_LIST_HEAD(&bo->list); 152 INIT_LIST_HEAD(&bo->va); 153 radeon_ttm_placement_from_domain(bo, domain); 154 /* Kernel allocation are uninterruptible */ 155 mutex_lock(&rdev->vram_mutex); 156 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 157 &bo->placement, page_align, 0, !kernel, NULL, 158 acc_size, &radeon_ttm_bo_destroy); 159 mutex_unlock(&rdev->vram_mutex); 160 if (unlikely(r != 0)) { 161 if (r != -ERESTARTSYS) { 162 if (domain == RADEON_GEM_DOMAIN_VRAM) { 163 domain |= RADEON_GEM_DOMAIN_GTT; 164 goto retry; 165 } 166 dev_err(rdev->dev, 167 "object_init failed for (%lu, 0x%08X)\n", 168 size, domain); 169 } 170 return r; 171 } 172 *bo_ptr = bo; 173 174 trace_radeon_bo_create(bo); 175 176 return 0; 177 } 178 179 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 180 { 181 bool is_iomem; 182 int r; 183 184 if (bo->kptr) { 185 if (ptr) { 186 *ptr = bo->kptr; 187 } 188 return 0; 189 } 190 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 191 if (r) { 192 return r; 193 } 194 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 195 if (ptr) { 196 *ptr = bo->kptr; 197 } 198 radeon_bo_check_tiling(bo, 0, 0); 199 return 0; 200 } 201 202 void radeon_bo_kunmap(struct radeon_bo *bo) 203 { 204 if (bo->kptr == NULL) 205 return; 206 bo->kptr = NULL; 207 radeon_bo_check_tiling(bo, 0, 0); 208 ttm_bo_kunmap(&bo->kmap); 209 } 210 211 void radeon_bo_unref(struct radeon_bo **bo) 212 { 213 struct ttm_buffer_object *tbo; 214 struct radeon_device *rdev; 215 216 if ((*bo) == NULL) 217 return; 218 rdev = (*bo)->rdev; 219 tbo = &((*bo)->tbo); 220 mutex_lock(&rdev->vram_mutex); 221 ttm_bo_unref(&tbo); 222 mutex_unlock(&rdev->vram_mutex); 223 if (tbo == NULL) 224 *bo = NULL; 225 } 226 227 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 228 u64 *gpu_addr) 229 { 230 int r, i; 231 232 if (bo->pin_count) { 233 bo->pin_count++; 234 if (gpu_addr) 235 *gpu_addr = radeon_bo_gpu_offset(bo); 236 WARN_ON_ONCE(max_offset != 0); 237 return 0; 238 } 239 radeon_ttm_placement_from_domain(bo, domain); 240 if (domain == RADEON_GEM_DOMAIN_VRAM) { 241 /* force to pin into visible video ram */ 242 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 243 } 244 if (max_offset) { 245 u64 lpfn = max_offset >> PAGE_SHIFT; 246 247 if (!bo->placement.lpfn) 248 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 249 250 if (lpfn < bo->placement.lpfn) 251 bo->placement.lpfn = lpfn; 252 } 253 for (i = 0; i < bo->placement.num_placement; i++) 254 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 255 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 256 if (likely(r == 0)) { 257 bo->pin_count = 1; 258 if (gpu_addr != NULL) 259 *gpu_addr = radeon_bo_gpu_offset(bo); 260 } 261 if (unlikely(r != 0)) 262 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 263 return r; 264 } 265 266 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 267 { 268 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 269 } 270 271 int radeon_bo_unpin(struct radeon_bo *bo) 272 { 273 int r, i; 274 275 if (!bo->pin_count) { 276 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 277 return 0; 278 } 279 bo->pin_count--; 280 if (bo->pin_count) 281 return 0; 282 for (i = 0; i < bo->placement.num_placement; i++) 283 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 284 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 285 if (unlikely(r != 0)) 286 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 287 return r; 288 } 289 290 int radeon_bo_evict_vram(struct radeon_device *rdev) 291 { 292 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 293 if (0 && (rdev->flags & RADEON_IS_IGP)) { 294 if (rdev->mc.igp_sideport_enabled == false) 295 /* Useless to evict on IGP chips */ 296 return 0; 297 } 298 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 299 } 300 301 void radeon_bo_force_delete(struct radeon_device *rdev) 302 { 303 struct radeon_bo *bo, *n; 304 305 if (list_empty(&rdev->gem.objects)) { 306 return; 307 } 308 dev_err(rdev->dev, "Userspace still has active objects !\n"); 309 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 310 mutex_lock(&rdev->ddev->struct_mutex); 311 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 312 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 313 *((unsigned long *)&bo->gem_base.refcount)); 314 mutex_lock(&bo->rdev->gem.mutex); 315 list_del_init(&bo->list); 316 mutex_unlock(&bo->rdev->gem.mutex); 317 /* this should unref the ttm bo */ 318 drm_gem_object_unreference(&bo->gem_base); 319 mutex_unlock(&rdev->ddev->struct_mutex); 320 } 321 } 322 323 int radeon_bo_init(struct radeon_device *rdev) 324 { 325 /* Add an MTRR for the VRAM */ 326 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 327 MTRR_TYPE_WRCOMB, 1); 328 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 329 rdev->mc.mc_vram_size >> 20, 330 (unsigned long long)rdev->mc.aper_size >> 20); 331 DRM_INFO("RAM width %dbits %cDR\n", 332 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 333 return radeon_ttm_init(rdev); 334 } 335 336 void radeon_bo_fini(struct radeon_device *rdev) 337 { 338 radeon_ttm_fini(rdev); 339 } 340 341 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 342 struct list_head *head) 343 { 344 if (lobj->wdomain) { 345 list_add(&lobj->tv.head, head); 346 } else { 347 list_add_tail(&lobj->tv.head, head); 348 } 349 } 350 351 int radeon_bo_list_validate(struct list_head *head) 352 { 353 struct radeon_bo_list *lobj; 354 struct radeon_bo *bo; 355 u32 domain; 356 int r; 357 358 r = ttm_eu_reserve_buffers(head); 359 if (unlikely(r != 0)) { 360 return r; 361 } 362 list_for_each_entry(lobj, head, tv.head) { 363 bo = lobj->bo; 364 if (!bo->pin_count) { 365 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 366 367 retry: 368 radeon_ttm_placement_from_domain(bo, domain); 369 r = ttm_bo_validate(&bo->tbo, &bo->placement, 370 true, false, false); 371 if (unlikely(r)) { 372 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 373 domain |= RADEON_GEM_DOMAIN_GTT; 374 goto retry; 375 } 376 return r; 377 } 378 } 379 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 380 lobj->tiling_flags = bo->tiling_flags; 381 } 382 return 0; 383 } 384 385 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 386 struct vm_area_struct *vma) 387 { 388 return ttm_fbdev_mmap(vma, &bo->tbo); 389 } 390 391 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 392 { 393 struct radeon_device *rdev = bo->rdev; 394 struct radeon_surface_reg *reg; 395 struct radeon_bo *old_object; 396 int steal; 397 int i; 398 399 BUG_ON(!atomic_read(&bo->tbo.reserved)); 400 401 if (!bo->tiling_flags) 402 return 0; 403 404 if (bo->surface_reg >= 0) { 405 reg = &rdev->surface_regs[bo->surface_reg]; 406 i = bo->surface_reg; 407 goto out; 408 } 409 410 steal = -1; 411 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 412 413 reg = &rdev->surface_regs[i]; 414 if (!reg->bo) 415 break; 416 417 old_object = reg->bo; 418 if (old_object->pin_count == 0) 419 steal = i; 420 } 421 422 /* if we are all out */ 423 if (i == RADEON_GEM_MAX_SURFACES) { 424 if (steal == -1) 425 return -ENOMEM; 426 /* find someone with a surface reg and nuke their BO */ 427 reg = &rdev->surface_regs[steal]; 428 old_object = reg->bo; 429 /* blow away the mapping */ 430 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 431 ttm_bo_unmap_virtual(&old_object->tbo); 432 old_object->surface_reg = -1; 433 i = steal; 434 } 435 436 bo->surface_reg = i; 437 reg->bo = bo; 438 439 out: 440 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 441 bo->tbo.mem.start << PAGE_SHIFT, 442 bo->tbo.num_pages << PAGE_SHIFT); 443 return 0; 444 } 445 446 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 447 { 448 struct radeon_device *rdev = bo->rdev; 449 struct radeon_surface_reg *reg; 450 451 if (bo->surface_reg == -1) 452 return; 453 454 reg = &rdev->surface_regs[bo->surface_reg]; 455 radeon_clear_surface_reg(rdev, bo->surface_reg); 456 457 reg->bo = NULL; 458 bo->surface_reg = -1; 459 } 460 461 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 462 uint32_t tiling_flags, uint32_t pitch) 463 { 464 struct radeon_device *rdev = bo->rdev; 465 int r; 466 467 if (rdev->family >= CHIP_CEDAR) { 468 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 469 470 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 471 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 472 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 473 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 474 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 475 switch (bankw) { 476 case 0: 477 case 1: 478 case 2: 479 case 4: 480 case 8: 481 break; 482 default: 483 return -EINVAL; 484 } 485 switch (bankh) { 486 case 0: 487 case 1: 488 case 2: 489 case 4: 490 case 8: 491 break; 492 default: 493 return -EINVAL; 494 } 495 switch (mtaspect) { 496 case 0: 497 case 1: 498 case 2: 499 case 4: 500 case 8: 501 break; 502 default: 503 return -EINVAL; 504 } 505 if (tilesplit > 6) { 506 return -EINVAL; 507 } 508 if (stilesplit > 6) { 509 return -EINVAL; 510 } 511 } 512 r = radeon_bo_reserve(bo, false); 513 if (unlikely(r != 0)) 514 return r; 515 bo->tiling_flags = tiling_flags; 516 bo->pitch = pitch; 517 radeon_bo_unreserve(bo); 518 return 0; 519 } 520 521 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 522 uint32_t *tiling_flags, 523 uint32_t *pitch) 524 { 525 BUG_ON(!atomic_read(&bo->tbo.reserved)); 526 if (tiling_flags) 527 *tiling_flags = bo->tiling_flags; 528 if (pitch) 529 *pitch = bo->pitch; 530 } 531 532 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 533 bool force_drop) 534 { 535 BUG_ON(!atomic_read(&bo->tbo.reserved)); 536 537 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 538 return 0; 539 540 if (force_drop) { 541 radeon_bo_clear_surface_reg(bo); 542 return 0; 543 } 544 545 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 546 if (!has_moved) 547 return 0; 548 549 if (bo->surface_reg >= 0) 550 radeon_bo_clear_surface_reg(bo); 551 return 0; 552 } 553 554 if ((bo->surface_reg >= 0) && !has_moved) 555 return 0; 556 557 return radeon_bo_get_surface_reg(bo); 558 } 559 560 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 561 struct ttm_mem_reg *mem) 562 { 563 struct radeon_bo *rbo; 564 if (!radeon_ttm_bo_is_radeon_bo(bo)) 565 return; 566 rbo = container_of(bo, struct radeon_bo, tbo); 567 radeon_bo_check_tiling(rbo, 0, 1); 568 radeon_vm_bo_invalidate(rbo->rdev, rbo); 569 } 570 571 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 572 { 573 struct radeon_device *rdev; 574 struct radeon_bo *rbo; 575 unsigned long offset, size; 576 int r; 577 578 if (!radeon_ttm_bo_is_radeon_bo(bo)) 579 return 0; 580 rbo = container_of(bo, struct radeon_bo, tbo); 581 radeon_bo_check_tiling(rbo, 0, 0); 582 rdev = rbo->rdev; 583 if (bo->mem.mem_type == TTM_PL_VRAM) { 584 size = bo->mem.num_pages << PAGE_SHIFT; 585 offset = bo->mem.start << PAGE_SHIFT; 586 if ((offset + size) > rdev->mc.visible_vram_size) { 587 /* hurrah the memory is not visible ! */ 588 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 589 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 590 r = ttm_bo_validate(bo, &rbo->placement, false, true, false); 591 if (unlikely(r != 0)) 592 return r; 593 offset = bo->mem.start << PAGE_SHIFT; 594 /* this should not happen */ 595 if ((offset + size) > rdev->mc.visible_vram_size) 596 return -EINVAL; 597 } 598 } 599 return 0; 600 } 601 602 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 603 { 604 int r; 605 606 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 607 if (unlikely(r != 0)) 608 return r; 609 spin_lock(&bo->tbo.bdev->fence_lock); 610 if (mem_type) 611 *mem_type = bo->tbo.mem.mem_type; 612 if (bo->tbo.sync_obj) 613 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 614 spin_unlock(&bo->tbo.bdev->fence_lock); 615 ttm_bo_unreserve(&bo->tbo); 616 return r; 617 } 618 619 620 /** 621 * radeon_bo_reserve - reserve bo 622 * @bo: bo structure 623 * @no_wait: don't sleep while trying to reserve (return -EBUSY) 624 * 625 * Returns: 626 * -EBUSY: buffer is busy and @no_wait is true 627 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 628 * a signal. Release all buffer reservations and return to user-space. 629 */ 630 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) 631 { 632 int r; 633 634 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 635 if (unlikely(r != 0)) { 636 if (r != -ERESTARTSYS) 637 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 638 return r; 639 } 640 return 0; 641 } 642 643 /* object have to be reserved */ 644 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm) 645 { 646 struct radeon_bo_va *bo_va; 647 648 list_for_each_entry(bo_va, &rbo->va, bo_list) { 649 if (bo_va->vm == vm) { 650 return bo_va; 651 } 652 } 653 return NULL; 654 } 655