1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include "radeon_drm.h" 36 #include "radeon.h" 37 #include "radeon_trace.h" 38 39 40 int radeon_ttm_init(struct radeon_device *rdev); 41 void radeon_ttm_fini(struct radeon_device *rdev); 42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 43 44 /* 45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 46 * function are calling it. 47 */ 48 49 void radeon_bo_clear_va(struct radeon_bo *bo) 50 { 51 struct radeon_bo_va *bo_va, *tmp; 52 53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 54 /* remove from all vm address space */ 55 mutex_lock(&bo_va->vm->mutex); 56 list_del(&bo_va->vm_list); 57 mutex_unlock(&bo_va->vm->mutex); 58 list_del(&bo_va->bo_list); 59 kfree(bo_va); 60 } 61 } 62 63 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 64 { 65 struct radeon_bo *bo; 66 67 bo = container_of(tbo, struct radeon_bo, tbo); 68 mutex_lock(&bo->rdev->gem.mutex); 69 list_del_init(&bo->list); 70 mutex_unlock(&bo->rdev->gem.mutex); 71 radeon_bo_clear_surface_reg(bo); 72 radeon_bo_clear_va(bo); 73 drm_gem_object_release(&bo->gem_base); 74 kfree(bo); 75 } 76 77 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 78 { 79 if (bo->destroy == &radeon_ttm_bo_destroy) 80 return true; 81 return false; 82 } 83 84 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 85 { 86 u32 c = 0; 87 88 rbo->placement.fpfn = 0; 89 rbo->placement.lpfn = 0; 90 rbo->placement.placement = rbo->placements; 91 rbo->placement.busy_placement = rbo->placements; 92 if (domain & RADEON_GEM_DOMAIN_VRAM) 93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 94 TTM_PL_FLAG_VRAM; 95 if (domain & RADEON_GEM_DOMAIN_GTT) 96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 97 if (domain & RADEON_GEM_DOMAIN_CPU) 98 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 99 if (!c) 100 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 101 rbo->placement.num_placement = c; 102 rbo->placement.num_busy_placement = c; 103 } 104 105 int radeon_bo_create(struct radeon_device *rdev, 106 unsigned long size, int byte_align, bool kernel, u32 domain, 107 struct sg_table *sg, struct radeon_bo **bo_ptr) 108 { 109 struct radeon_bo *bo; 110 enum ttm_bo_type type; 111 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 112 unsigned long max_size = 0; 113 size_t acc_size; 114 int r; 115 116 size = ALIGN(size, PAGE_SIZE); 117 118 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 119 if (kernel) { 120 type = ttm_bo_type_kernel; 121 } else if (sg) { 122 type = ttm_bo_type_sg; 123 } else { 124 type = ttm_bo_type_device; 125 } 126 *bo_ptr = NULL; 127 128 /* maximun bo size is the minimun btw visible vram and gtt size */ 129 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size); 130 if ((page_align << PAGE_SHIFT) >= max_size) { 131 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n", 132 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20); 133 return -ENOMEM; 134 } 135 136 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 137 sizeof(struct radeon_bo)); 138 139 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 140 if (bo == NULL) 141 return -ENOMEM; 142 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 143 if (unlikely(r)) { 144 kfree(bo); 145 return r; 146 } 147 bo->rdev = rdev; 148 bo->gem_base.driver_private = NULL; 149 bo->surface_reg = -1; 150 INIT_LIST_HEAD(&bo->list); 151 INIT_LIST_HEAD(&bo->va); 152 153 retry: 154 radeon_ttm_placement_from_domain(bo, domain); 155 /* Kernel allocation are uninterruptible */ 156 down_read(&rdev->pm.mclk_lock); 157 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 158 &bo->placement, page_align, 0, !kernel, NULL, 159 acc_size, sg, &radeon_ttm_bo_destroy); 160 up_read(&rdev->pm.mclk_lock); 161 if (unlikely(r != 0)) { 162 if (r != -ERESTARTSYS) { 163 if (domain == RADEON_GEM_DOMAIN_VRAM) { 164 domain |= RADEON_GEM_DOMAIN_GTT; 165 goto retry; 166 } 167 dev_err(rdev->dev, 168 "object_init failed for (%lu, 0x%08X)\n", 169 size, domain); 170 } 171 return r; 172 } 173 *bo_ptr = bo; 174 175 trace_radeon_bo_create(bo); 176 177 return 0; 178 } 179 180 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 181 { 182 bool is_iomem; 183 int r; 184 185 if (bo->kptr) { 186 if (ptr) { 187 *ptr = bo->kptr; 188 } 189 return 0; 190 } 191 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 192 if (r) { 193 return r; 194 } 195 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 196 if (ptr) { 197 *ptr = bo->kptr; 198 } 199 radeon_bo_check_tiling(bo, 0, 0); 200 return 0; 201 } 202 203 void radeon_bo_kunmap(struct radeon_bo *bo) 204 { 205 if (bo->kptr == NULL) 206 return; 207 bo->kptr = NULL; 208 radeon_bo_check_tiling(bo, 0, 0); 209 ttm_bo_kunmap(&bo->kmap); 210 } 211 212 void radeon_bo_unref(struct radeon_bo **bo) 213 { 214 struct ttm_buffer_object *tbo; 215 struct radeon_device *rdev; 216 217 if ((*bo) == NULL) 218 return; 219 rdev = (*bo)->rdev; 220 tbo = &((*bo)->tbo); 221 down_read(&rdev->pm.mclk_lock); 222 ttm_bo_unref(&tbo); 223 up_read(&rdev->pm.mclk_lock); 224 if (tbo == NULL) 225 *bo = NULL; 226 } 227 228 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 229 u64 *gpu_addr) 230 { 231 int r, i; 232 233 if (bo->pin_count) { 234 bo->pin_count++; 235 if (gpu_addr) 236 *gpu_addr = radeon_bo_gpu_offset(bo); 237 238 if (max_offset != 0) { 239 u64 domain_start; 240 241 if (domain == RADEON_GEM_DOMAIN_VRAM) 242 domain_start = bo->rdev->mc.vram_start; 243 else 244 domain_start = bo->rdev->mc.gtt_start; 245 WARN_ON_ONCE(max_offset < 246 (radeon_bo_gpu_offset(bo) - domain_start)); 247 } 248 249 return 0; 250 } 251 radeon_ttm_placement_from_domain(bo, domain); 252 if (domain == RADEON_GEM_DOMAIN_VRAM) { 253 /* force to pin into visible video ram */ 254 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 255 } 256 if (max_offset) { 257 u64 lpfn = max_offset >> PAGE_SHIFT; 258 259 if (!bo->placement.lpfn) 260 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 261 262 if (lpfn < bo->placement.lpfn) 263 bo->placement.lpfn = lpfn; 264 } 265 for (i = 0; i < bo->placement.num_placement; i++) 266 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 267 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 268 if (likely(r == 0)) { 269 bo->pin_count = 1; 270 if (gpu_addr != NULL) 271 *gpu_addr = radeon_bo_gpu_offset(bo); 272 } 273 if (unlikely(r != 0)) 274 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 275 return r; 276 } 277 278 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 279 { 280 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 281 } 282 283 int radeon_bo_unpin(struct radeon_bo *bo) 284 { 285 int r, i; 286 287 if (!bo->pin_count) { 288 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 289 return 0; 290 } 291 bo->pin_count--; 292 if (bo->pin_count) 293 return 0; 294 for (i = 0; i < bo->placement.num_placement; i++) 295 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 296 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 297 if (unlikely(r != 0)) 298 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 299 return r; 300 } 301 302 int radeon_bo_evict_vram(struct radeon_device *rdev) 303 { 304 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 305 if (0 && (rdev->flags & RADEON_IS_IGP)) { 306 if (rdev->mc.igp_sideport_enabled == false) 307 /* Useless to evict on IGP chips */ 308 return 0; 309 } 310 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 311 } 312 313 void radeon_bo_force_delete(struct radeon_device *rdev) 314 { 315 struct radeon_bo *bo, *n; 316 317 if (list_empty(&rdev->gem.objects)) { 318 return; 319 } 320 dev_err(rdev->dev, "Userspace still has active objects !\n"); 321 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 322 mutex_lock(&rdev->ddev->struct_mutex); 323 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 324 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 325 *((unsigned long *)&bo->gem_base.refcount)); 326 mutex_lock(&bo->rdev->gem.mutex); 327 list_del_init(&bo->list); 328 mutex_unlock(&bo->rdev->gem.mutex); 329 /* this should unref the ttm bo */ 330 drm_gem_object_unreference(&bo->gem_base); 331 mutex_unlock(&rdev->ddev->struct_mutex); 332 } 333 } 334 335 int radeon_bo_init(struct radeon_device *rdev) 336 { 337 /* Add an MTRR for the VRAM */ 338 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 339 MTRR_TYPE_WRCOMB, 1); 340 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 341 rdev->mc.mc_vram_size >> 20, 342 (unsigned long long)rdev->mc.aper_size >> 20); 343 DRM_INFO("RAM width %dbits %cDR\n", 344 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 345 return radeon_ttm_init(rdev); 346 } 347 348 void radeon_bo_fini(struct radeon_device *rdev) 349 { 350 radeon_ttm_fini(rdev); 351 } 352 353 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 354 struct list_head *head) 355 { 356 if (lobj->wdomain) { 357 list_add(&lobj->tv.head, head); 358 } else { 359 list_add_tail(&lobj->tv.head, head); 360 } 361 } 362 363 int radeon_bo_list_validate(struct list_head *head) 364 { 365 struct radeon_bo_list *lobj; 366 struct radeon_bo *bo; 367 u32 domain; 368 int r; 369 370 r = ttm_eu_reserve_buffers(head); 371 if (unlikely(r != 0)) { 372 return r; 373 } 374 list_for_each_entry(lobj, head, tv.head) { 375 bo = lobj->bo; 376 if (!bo->pin_count) { 377 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 378 379 retry: 380 radeon_ttm_placement_from_domain(bo, domain); 381 r = ttm_bo_validate(&bo->tbo, &bo->placement, 382 true, false, false); 383 if (unlikely(r)) { 384 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 385 domain |= RADEON_GEM_DOMAIN_GTT; 386 goto retry; 387 } 388 return r; 389 } 390 } 391 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 392 lobj->tiling_flags = bo->tiling_flags; 393 } 394 return 0; 395 } 396 397 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 398 struct vm_area_struct *vma) 399 { 400 return ttm_fbdev_mmap(vma, &bo->tbo); 401 } 402 403 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 404 { 405 struct radeon_device *rdev = bo->rdev; 406 struct radeon_surface_reg *reg; 407 struct radeon_bo *old_object; 408 int steal; 409 int i; 410 411 BUG_ON(!atomic_read(&bo->tbo.reserved)); 412 413 if (!bo->tiling_flags) 414 return 0; 415 416 if (bo->surface_reg >= 0) { 417 reg = &rdev->surface_regs[bo->surface_reg]; 418 i = bo->surface_reg; 419 goto out; 420 } 421 422 steal = -1; 423 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 424 425 reg = &rdev->surface_regs[i]; 426 if (!reg->bo) 427 break; 428 429 old_object = reg->bo; 430 if (old_object->pin_count == 0) 431 steal = i; 432 } 433 434 /* if we are all out */ 435 if (i == RADEON_GEM_MAX_SURFACES) { 436 if (steal == -1) 437 return -ENOMEM; 438 /* find someone with a surface reg and nuke their BO */ 439 reg = &rdev->surface_regs[steal]; 440 old_object = reg->bo; 441 /* blow away the mapping */ 442 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 443 ttm_bo_unmap_virtual(&old_object->tbo); 444 old_object->surface_reg = -1; 445 i = steal; 446 } 447 448 bo->surface_reg = i; 449 reg->bo = bo; 450 451 out: 452 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 453 bo->tbo.mem.start << PAGE_SHIFT, 454 bo->tbo.num_pages << PAGE_SHIFT); 455 return 0; 456 } 457 458 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 459 { 460 struct radeon_device *rdev = bo->rdev; 461 struct radeon_surface_reg *reg; 462 463 if (bo->surface_reg == -1) 464 return; 465 466 reg = &rdev->surface_regs[bo->surface_reg]; 467 radeon_clear_surface_reg(rdev, bo->surface_reg); 468 469 reg->bo = NULL; 470 bo->surface_reg = -1; 471 } 472 473 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 474 uint32_t tiling_flags, uint32_t pitch) 475 { 476 struct radeon_device *rdev = bo->rdev; 477 int r; 478 479 if (rdev->family >= CHIP_CEDAR) { 480 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 481 482 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 483 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 484 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 485 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 486 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 487 switch (bankw) { 488 case 0: 489 case 1: 490 case 2: 491 case 4: 492 case 8: 493 break; 494 default: 495 return -EINVAL; 496 } 497 switch (bankh) { 498 case 0: 499 case 1: 500 case 2: 501 case 4: 502 case 8: 503 break; 504 default: 505 return -EINVAL; 506 } 507 switch (mtaspect) { 508 case 0: 509 case 1: 510 case 2: 511 case 4: 512 case 8: 513 break; 514 default: 515 return -EINVAL; 516 } 517 if (tilesplit > 6) { 518 return -EINVAL; 519 } 520 if (stilesplit > 6) { 521 return -EINVAL; 522 } 523 } 524 r = radeon_bo_reserve(bo, false); 525 if (unlikely(r != 0)) 526 return r; 527 bo->tiling_flags = tiling_flags; 528 bo->pitch = pitch; 529 radeon_bo_unreserve(bo); 530 return 0; 531 } 532 533 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 534 uint32_t *tiling_flags, 535 uint32_t *pitch) 536 { 537 BUG_ON(!atomic_read(&bo->tbo.reserved)); 538 if (tiling_flags) 539 *tiling_flags = bo->tiling_flags; 540 if (pitch) 541 *pitch = bo->pitch; 542 } 543 544 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 545 bool force_drop) 546 { 547 BUG_ON(!atomic_read(&bo->tbo.reserved)); 548 549 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 550 return 0; 551 552 if (force_drop) { 553 radeon_bo_clear_surface_reg(bo); 554 return 0; 555 } 556 557 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 558 if (!has_moved) 559 return 0; 560 561 if (bo->surface_reg >= 0) 562 radeon_bo_clear_surface_reg(bo); 563 return 0; 564 } 565 566 if ((bo->surface_reg >= 0) && !has_moved) 567 return 0; 568 569 return radeon_bo_get_surface_reg(bo); 570 } 571 572 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 573 struct ttm_mem_reg *mem) 574 { 575 struct radeon_bo *rbo; 576 if (!radeon_ttm_bo_is_radeon_bo(bo)) 577 return; 578 rbo = container_of(bo, struct radeon_bo, tbo); 579 radeon_bo_check_tiling(rbo, 0, 1); 580 radeon_vm_bo_invalidate(rbo->rdev, rbo); 581 } 582 583 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 584 { 585 struct radeon_device *rdev; 586 struct radeon_bo *rbo; 587 unsigned long offset, size; 588 int r; 589 590 if (!radeon_ttm_bo_is_radeon_bo(bo)) 591 return 0; 592 rbo = container_of(bo, struct radeon_bo, tbo); 593 radeon_bo_check_tiling(rbo, 0, 0); 594 rdev = rbo->rdev; 595 if (bo->mem.mem_type == TTM_PL_VRAM) { 596 size = bo->mem.num_pages << PAGE_SHIFT; 597 offset = bo->mem.start << PAGE_SHIFT; 598 if ((offset + size) > rdev->mc.visible_vram_size) { 599 /* hurrah the memory is not visible ! */ 600 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 601 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 602 r = ttm_bo_validate(bo, &rbo->placement, false, true, false); 603 if (unlikely(r != 0)) 604 return r; 605 offset = bo->mem.start << PAGE_SHIFT; 606 /* this should not happen */ 607 if ((offset + size) > rdev->mc.visible_vram_size) 608 return -EINVAL; 609 } 610 } 611 return 0; 612 } 613 614 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 615 { 616 int r; 617 618 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 619 if (unlikely(r != 0)) 620 return r; 621 spin_lock(&bo->tbo.bdev->fence_lock); 622 if (mem_type) 623 *mem_type = bo->tbo.mem.mem_type; 624 if (bo->tbo.sync_obj) 625 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 626 spin_unlock(&bo->tbo.bdev->fence_lock); 627 ttm_bo_unreserve(&bo->tbo); 628 return r; 629 } 630 631 632 /** 633 * radeon_bo_reserve - reserve bo 634 * @bo: bo structure 635 * @no_wait: don't sleep while trying to reserve (return -EBUSY) 636 * 637 * Returns: 638 * -EBUSY: buffer is busy and @no_wait is true 639 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 640 * a signal. Release all buffer reservations and return to user-space. 641 */ 642 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) 643 { 644 int r; 645 646 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 647 if (unlikely(r != 0)) { 648 if (r != -ERESTARTSYS) 649 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 650 return r; 651 } 652 return 0; 653 } 654 655 /* object have to be reserved */ 656 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm) 657 { 658 struct radeon_bo_va *bo_va; 659 660 list_for_each_entry(bo_va, &rbo->va, bo_list) { 661 if (bo_va->vm == vm) { 662 return bo_va; 663 } 664 } 665 return NULL; 666 } 667