1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include "radeon_drm.h" 36 #include "radeon.h" 37 #include "radeon_trace.h" 38 39 40 int radeon_ttm_init(struct radeon_device *rdev); 41 void radeon_ttm_fini(struct radeon_device *rdev); 42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 43 44 /* 45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 46 * function are calling it. 47 */ 48 49 void radeon_bo_clear_va(struct radeon_bo *bo) 50 { 51 struct radeon_bo_va *bo_va, *tmp; 52 53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 54 /* remove from all vm address space */ 55 radeon_vm_bo_rmv(bo->rdev, bo_va->vm, bo); 56 } 57 } 58 59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 60 { 61 struct radeon_bo *bo; 62 63 bo = container_of(tbo, struct radeon_bo, tbo); 64 mutex_lock(&bo->rdev->gem.mutex); 65 list_del_init(&bo->list); 66 mutex_unlock(&bo->rdev->gem.mutex); 67 radeon_bo_clear_surface_reg(bo); 68 radeon_bo_clear_va(bo); 69 drm_gem_object_release(&bo->gem_base); 70 kfree(bo); 71 } 72 73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 74 { 75 if (bo->destroy == &radeon_ttm_bo_destroy) 76 return true; 77 return false; 78 } 79 80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 81 { 82 u32 c = 0; 83 84 rbo->placement.fpfn = 0; 85 rbo->placement.lpfn = 0; 86 rbo->placement.placement = rbo->placements; 87 rbo->placement.busy_placement = rbo->placements; 88 if (domain & RADEON_GEM_DOMAIN_VRAM) 89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 90 TTM_PL_FLAG_VRAM; 91 if (domain & RADEON_GEM_DOMAIN_GTT) 92 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 93 if (domain & RADEON_GEM_DOMAIN_CPU) 94 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 95 if (!c) 96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 97 rbo->placement.num_placement = c; 98 rbo->placement.num_busy_placement = c; 99 } 100 101 int radeon_bo_create(struct radeon_device *rdev, 102 unsigned long size, int byte_align, bool kernel, u32 domain, 103 struct sg_table *sg, struct radeon_bo **bo_ptr) 104 { 105 struct radeon_bo *bo; 106 enum ttm_bo_type type; 107 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 108 unsigned long max_size = 0; 109 size_t acc_size; 110 int r; 111 112 size = ALIGN(size, PAGE_SIZE); 113 114 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 115 if (kernel) { 116 type = ttm_bo_type_kernel; 117 } else if (sg) { 118 type = ttm_bo_type_sg; 119 } else { 120 type = ttm_bo_type_device; 121 } 122 *bo_ptr = NULL; 123 124 /* maximun bo size is the minimun btw visible vram and gtt size */ 125 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size); 126 if ((page_align << PAGE_SHIFT) >= max_size) { 127 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n", 128 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20); 129 return -ENOMEM; 130 } 131 132 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 133 sizeof(struct radeon_bo)); 134 135 retry: 136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 137 if (bo == NULL) 138 return -ENOMEM; 139 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 140 if (unlikely(r)) { 141 kfree(bo); 142 return r; 143 } 144 bo->rdev = rdev; 145 bo->gem_base.driver_private = NULL; 146 bo->surface_reg = -1; 147 INIT_LIST_HEAD(&bo->list); 148 INIT_LIST_HEAD(&bo->va); 149 radeon_ttm_placement_from_domain(bo, domain); 150 /* Kernel allocation are uninterruptible */ 151 down_read(&rdev->pm.mclk_lock); 152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 153 &bo->placement, page_align, 0, !kernel, NULL, 154 acc_size, sg, &radeon_ttm_bo_destroy); 155 up_read(&rdev->pm.mclk_lock); 156 if (unlikely(r != 0)) { 157 if (r != -ERESTARTSYS) { 158 if (domain == RADEON_GEM_DOMAIN_VRAM) { 159 domain |= RADEON_GEM_DOMAIN_GTT; 160 goto retry; 161 } 162 dev_err(rdev->dev, 163 "object_init failed for (%lu, 0x%08X)\n", 164 size, domain); 165 } 166 return r; 167 } 168 *bo_ptr = bo; 169 170 trace_radeon_bo_create(bo); 171 172 return 0; 173 } 174 175 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 176 { 177 bool is_iomem; 178 int r; 179 180 if (bo->kptr) { 181 if (ptr) { 182 *ptr = bo->kptr; 183 } 184 return 0; 185 } 186 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 187 if (r) { 188 return r; 189 } 190 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 191 if (ptr) { 192 *ptr = bo->kptr; 193 } 194 radeon_bo_check_tiling(bo, 0, 0); 195 return 0; 196 } 197 198 void radeon_bo_kunmap(struct radeon_bo *bo) 199 { 200 if (bo->kptr == NULL) 201 return; 202 bo->kptr = NULL; 203 radeon_bo_check_tiling(bo, 0, 0); 204 ttm_bo_kunmap(&bo->kmap); 205 } 206 207 void radeon_bo_unref(struct radeon_bo **bo) 208 { 209 struct ttm_buffer_object *tbo; 210 struct radeon_device *rdev; 211 212 if ((*bo) == NULL) 213 return; 214 rdev = (*bo)->rdev; 215 tbo = &((*bo)->tbo); 216 down_read(&rdev->pm.mclk_lock); 217 ttm_bo_unref(&tbo); 218 up_read(&rdev->pm.mclk_lock); 219 if (tbo == NULL) 220 *bo = NULL; 221 } 222 223 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 224 u64 *gpu_addr) 225 { 226 int r, i; 227 228 if (bo->pin_count) { 229 bo->pin_count++; 230 if (gpu_addr) 231 *gpu_addr = radeon_bo_gpu_offset(bo); 232 233 if (max_offset != 0) { 234 u64 domain_start; 235 236 if (domain == RADEON_GEM_DOMAIN_VRAM) 237 domain_start = bo->rdev->mc.vram_start; 238 else 239 domain_start = bo->rdev->mc.gtt_start; 240 WARN_ON_ONCE(max_offset < 241 (radeon_bo_gpu_offset(bo) - domain_start)); 242 } 243 244 return 0; 245 } 246 radeon_ttm_placement_from_domain(bo, domain); 247 if (domain == RADEON_GEM_DOMAIN_VRAM) { 248 /* force to pin into visible video ram */ 249 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 250 } 251 if (max_offset) { 252 u64 lpfn = max_offset >> PAGE_SHIFT; 253 254 if (!bo->placement.lpfn) 255 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 256 257 if (lpfn < bo->placement.lpfn) 258 bo->placement.lpfn = lpfn; 259 } 260 for (i = 0; i < bo->placement.num_placement; i++) 261 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 262 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 263 if (likely(r == 0)) { 264 bo->pin_count = 1; 265 if (gpu_addr != NULL) 266 *gpu_addr = radeon_bo_gpu_offset(bo); 267 } 268 if (unlikely(r != 0)) 269 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 270 return r; 271 } 272 273 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 274 { 275 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 276 } 277 278 int radeon_bo_unpin(struct radeon_bo *bo) 279 { 280 int r, i; 281 282 if (!bo->pin_count) { 283 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 284 return 0; 285 } 286 bo->pin_count--; 287 if (bo->pin_count) 288 return 0; 289 for (i = 0; i < bo->placement.num_placement; i++) 290 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 291 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); 292 if (unlikely(r != 0)) 293 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 294 return r; 295 } 296 297 int radeon_bo_evict_vram(struct radeon_device *rdev) 298 { 299 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 300 if (0 && (rdev->flags & RADEON_IS_IGP)) { 301 if (rdev->mc.igp_sideport_enabled == false) 302 /* Useless to evict on IGP chips */ 303 return 0; 304 } 305 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 306 } 307 308 void radeon_bo_force_delete(struct radeon_device *rdev) 309 { 310 struct radeon_bo *bo, *n; 311 312 if (list_empty(&rdev->gem.objects)) { 313 return; 314 } 315 dev_err(rdev->dev, "Userspace still has active objects !\n"); 316 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 317 mutex_lock(&rdev->ddev->struct_mutex); 318 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 319 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 320 *((unsigned long *)&bo->gem_base.refcount)); 321 mutex_lock(&bo->rdev->gem.mutex); 322 list_del_init(&bo->list); 323 mutex_unlock(&bo->rdev->gem.mutex); 324 /* this should unref the ttm bo */ 325 drm_gem_object_unreference(&bo->gem_base); 326 mutex_unlock(&rdev->ddev->struct_mutex); 327 } 328 } 329 330 int radeon_bo_init(struct radeon_device *rdev) 331 { 332 /* Add an MTRR for the VRAM */ 333 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 334 MTRR_TYPE_WRCOMB, 1); 335 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 336 rdev->mc.mc_vram_size >> 20, 337 (unsigned long long)rdev->mc.aper_size >> 20); 338 DRM_INFO("RAM width %dbits %cDR\n", 339 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 340 return radeon_ttm_init(rdev); 341 } 342 343 void radeon_bo_fini(struct radeon_device *rdev) 344 { 345 radeon_ttm_fini(rdev); 346 } 347 348 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 349 struct list_head *head) 350 { 351 if (lobj->wdomain) { 352 list_add(&lobj->tv.head, head); 353 } else { 354 list_add_tail(&lobj->tv.head, head); 355 } 356 } 357 358 int radeon_bo_list_validate(struct list_head *head) 359 { 360 struct radeon_bo_list *lobj; 361 struct radeon_bo *bo; 362 u32 domain; 363 int r; 364 365 r = ttm_eu_reserve_buffers(head); 366 if (unlikely(r != 0)) { 367 return r; 368 } 369 list_for_each_entry(lobj, head, tv.head) { 370 bo = lobj->bo; 371 if (!bo->pin_count) { 372 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 373 374 retry: 375 radeon_ttm_placement_from_domain(bo, domain); 376 r = ttm_bo_validate(&bo->tbo, &bo->placement, 377 true, false, false); 378 if (unlikely(r)) { 379 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 380 domain |= RADEON_GEM_DOMAIN_GTT; 381 goto retry; 382 } 383 return r; 384 } 385 } 386 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 387 lobj->tiling_flags = bo->tiling_flags; 388 } 389 return 0; 390 } 391 392 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 393 struct vm_area_struct *vma) 394 { 395 return ttm_fbdev_mmap(vma, &bo->tbo); 396 } 397 398 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 399 { 400 struct radeon_device *rdev = bo->rdev; 401 struct radeon_surface_reg *reg; 402 struct radeon_bo *old_object; 403 int steal; 404 int i; 405 406 BUG_ON(!atomic_read(&bo->tbo.reserved)); 407 408 if (!bo->tiling_flags) 409 return 0; 410 411 if (bo->surface_reg >= 0) { 412 reg = &rdev->surface_regs[bo->surface_reg]; 413 i = bo->surface_reg; 414 goto out; 415 } 416 417 steal = -1; 418 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 419 420 reg = &rdev->surface_regs[i]; 421 if (!reg->bo) 422 break; 423 424 old_object = reg->bo; 425 if (old_object->pin_count == 0) 426 steal = i; 427 } 428 429 /* if we are all out */ 430 if (i == RADEON_GEM_MAX_SURFACES) { 431 if (steal == -1) 432 return -ENOMEM; 433 /* find someone with a surface reg and nuke their BO */ 434 reg = &rdev->surface_regs[steal]; 435 old_object = reg->bo; 436 /* blow away the mapping */ 437 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 438 ttm_bo_unmap_virtual(&old_object->tbo); 439 old_object->surface_reg = -1; 440 i = steal; 441 } 442 443 bo->surface_reg = i; 444 reg->bo = bo; 445 446 out: 447 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 448 bo->tbo.mem.start << PAGE_SHIFT, 449 bo->tbo.num_pages << PAGE_SHIFT); 450 return 0; 451 } 452 453 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 454 { 455 struct radeon_device *rdev = bo->rdev; 456 struct radeon_surface_reg *reg; 457 458 if (bo->surface_reg == -1) 459 return; 460 461 reg = &rdev->surface_regs[bo->surface_reg]; 462 radeon_clear_surface_reg(rdev, bo->surface_reg); 463 464 reg->bo = NULL; 465 bo->surface_reg = -1; 466 } 467 468 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 469 uint32_t tiling_flags, uint32_t pitch) 470 { 471 struct radeon_device *rdev = bo->rdev; 472 int r; 473 474 if (rdev->family >= CHIP_CEDAR) { 475 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 476 477 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 478 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 479 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 480 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 481 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 482 switch (bankw) { 483 case 0: 484 case 1: 485 case 2: 486 case 4: 487 case 8: 488 break; 489 default: 490 return -EINVAL; 491 } 492 switch (bankh) { 493 case 0: 494 case 1: 495 case 2: 496 case 4: 497 case 8: 498 break; 499 default: 500 return -EINVAL; 501 } 502 switch (mtaspect) { 503 case 0: 504 case 1: 505 case 2: 506 case 4: 507 case 8: 508 break; 509 default: 510 return -EINVAL; 511 } 512 if (tilesplit > 6) { 513 return -EINVAL; 514 } 515 if (stilesplit > 6) { 516 return -EINVAL; 517 } 518 } 519 r = radeon_bo_reserve(bo, false); 520 if (unlikely(r != 0)) 521 return r; 522 bo->tiling_flags = tiling_flags; 523 bo->pitch = pitch; 524 radeon_bo_unreserve(bo); 525 return 0; 526 } 527 528 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 529 uint32_t *tiling_flags, 530 uint32_t *pitch) 531 { 532 BUG_ON(!atomic_read(&bo->tbo.reserved)); 533 if (tiling_flags) 534 *tiling_flags = bo->tiling_flags; 535 if (pitch) 536 *pitch = bo->pitch; 537 } 538 539 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 540 bool force_drop) 541 { 542 BUG_ON(!atomic_read(&bo->tbo.reserved)); 543 544 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 545 return 0; 546 547 if (force_drop) { 548 radeon_bo_clear_surface_reg(bo); 549 return 0; 550 } 551 552 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 553 if (!has_moved) 554 return 0; 555 556 if (bo->surface_reg >= 0) 557 radeon_bo_clear_surface_reg(bo); 558 return 0; 559 } 560 561 if ((bo->surface_reg >= 0) && !has_moved) 562 return 0; 563 564 return radeon_bo_get_surface_reg(bo); 565 } 566 567 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 568 struct ttm_mem_reg *mem) 569 { 570 struct radeon_bo *rbo; 571 if (!radeon_ttm_bo_is_radeon_bo(bo)) 572 return; 573 rbo = container_of(bo, struct radeon_bo, tbo); 574 radeon_bo_check_tiling(rbo, 0, 1); 575 radeon_vm_bo_invalidate(rbo->rdev, rbo); 576 } 577 578 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 579 { 580 struct radeon_device *rdev; 581 struct radeon_bo *rbo; 582 unsigned long offset, size; 583 int r; 584 585 if (!radeon_ttm_bo_is_radeon_bo(bo)) 586 return 0; 587 rbo = container_of(bo, struct radeon_bo, tbo); 588 radeon_bo_check_tiling(rbo, 0, 0); 589 rdev = rbo->rdev; 590 if (bo->mem.mem_type == TTM_PL_VRAM) { 591 size = bo->mem.num_pages << PAGE_SHIFT; 592 offset = bo->mem.start << PAGE_SHIFT; 593 if ((offset + size) > rdev->mc.visible_vram_size) { 594 /* hurrah the memory is not visible ! */ 595 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 596 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 597 r = ttm_bo_validate(bo, &rbo->placement, false, true, false); 598 if (unlikely(r != 0)) 599 return r; 600 offset = bo->mem.start << PAGE_SHIFT; 601 /* this should not happen */ 602 if ((offset + size) > rdev->mc.visible_vram_size) 603 return -EINVAL; 604 } 605 } 606 return 0; 607 } 608 609 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 610 { 611 int r; 612 613 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 614 if (unlikely(r != 0)) 615 return r; 616 spin_lock(&bo->tbo.bdev->fence_lock); 617 if (mem_type) 618 *mem_type = bo->tbo.mem.mem_type; 619 if (bo->tbo.sync_obj) 620 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 621 spin_unlock(&bo->tbo.bdev->fence_lock); 622 ttm_bo_unreserve(&bo->tbo); 623 return r; 624 } 625 626 627 /** 628 * radeon_bo_reserve - reserve bo 629 * @bo: bo structure 630 * @no_wait: don't sleep while trying to reserve (return -EBUSY) 631 * 632 * Returns: 633 * -EBUSY: buffer is busy and @no_wait is true 634 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 635 * a signal. Release all buffer reservations and return to user-space. 636 */ 637 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) 638 { 639 int r; 640 641 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 642 if (unlikely(r != 0)) { 643 if (r != -ERESTARTSYS) 644 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 645 return r; 646 } 647 return 0; 648 } 649 650 /* object have to be reserved */ 651 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm) 652 { 653 struct radeon_bo_va *bo_va; 654 655 list_for_each_entry(bo_va, &rbo->va, bo_list) { 656 if (bo_va->vm == vm) { 657 return bo_va; 658 } 659 } 660 return NULL; 661 } 662