1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_dp_mst_helper.h> 37 #include <drm/drm_fixed.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 42 struct radeon_bo; 43 struct radeon_device; 44 45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 46 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 47 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 48 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 49 50 #define RADEON_MAX_HPD_PINS 7 51 #define RADEON_MAX_CRTCS 6 52 #define RADEON_MAX_AFMT_BLOCKS 7 53 54 enum radeon_rmx_type { 55 RMX_OFF, 56 RMX_FULL, 57 RMX_CENTER, 58 RMX_ASPECT 59 }; 60 61 enum radeon_tv_std { 62 TV_STD_NTSC, 63 TV_STD_PAL, 64 TV_STD_PAL_M, 65 TV_STD_PAL_60, 66 TV_STD_NTSC_J, 67 TV_STD_SCART_PAL, 68 TV_STD_SECAM, 69 TV_STD_PAL_CN, 70 TV_STD_PAL_N, 71 }; 72 73 enum radeon_underscan_type { 74 UNDERSCAN_OFF, 75 UNDERSCAN_ON, 76 UNDERSCAN_AUTO, 77 }; 78 79 enum radeon_hpd_id { 80 RADEON_HPD_1 = 0, 81 RADEON_HPD_2, 82 RADEON_HPD_3, 83 RADEON_HPD_4, 84 RADEON_HPD_5, 85 RADEON_HPD_6, 86 RADEON_HPD_NONE = 0xff, 87 }; 88 89 enum radeon_output_csc { 90 RADEON_OUTPUT_CSC_BYPASS = 0, 91 RADEON_OUTPUT_CSC_TVRGB = 1, 92 RADEON_OUTPUT_CSC_YCBCR601 = 2, 93 RADEON_OUTPUT_CSC_YCBCR709 = 3, 94 }; 95 96 #define RADEON_MAX_I2C_BUS 16 97 98 /* radeon gpio-based i2c 99 * 1. "mask" reg and bits 100 * grabs the gpio pins for software use 101 * 0=not held 1=held 102 * 2. "a" reg and bits 103 * output pin value 104 * 0=low 1=high 105 * 3. "en" reg and bits 106 * sets the pin direction 107 * 0=input 1=output 108 * 4. "y" reg and bits 109 * input pin value 110 * 0=low 1=high 111 */ 112 struct radeon_i2c_bus_rec { 113 bool valid; 114 /* id used by atom */ 115 uint8_t i2c_id; 116 /* id used by atom */ 117 enum radeon_hpd_id hpd; 118 /* can be used with hw i2c engine */ 119 bool hw_capable; 120 /* uses multi-media i2c engine */ 121 bool mm_i2c; 122 /* regs and bits */ 123 uint32_t mask_clk_reg; 124 uint32_t mask_data_reg; 125 uint32_t a_clk_reg; 126 uint32_t a_data_reg; 127 uint32_t en_clk_reg; 128 uint32_t en_data_reg; 129 uint32_t y_clk_reg; 130 uint32_t y_data_reg; 131 uint32_t mask_clk_mask; 132 uint32_t mask_data_mask; 133 uint32_t a_clk_mask; 134 uint32_t a_data_mask; 135 uint32_t en_clk_mask; 136 uint32_t en_data_mask; 137 uint32_t y_clk_mask; 138 uint32_t y_data_mask; 139 }; 140 141 struct radeon_tmds_pll { 142 uint32_t freq; 143 uint32_t value; 144 }; 145 146 #define RADEON_MAX_BIOS_CONNECTOR 16 147 148 /* pll flags */ 149 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 150 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 151 #define RADEON_PLL_USE_REF_DIV (1 << 2) 152 #define RADEON_PLL_LEGACY (1 << 3) 153 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 154 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 155 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 156 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 157 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 158 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 159 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 160 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 161 #define RADEON_PLL_USE_POST_DIV (1 << 12) 162 #define RADEON_PLL_IS_LCD (1 << 13) 163 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 164 165 struct radeon_pll { 166 /* reference frequency */ 167 uint32_t reference_freq; 168 169 /* fixed dividers */ 170 uint32_t reference_div; 171 uint32_t post_div; 172 173 /* pll in/out limits */ 174 uint32_t pll_in_min; 175 uint32_t pll_in_max; 176 uint32_t pll_out_min; 177 uint32_t pll_out_max; 178 uint32_t lcd_pll_out_min; 179 uint32_t lcd_pll_out_max; 180 uint32_t best_vco; 181 182 /* divider limits */ 183 uint32_t min_ref_div; 184 uint32_t max_ref_div; 185 uint32_t min_post_div; 186 uint32_t max_post_div; 187 uint32_t min_feedback_div; 188 uint32_t max_feedback_div; 189 uint32_t min_frac_feedback_div; 190 uint32_t max_frac_feedback_div; 191 192 /* flags for the current clock */ 193 uint32_t flags; 194 195 /* pll id */ 196 uint32_t id; 197 }; 198 199 struct radeon_i2c_chan { 200 struct i2c_adapter adapter; 201 struct drm_device *dev; 202 struct i2c_algo_bit_data bit; 203 struct radeon_i2c_bus_rec rec; 204 struct drm_dp_aux aux; 205 bool has_aux; 206 struct mutex mutex; 207 }; 208 209 /* mostly for macs, but really any system without connector tables */ 210 enum radeon_connector_table { 211 CT_NONE = 0, 212 CT_GENERIC, 213 CT_IBOOK, 214 CT_POWERBOOK_EXTERNAL, 215 CT_POWERBOOK_INTERNAL, 216 CT_POWERBOOK_VGA, 217 CT_MINI_EXTERNAL, 218 CT_MINI_INTERNAL, 219 CT_IMAC_G5_ISIGHT, 220 CT_EMAC, 221 CT_RN50_POWER, 222 CT_MAC_X800, 223 CT_MAC_G5_9600, 224 CT_SAM440EP, 225 CT_MAC_G4_SILVER 226 }; 227 228 enum radeon_dvo_chip { 229 DVO_SIL164, 230 DVO_SIL1178, 231 }; 232 233 struct radeon_fbdev; 234 235 struct radeon_afmt { 236 bool enabled; 237 int offset; 238 bool last_buffer_filled_status; 239 int id; 240 }; 241 242 struct radeon_mode_info { 243 struct atom_context *atom_context; 244 struct card_info *atom_card_info; 245 enum radeon_connector_table connector_table; 246 bool mode_config_initialized; 247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 248 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 249 /* DVI-I properties */ 250 struct drm_property *coherent_mode_property; 251 /* DAC enable load detect */ 252 struct drm_property *load_detect_property; 253 /* TV standard */ 254 struct drm_property *tv_std_property; 255 /* legacy TMDS PLL detect */ 256 struct drm_property *tmds_pll_property; 257 /* underscan */ 258 struct drm_property *underscan_property; 259 struct drm_property *underscan_hborder_property; 260 struct drm_property *underscan_vborder_property; 261 /* audio */ 262 struct drm_property *audio_property; 263 /* FMT dithering */ 264 struct drm_property *dither_property; 265 /* Output CSC */ 266 struct drm_property *output_csc_property; 267 /* hardcoded DFP edid from BIOS */ 268 struct edid *bios_hardcoded_edid; 269 int bios_hardcoded_edid_size; 270 271 /* pointer to fbdev info structure */ 272 struct radeon_fbdev *rfbdev; 273 /* firmware flags */ 274 u16 firmware_flags; 275 /* pointer to backlight encoder */ 276 struct radeon_encoder *bl_encoder; 277 278 /* bitmask for active encoder frontends */ 279 uint32_t active_encoders; 280 }; 281 282 #define RADEON_MAX_BL_LEVEL 0xFF 283 284 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 285 286 struct radeon_backlight_privdata { 287 struct radeon_encoder *encoder; 288 uint8_t negative; 289 }; 290 291 #endif 292 293 #define MAX_H_CODE_TIMING_LEN 32 294 #define MAX_V_CODE_TIMING_LEN 32 295 296 /* need to store these as reading 297 back code tables is excessive */ 298 struct radeon_tv_regs { 299 uint32_t tv_uv_adr; 300 uint32_t timing_cntl; 301 uint32_t hrestart; 302 uint32_t vrestart; 303 uint32_t frestart; 304 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 305 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 306 }; 307 308 struct radeon_atom_ss { 309 uint16_t percentage; 310 uint16_t percentage_divider; 311 uint8_t type; 312 uint16_t step; 313 uint8_t delay; 314 uint8_t range; 315 uint8_t refdiv; 316 /* asic_ss */ 317 uint16_t rate; 318 uint16_t amount; 319 }; 320 321 enum radeon_flip_status { 322 RADEON_FLIP_NONE, 323 RADEON_FLIP_PENDING, 324 RADEON_FLIP_SUBMITTED 325 }; 326 327 struct radeon_crtc { 328 struct drm_crtc base; 329 int crtc_id; 330 u16 lut_r[256], lut_g[256], lut_b[256]; 331 bool enabled; 332 bool can_tile; 333 uint32_t crtc_offset; 334 struct drm_gem_object *cursor_bo; 335 uint64_t cursor_addr; 336 int cursor_x; 337 int cursor_y; 338 int cursor_hot_x; 339 int cursor_hot_y; 340 int cursor_width; 341 int cursor_height; 342 int max_cursor_width; 343 int max_cursor_height; 344 uint32_t legacy_display_base_addr; 345 enum radeon_rmx_type rmx_type; 346 u8 h_border; 347 u8 v_border; 348 fixed20_12 vsc; 349 fixed20_12 hsc; 350 struct drm_display_mode native_mode; 351 int pll_id; 352 /* page flipping */ 353 struct workqueue_struct *flip_queue; 354 struct radeon_flip_work *flip_work; 355 enum radeon_flip_status flip_status; 356 /* pll sharing */ 357 struct radeon_atom_ss ss; 358 bool ss_enabled; 359 u32 adjusted_clock; 360 int bpc; 361 u32 pll_reference_div; 362 u32 pll_post_div; 363 u32 pll_flags; 364 struct drm_encoder *encoder; 365 struct drm_connector *connector; 366 /* for dpm */ 367 u32 line_time; 368 u32 wm_low; 369 u32 wm_high; 370 struct drm_display_mode hw_mode; 371 enum radeon_output_csc output_csc; 372 }; 373 374 struct radeon_encoder_primary_dac { 375 /* legacy primary dac */ 376 uint32_t ps2_pdac_adj; 377 }; 378 379 struct radeon_encoder_lvds { 380 /* legacy lvds */ 381 uint16_t panel_vcc_delay; 382 uint8_t panel_pwr_delay; 383 uint8_t panel_digon_delay; 384 uint8_t panel_blon_delay; 385 uint16_t panel_ref_divider; 386 uint8_t panel_post_divider; 387 uint16_t panel_fb_divider; 388 bool use_bios_dividers; 389 uint32_t lvds_gen_cntl; 390 /* panel mode */ 391 struct drm_display_mode native_mode; 392 struct backlight_device *bl_dev; 393 int dpms_mode; 394 uint8_t backlight_level; 395 }; 396 397 struct radeon_encoder_tv_dac { 398 /* legacy tv dac */ 399 uint32_t ps2_tvdac_adj; 400 uint32_t ntsc_tvdac_adj; 401 uint32_t pal_tvdac_adj; 402 403 int h_pos; 404 int v_pos; 405 int h_size; 406 int supported_tv_stds; 407 bool tv_on; 408 enum radeon_tv_std tv_std; 409 struct radeon_tv_regs tv; 410 }; 411 412 struct radeon_encoder_int_tmds { 413 /* legacy int tmds */ 414 struct radeon_tmds_pll tmds_pll[4]; 415 }; 416 417 struct radeon_encoder_ext_tmds { 418 /* tmds over dvo */ 419 struct radeon_i2c_chan *i2c_bus; 420 uint8_t slave_addr; 421 enum radeon_dvo_chip dvo_chip; 422 }; 423 424 /* spread spectrum */ 425 struct radeon_encoder_atom_dig { 426 bool linkb; 427 /* atom dig */ 428 bool coherent_mode; 429 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 430 /* atom lvds/edp */ 431 uint32_t lcd_misc; 432 uint16_t panel_pwr_delay; 433 uint32_t lcd_ss_id; 434 /* panel mode */ 435 struct drm_display_mode native_mode; 436 struct backlight_device *bl_dev; 437 int dpms_mode; 438 uint8_t backlight_level; 439 int panel_mode; 440 struct radeon_afmt *afmt; 441 struct r600_audio_pin *pin; 442 int active_mst_links; 443 }; 444 445 struct radeon_encoder_atom_dac { 446 enum radeon_tv_std tv_std; 447 }; 448 449 struct radeon_encoder_mst { 450 int crtc; 451 struct radeon_encoder *primary; 452 struct radeon_connector *connector; 453 struct drm_dp_mst_port *port; 454 int pbn; 455 int fe; 456 bool fe_from_be; 457 bool enc_active; 458 }; 459 460 struct radeon_encoder { 461 struct drm_encoder base; 462 uint32_t encoder_enum; 463 uint32_t encoder_id; 464 uint32_t devices; 465 uint32_t active_device; 466 uint32_t flags; 467 uint32_t pixel_clock; 468 enum radeon_rmx_type rmx_type; 469 enum radeon_underscan_type underscan_type; 470 uint32_t underscan_hborder; 471 uint32_t underscan_vborder; 472 struct drm_display_mode native_mode; 473 void *enc_priv; 474 int audio_polling_active; 475 bool is_ext_encoder; 476 u16 caps; 477 struct radeon_audio_funcs *audio; 478 enum radeon_output_csc output_csc; 479 bool can_mst; 480 uint32_t offset; 481 bool is_mst_encoder; 482 /* front end for this mst encoder */ 483 }; 484 485 struct radeon_connector_atom_dig { 486 uint32_t igp_lane_info; 487 /* displayport */ 488 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 489 u8 dp_sink_type; 490 int dp_clock; 491 int dp_lane_count; 492 bool edp_on; 493 bool is_mst; 494 }; 495 496 struct radeon_gpio_rec { 497 bool valid; 498 u8 id; 499 u32 reg; 500 u32 mask; 501 u32 shift; 502 }; 503 504 struct radeon_hpd { 505 enum radeon_hpd_id hpd; 506 u8 plugged_state; 507 struct radeon_gpio_rec gpio; 508 }; 509 510 struct radeon_router { 511 u32 router_id; 512 struct radeon_i2c_bus_rec i2c_info; 513 u8 i2c_addr; 514 /* i2c mux */ 515 bool ddc_valid; 516 u8 ddc_mux_type; 517 u8 ddc_mux_control_pin; 518 u8 ddc_mux_state; 519 /* clock/data mux */ 520 bool cd_valid; 521 u8 cd_mux_type; 522 u8 cd_mux_control_pin; 523 u8 cd_mux_state; 524 }; 525 526 enum radeon_connector_audio { 527 RADEON_AUDIO_DISABLE = 0, 528 RADEON_AUDIO_ENABLE = 1, 529 RADEON_AUDIO_AUTO = 2 530 }; 531 532 enum radeon_connector_dither { 533 RADEON_FMT_DITHER_DISABLE = 0, 534 RADEON_FMT_DITHER_ENABLE = 1, 535 }; 536 537 struct stream_attribs { 538 uint16_t fe; 539 uint16_t slots; 540 }; 541 542 struct radeon_connector { 543 struct drm_connector base; 544 uint32_t connector_id; 545 uint32_t devices; 546 struct radeon_i2c_chan *ddc_bus; 547 /* some systems have an hdmi and vga port with a shared ddc line */ 548 bool shared_ddc; 549 bool use_digital; 550 /* we need to mind the EDID between detect 551 and get modes due to analog/digital/tvencoder */ 552 struct edid *edid; 553 void *con_priv; 554 bool dac_load_detect; 555 bool detected_by_load; /* if the connection status was determined by load */ 556 uint16_t connector_object_id; 557 struct radeon_hpd hpd; 558 struct radeon_router router; 559 struct radeon_i2c_chan *router_bus; 560 enum radeon_connector_audio audio; 561 enum radeon_connector_dither dither; 562 int pixelclock_for_modeset; 563 bool is_mst_connector; 564 struct radeon_connector *mst_port; 565 struct drm_dp_mst_port *port; 566 struct drm_dp_mst_topology_mgr mst_mgr; 567 568 struct radeon_encoder *mst_encoder; 569 struct stream_attribs cur_stream_attribs[6]; 570 int enabled_attribs; 571 }; 572 573 struct radeon_framebuffer { 574 struct drm_framebuffer base; 575 struct drm_gem_object *obj; 576 }; 577 578 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 579 ((em) == ATOM_ENCODER_MODE_DP_MST)) 580 581 struct atom_clock_dividers { 582 u32 post_div; 583 union { 584 struct { 585 #ifdef __BIG_ENDIAN 586 u32 reserved : 6; 587 u32 whole_fb_div : 12; 588 u32 frac_fb_div : 14; 589 #else 590 u32 frac_fb_div : 14; 591 u32 whole_fb_div : 12; 592 u32 reserved : 6; 593 #endif 594 }; 595 u32 fb_div; 596 }; 597 u32 ref_div; 598 bool enable_post_div; 599 bool enable_dithen; 600 u32 vco_mode; 601 u32 real_clock; 602 /* added for CI */ 603 u32 post_divider; 604 u32 flags; 605 }; 606 607 struct atom_mpll_param { 608 union { 609 struct { 610 #ifdef __BIG_ENDIAN 611 u32 reserved : 8; 612 u32 clkfrac : 12; 613 u32 clkf : 12; 614 #else 615 u32 clkf : 12; 616 u32 clkfrac : 12; 617 u32 reserved : 8; 618 #endif 619 }; 620 u32 fb_div; 621 }; 622 u32 post_div; 623 u32 bwcntl; 624 u32 dll_speed; 625 u32 vco_mode; 626 u32 yclk_sel; 627 u32 qdr; 628 u32 half_rate; 629 }; 630 631 #define MEM_TYPE_GDDR5 0x50 632 #define MEM_TYPE_GDDR4 0x40 633 #define MEM_TYPE_GDDR3 0x30 634 #define MEM_TYPE_DDR2 0x20 635 #define MEM_TYPE_GDDR1 0x10 636 #define MEM_TYPE_DDR3 0xb0 637 #define MEM_TYPE_MASK 0xf0 638 639 struct atom_memory_info { 640 u8 mem_vendor; 641 u8 mem_type; 642 }; 643 644 #define MAX_AC_TIMING_ENTRIES 16 645 646 struct atom_memory_clock_range_table 647 { 648 u8 num_entries; 649 u8 rsv[3]; 650 u32 mclk[MAX_AC_TIMING_ENTRIES]; 651 }; 652 653 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 654 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 655 656 struct atom_mc_reg_entry { 657 u32 mclk_max; 658 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 659 }; 660 661 struct atom_mc_register_address { 662 u16 s1; 663 u8 pre_reg_data; 664 }; 665 666 struct atom_mc_reg_table { 667 u8 last; 668 u8 num_entries; 669 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 670 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 671 }; 672 673 #define MAX_VOLTAGE_ENTRIES 32 674 675 struct atom_voltage_table_entry 676 { 677 u16 value; 678 u32 smio_low; 679 }; 680 681 struct atom_voltage_table 682 { 683 u32 count; 684 u32 mask_low; 685 u32 phase_delay; 686 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 687 }; 688 689 690 extern void 691 radeon_add_atom_connector(struct drm_device *dev, 692 uint32_t connector_id, 693 uint32_t supported_device, 694 int connector_type, 695 struct radeon_i2c_bus_rec *i2c_bus, 696 uint32_t igp_lane_info, 697 uint16_t connector_object_id, 698 struct radeon_hpd *hpd, 699 struct radeon_router *router); 700 extern void 701 radeon_add_legacy_connector(struct drm_device *dev, 702 uint32_t connector_id, 703 uint32_t supported_device, 704 int connector_type, 705 struct radeon_i2c_bus_rec *i2c_bus, 706 uint16_t connector_object_id, 707 struct radeon_hpd *hpd); 708 extern uint32_t 709 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 710 uint8_t dac); 711 extern void radeon_link_encoder_connector(struct drm_device *dev); 712 713 extern enum radeon_tv_std 714 radeon_combios_get_tv_info(struct radeon_device *rdev); 715 extern enum radeon_tv_std 716 radeon_atombios_get_tv_info(struct radeon_device *rdev); 717 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 718 u16 *vddc, u16 *vddci, u16 *mvdd); 719 720 extern void 721 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 722 struct drm_encoder *encoder, 723 bool connected); 724 extern void 725 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 726 struct drm_encoder *encoder, 727 bool connected); 728 729 extern struct drm_connector * 730 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 731 extern struct drm_connector * 732 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 733 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 734 u32 pixel_clock); 735 736 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 737 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 738 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 739 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 740 741 extern struct edid *radeon_connector_edid(struct drm_connector *connector); 742 743 extern void radeon_connector_hotplug(struct drm_connector *connector); 744 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 745 struct drm_display_mode *mode); 746 extern void radeon_dp_set_link_config(struct drm_connector *connector, 747 const struct drm_display_mode *mode); 748 extern void radeon_dp_link_train(struct drm_encoder *encoder, 749 struct drm_connector *connector); 750 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 751 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 752 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 753 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 754 struct drm_connector *connector); 755 int radeon_dp_get_max_link_rate(struct drm_connector *connector, 756 const u8 *dpcd); 757 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 758 u8 power_state); 759 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 760 extern ssize_t 761 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 762 763 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 764 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 765 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 766 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 767 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 768 int action, uint8_t lane_num, 769 uint8_t lane_set); 770 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 771 int action, uint8_t lane_num, 772 uint8_t lane_set, int fe); 773 extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, 774 int fe); 775 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 776 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 777 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 778 779 extern void radeon_i2c_init(struct radeon_device *rdev); 780 extern void radeon_i2c_fini(struct radeon_device *rdev); 781 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 782 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 783 extern void radeon_i2c_add(struct radeon_device *rdev, 784 struct radeon_i2c_bus_rec *rec, 785 const char *name); 786 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 787 struct radeon_i2c_bus_rec *i2c_bus); 788 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 789 struct radeon_i2c_bus_rec *rec, 790 const char *name); 791 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 792 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 793 u8 slave_addr, 794 u8 addr, 795 u8 *val); 796 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 797 u8 slave_addr, 798 u8 addr, 799 u8 val); 800 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 801 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 802 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 803 804 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 805 struct radeon_atom_ss *ss, 806 int id); 807 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 808 struct radeon_atom_ss *ss, 809 int id, u32 clock); 810 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 811 u8 id); 812 813 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 814 uint64_t freq, 815 uint32_t *dot_clock_p, 816 uint32_t *fb_div_p, 817 uint32_t *frac_fb_div_p, 818 uint32_t *ref_div_p, 819 uint32_t *post_div_p); 820 821 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 822 u32 freq, 823 u32 *dot_clock_p, 824 u32 *fb_div_p, 825 u32 *frac_fb_div_p, 826 u32 *ref_div_p, 827 u32 *post_div_p); 828 829 extern void radeon_setup_encoder_clones(struct drm_device *dev); 830 831 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 832 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 833 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 834 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 835 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 836 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 837 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 838 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 839 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 840 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 841 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 842 843 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 844 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 845 struct drm_framebuffer *old_fb); 846 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 847 struct drm_framebuffer *fb, 848 int x, int y, 849 enum mode_set_atomic state); 850 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 851 struct drm_display_mode *mode, 852 struct drm_display_mode *adjusted_mode, 853 int x, int y, 854 struct drm_framebuffer *old_fb); 855 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 856 857 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 858 struct drm_framebuffer *old_fb); 859 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 860 struct drm_framebuffer *fb, 861 int x, int y, 862 enum mode_set_atomic state); 863 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 864 struct drm_framebuffer *fb, 865 int x, int y, int atomic); 866 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 867 struct drm_file *file_priv, 868 uint32_t handle, 869 uint32_t width, 870 uint32_t height, 871 int32_t hot_x, 872 int32_t hot_y); 873 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 874 int x, int y); 875 extern void radeon_cursor_reset(struct drm_crtc *crtc); 876 877 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 878 unsigned int flags, 879 int *vpos, int *hpos, ktime_t *stime, 880 ktime_t *etime); 881 882 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 883 extern struct edid * 884 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 885 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 886 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 887 extern struct radeon_encoder_atom_dig * 888 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 889 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 890 struct radeon_encoder_int_tmds *tmds); 891 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 892 struct radeon_encoder_int_tmds *tmds); 893 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 894 struct radeon_encoder_int_tmds *tmds); 895 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 896 struct radeon_encoder_ext_tmds *tmds); 897 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 898 struct radeon_encoder_ext_tmds *tmds); 899 extern struct radeon_encoder_primary_dac * 900 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 901 extern struct radeon_encoder_tv_dac * 902 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 903 extern struct radeon_encoder_lvds * 904 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 905 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 906 extern struct radeon_encoder_tv_dac * 907 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 908 extern struct radeon_encoder_primary_dac * 909 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 910 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 911 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 912 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 913 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 914 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 915 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 916 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 917 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 918 extern void 919 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 920 extern void 921 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 922 extern void 923 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 924 extern void 925 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 926 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 927 u16 blue, int regno); 928 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 929 u16 *blue, int regno); 930 int radeon_framebuffer_init(struct drm_device *dev, 931 struct radeon_framebuffer *rfb, 932 struct drm_mode_fb_cmd2 *mode_cmd, 933 struct drm_gem_object *obj); 934 935 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 936 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 937 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 938 void radeon_atombios_init_crtc(struct drm_device *dev, 939 struct radeon_crtc *radeon_crtc); 940 void radeon_legacy_init_crtc(struct drm_device *dev, 941 struct radeon_crtc *radeon_crtc); 942 943 void radeon_get_clock_info(struct drm_device *dev); 944 945 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 946 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 947 948 void radeon_enc_destroy(struct drm_encoder *encoder); 949 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 950 void radeon_combios_asic_init(struct drm_device *dev); 951 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 952 const struct drm_display_mode *mode, 953 struct drm_display_mode *adjusted_mode); 954 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 955 struct drm_display_mode *adjusted_mode); 956 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 957 958 /* legacy tv */ 959 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 960 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 961 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 962 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 963 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 964 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 965 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 966 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 967 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 968 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 969 struct drm_display_mode *mode, 970 struct drm_display_mode *adjusted_mode); 971 972 /* fmt blocks */ 973 void avivo_program_fmt(struct drm_encoder *encoder); 974 void dce3_program_fmt(struct drm_encoder *encoder); 975 void dce4_program_fmt(struct drm_encoder *encoder); 976 void dce8_program_fmt(struct drm_encoder *encoder); 977 978 /* fbdev layer */ 979 int radeon_fbdev_init(struct radeon_device *rdev); 980 void radeon_fbdev_fini(struct radeon_device *rdev); 981 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 982 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 983 void radeon_fbdev_restore_mode(struct radeon_device *rdev); 984 985 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 986 987 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 988 989 void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector); 990 void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector); 991 992 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 993 994 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 995 996 /* mst */ 997 int radeon_dp_mst_init(struct radeon_connector *radeon_connector); 998 int radeon_dp_mst_probe(struct radeon_connector *radeon_connector); 999 int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector); 1000 int radeon_mst_debugfs_init(struct radeon_device *rdev); 1001 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode); 1002 1003 void radeon_setup_mst_connector(struct drm_device *dev); 1004 1005 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 1006 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 1007 #endif 1008