1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct radeon_bo; 42 struct radeon_device; 43 44 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 45 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 46 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 47 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 48 49 enum radeon_rmx_type { 50 RMX_OFF, 51 RMX_FULL, 52 RMX_CENTER, 53 RMX_ASPECT 54 }; 55 56 enum radeon_tv_std { 57 TV_STD_NTSC, 58 TV_STD_PAL, 59 TV_STD_PAL_M, 60 TV_STD_PAL_60, 61 TV_STD_NTSC_J, 62 TV_STD_SCART_PAL, 63 TV_STD_SECAM, 64 TV_STD_PAL_CN, 65 TV_STD_PAL_N, 66 }; 67 68 enum radeon_underscan_type { 69 UNDERSCAN_OFF, 70 UNDERSCAN_ON, 71 UNDERSCAN_AUTO, 72 }; 73 74 enum radeon_hpd_id { 75 RADEON_HPD_1 = 0, 76 RADEON_HPD_2, 77 RADEON_HPD_3, 78 RADEON_HPD_4, 79 RADEON_HPD_5, 80 RADEON_HPD_6, 81 RADEON_HPD_NONE = 0xff, 82 }; 83 84 #define RADEON_MAX_I2C_BUS 16 85 86 /* radeon gpio-based i2c 87 * 1. "mask" reg and bits 88 * grabs the gpio pins for software use 89 * 0=not held 1=held 90 * 2. "a" reg and bits 91 * output pin value 92 * 0=low 1=high 93 * 3. "en" reg and bits 94 * sets the pin direction 95 * 0=input 1=output 96 * 4. "y" reg and bits 97 * input pin value 98 * 0=low 1=high 99 */ 100 struct radeon_i2c_bus_rec { 101 bool valid; 102 /* id used by atom */ 103 uint8_t i2c_id; 104 /* id used by atom */ 105 enum radeon_hpd_id hpd; 106 /* can be used with hw i2c engine */ 107 bool hw_capable; 108 /* uses multi-media i2c engine */ 109 bool mm_i2c; 110 /* regs and bits */ 111 uint32_t mask_clk_reg; 112 uint32_t mask_data_reg; 113 uint32_t a_clk_reg; 114 uint32_t a_data_reg; 115 uint32_t en_clk_reg; 116 uint32_t en_data_reg; 117 uint32_t y_clk_reg; 118 uint32_t y_data_reg; 119 uint32_t mask_clk_mask; 120 uint32_t mask_data_mask; 121 uint32_t a_clk_mask; 122 uint32_t a_data_mask; 123 uint32_t en_clk_mask; 124 uint32_t en_data_mask; 125 uint32_t y_clk_mask; 126 uint32_t y_data_mask; 127 }; 128 129 struct radeon_tmds_pll { 130 uint32_t freq; 131 uint32_t value; 132 }; 133 134 #define RADEON_MAX_BIOS_CONNECTOR 16 135 136 /* pll flags */ 137 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 138 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139 #define RADEON_PLL_USE_REF_DIV (1 << 2) 140 #define RADEON_PLL_LEGACY (1 << 3) 141 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 142 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 143 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 144 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 145 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 146 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 147 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 148 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 149 #define RADEON_PLL_USE_POST_DIV (1 << 12) 150 #define RADEON_PLL_IS_LCD (1 << 13) 151 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 152 153 struct radeon_pll { 154 /* reference frequency */ 155 uint32_t reference_freq; 156 157 /* fixed dividers */ 158 uint32_t reference_div; 159 uint32_t post_div; 160 161 /* pll in/out limits */ 162 uint32_t pll_in_min; 163 uint32_t pll_in_max; 164 uint32_t pll_out_min; 165 uint32_t pll_out_max; 166 uint32_t lcd_pll_out_min; 167 uint32_t lcd_pll_out_max; 168 uint32_t best_vco; 169 170 /* divider limits */ 171 uint32_t min_ref_div; 172 uint32_t max_ref_div; 173 uint32_t min_post_div; 174 uint32_t max_post_div; 175 uint32_t min_feedback_div; 176 uint32_t max_feedback_div; 177 uint32_t min_frac_feedback_div; 178 uint32_t max_frac_feedback_div; 179 180 /* flags for the current clock */ 181 uint32_t flags; 182 183 /* pll id */ 184 uint32_t id; 185 }; 186 187 struct radeon_i2c_chan { 188 struct i2c_adapter adapter; 189 struct drm_device *dev; 190 union { 191 struct i2c_algo_bit_data bit; 192 struct i2c_algo_dp_aux_data dp; 193 } algo; 194 struct radeon_i2c_bus_rec rec; 195 }; 196 197 /* mostly for macs, but really any system without connector tables */ 198 enum radeon_connector_table { 199 CT_NONE = 0, 200 CT_GENERIC, 201 CT_IBOOK, 202 CT_POWERBOOK_EXTERNAL, 203 CT_POWERBOOK_INTERNAL, 204 CT_POWERBOOK_VGA, 205 CT_MINI_EXTERNAL, 206 CT_MINI_INTERNAL, 207 CT_IMAC_G5_ISIGHT, 208 CT_EMAC, 209 CT_RN50_POWER, 210 CT_MAC_X800, 211 CT_MAC_G5_9600, 212 CT_SAM440EP 213 }; 214 215 enum radeon_dvo_chip { 216 DVO_SIL164, 217 DVO_SIL1178, 218 }; 219 220 struct radeon_fbdev; 221 222 struct radeon_afmt { 223 bool enabled; 224 int offset; 225 bool last_buffer_filled_status; 226 int id; 227 }; 228 229 struct radeon_mode_info { 230 struct atom_context *atom_context; 231 struct card_info *atom_card_info; 232 enum radeon_connector_table connector_table; 233 bool mode_config_initialized; 234 struct radeon_crtc *crtcs[6]; 235 struct radeon_afmt *afmt[6]; 236 /* DVI-I properties */ 237 struct drm_property *coherent_mode_property; 238 /* DAC enable load detect */ 239 struct drm_property *load_detect_property; 240 /* TV standard */ 241 struct drm_property *tv_std_property; 242 /* legacy TMDS PLL detect */ 243 struct drm_property *tmds_pll_property; 244 /* underscan */ 245 struct drm_property *underscan_property; 246 struct drm_property *underscan_hborder_property; 247 struct drm_property *underscan_vborder_property; 248 /* hardcoded DFP edid from BIOS */ 249 struct edid *bios_hardcoded_edid; 250 int bios_hardcoded_edid_size; 251 252 /* pointer to fbdev info structure */ 253 struct radeon_fbdev *rfbdev; 254 /* firmware flags */ 255 u16 firmware_flags; 256 /* pointer to backlight encoder */ 257 struct radeon_encoder *bl_encoder; 258 }; 259 260 #define RADEON_MAX_BL_LEVEL 0xFF 261 262 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 263 264 struct radeon_backlight_privdata { 265 struct radeon_encoder *encoder; 266 uint8_t negative; 267 }; 268 269 #endif 270 271 #define MAX_H_CODE_TIMING_LEN 32 272 #define MAX_V_CODE_TIMING_LEN 32 273 274 /* need to store these as reading 275 back code tables is excessive */ 276 struct radeon_tv_regs { 277 uint32_t tv_uv_adr; 278 uint32_t timing_cntl; 279 uint32_t hrestart; 280 uint32_t vrestart; 281 uint32_t frestart; 282 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 283 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 284 }; 285 286 struct radeon_atom_ss { 287 uint16_t percentage; 288 uint8_t type; 289 uint16_t step; 290 uint8_t delay; 291 uint8_t range; 292 uint8_t refdiv; 293 /* asic_ss */ 294 uint16_t rate; 295 uint16_t amount; 296 }; 297 298 struct radeon_crtc { 299 struct drm_crtc base; 300 int crtc_id; 301 u16 lut_r[256], lut_g[256], lut_b[256]; 302 bool enabled; 303 bool can_tile; 304 bool in_mode_set; 305 uint32_t crtc_offset; 306 struct drm_gem_object *cursor_bo; 307 uint64_t cursor_addr; 308 int cursor_width; 309 int cursor_height; 310 uint32_t legacy_display_base_addr; 311 uint32_t legacy_cursor_offset; 312 enum radeon_rmx_type rmx_type; 313 u8 h_border; 314 u8 v_border; 315 fixed20_12 vsc; 316 fixed20_12 hsc; 317 struct drm_display_mode native_mode; 318 int pll_id; 319 /* page flipping */ 320 struct radeon_unpin_work *unpin_work; 321 int deferred_flip_completion; 322 /* pll sharing */ 323 struct radeon_atom_ss ss; 324 bool ss_enabled; 325 u32 adjusted_clock; 326 int bpc; 327 u32 pll_reference_div; 328 u32 pll_post_div; 329 u32 pll_flags; 330 struct drm_encoder *encoder; 331 struct drm_connector *connector; 332 }; 333 334 struct radeon_encoder_primary_dac { 335 /* legacy primary dac */ 336 uint32_t ps2_pdac_adj; 337 }; 338 339 struct radeon_encoder_lvds { 340 /* legacy lvds */ 341 uint16_t panel_vcc_delay; 342 uint8_t panel_pwr_delay; 343 uint8_t panel_digon_delay; 344 uint8_t panel_blon_delay; 345 uint16_t panel_ref_divider; 346 uint8_t panel_post_divider; 347 uint16_t panel_fb_divider; 348 bool use_bios_dividers; 349 uint32_t lvds_gen_cntl; 350 /* panel mode */ 351 struct drm_display_mode native_mode; 352 struct backlight_device *bl_dev; 353 int dpms_mode; 354 uint8_t backlight_level; 355 }; 356 357 struct radeon_encoder_tv_dac { 358 /* legacy tv dac */ 359 uint32_t ps2_tvdac_adj; 360 uint32_t ntsc_tvdac_adj; 361 uint32_t pal_tvdac_adj; 362 363 int h_pos; 364 int v_pos; 365 int h_size; 366 int supported_tv_stds; 367 bool tv_on; 368 enum radeon_tv_std tv_std; 369 struct radeon_tv_regs tv; 370 }; 371 372 struct radeon_encoder_int_tmds { 373 /* legacy int tmds */ 374 struct radeon_tmds_pll tmds_pll[4]; 375 }; 376 377 struct radeon_encoder_ext_tmds { 378 /* tmds over dvo */ 379 struct radeon_i2c_chan *i2c_bus; 380 uint8_t slave_addr; 381 enum radeon_dvo_chip dvo_chip; 382 }; 383 384 /* spread spectrum */ 385 struct radeon_encoder_atom_dig { 386 bool linkb; 387 /* atom dig */ 388 bool coherent_mode; 389 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 390 /* atom lvds/edp */ 391 uint32_t lcd_misc; 392 uint16_t panel_pwr_delay; 393 uint32_t lcd_ss_id; 394 /* panel mode */ 395 struct drm_display_mode native_mode; 396 struct backlight_device *bl_dev; 397 int dpms_mode; 398 uint8_t backlight_level; 399 int panel_mode; 400 struct radeon_afmt *afmt; 401 }; 402 403 struct radeon_encoder_atom_dac { 404 enum radeon_tv_std tv_std; 405 }; 406 407 struct radeon_encoder { 408 struct drm_encoder base; 409 uint32_t encoder_enum; 410 uint32_t encoder_id; 411 uint32_t devices; 412 uint32_t active_device; 413 uint32_t flags; 414 uint32_t pixel_clock; 415 enum radeon_rmx_type rmx_type; 416 enum radeon_underscan_type underscan_type; 417 uint32_t underscan_hborder; 418 uint32_t underscan_vborder; 419 struct drm_display_mode native_mode; 420 void *enc_priv; 421 int audio_polling_active; 422 bool is_ext_encoder; 423 u16 caps; 424 }; 425 426 struct radeon_connector_atom_dig { 427 uint32_t igp_lane_info; 428 /* displayport */ 429 struct radeon_i2c_chan *dp_i2c_bus; 430 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 431 u8 dp_sink_type; 432 int dp_clock; 433 int dp_lane_count; 434 bool edp_on; 435 }; 436 437 struct radeon_gpio_rec { 438 bool valid; 439 u8 id; 440 u32 reg; 441 u32 mask; 442 }; 443 444 struct radeon_hpd { 445 enum radeon_hpd_id hpd; 446 u8 plugged_state; 447 struct radeon_gpio_rec gpio; 448 }; 449 450 struct radeon_router { 451 u32 router_id; 452 struct radeon_i2c_bus_rec i2c_info; 453 u8 i2c_addr; 454 /* i2c mux */ 455 bool ddc_valid; 456 u8 ddc_mux_type; 457 u8 ddc_mux_control_pin; 458 u8 ddc_mux_state; 459 /* clock/data mux */ 460 bool cd_valid; 461 u8 cd_mux_type; 462 u8 cd_mux_control_pin; 463 u8 cd_mux_state; 464 }; 465 466 struct radeon_connector { 467 struct drm_connector base; 468 uint32_t connector_id; 469 uint32_t devices; 470 struct radeon_i2c_chan *ddc_bus; 471 /* some systems have an hdmi and vga port with a shared ddc line */ 472 bool shared_ddc; 473 bool use_digital; 474 /* we need to mind the EDID between detect 475 and get modes due to analog/digital/tvencoder */ 476 struct edid *edid; 477 void *con_priv; 478 bool dac_load_detect; 479 bool detected_by_load; /* if the connection status was determined by load */ 480 uint16_t connector_object_id; 481 struct radeon_hpd hpd; 482 struct radeon_router router; 483 struct radeon_i2c_chan *router_bus; 484 }; 485 486 struct radeon_framebuffer { 487 struct drm_framebuffer base; 488 struct drm_gem_object *obj; 489 }; 490 491 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 492 ((em) == ATOM_ENCODER_MODE_DP_MST)) 493 494 extern enum radeon_tv_std 495 radeon_combios_get_tv_info(struct radeon_device *rdev); 496 extern enum radeon_tv_std 497 radeon_atombios_get_tv_info(struct radeon_device *rdev); 498 499 extern struct drm_connector * 500 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 501 extern struct drm_connector * 502 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 503 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 504 u32 pixel_clock); 505 506 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 507 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 508 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 509 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 510 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 511 512 extern void radeon_connector_hotplug(struct drm_connector *connector); 513 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 514 struct drm_display_mode *mode); 515 extern void radeon_dp_set_link_config(struct drm_connector *connector, 516 const struct drm_display_mode *mode); 517 extern void radeon_dp_link_train(struct drm_encoder *encoder, 518 struct drm_connector *connector); 519 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 520 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 521 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 522 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 523 struct drm_connector *connector); 524 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 525 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 526 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 527 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 528 int action, uint8_t lane_num, 529 uint8_t lane_set); 530 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 531 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 532 extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 533 u8 write_byte, u8 *read_byte); 534 535 extern void radeon_i2c_init(struct radeon_device *rdev); 536 extern void radeon_i2c_fini(struct radeon_device *rdev); 537 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 538 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 539 extern void radeon_i2c_add(struct radeon_device *rdev, 540 struct radeon_i2c_bus_rec *rec, 541 const char *name); 542 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 543 struct radeon_i2c_bus_rec *i2c_bus); 544 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 545 struct radeon_i2c_bus_rec *rec, 546 const char *name); 547 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 548 struct radeon_i2c_bus_rec *rec, 549 const char *name); 550 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 551 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 552 u8 slave_addr, 553 u8 addr, 554 u8 *val); 555 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 556 u8 slave_addr, 557 u8 addr, 558 u8 val); 559 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 560 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 561 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 562 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 563 564 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 565 566 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 567 struct radeon_atom_ss *ss, 568 int id); 569 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 570 struct radeon_atom_ss *ss, 571 int id, u32 clock); 572 573 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 574 uint64_t freq, 575 uint32_t *dot_clock_p, 576 uint32_t *fb_div_p, 577 uint32_t *frac_fb_div_p, 578 uint32_t *ref_div_p, 579 uint32_t *post_div_p); 580 581 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 582 u32 freq, 583 u32 *dot_clock_p, 584 u32 *fb_div_p, 585 u32 *frac_fb_div_p, 586 u32 *ref_div_p, 587 u32 *post_div_p); 588 589 extern void radeon_setup_encoder_clones(struct drm_device *dev); 590 591 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 592 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 593 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 594 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 595 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 596 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 597 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 598 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 599 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 600 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 601 602 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 603 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 604 struct drm_framebuffer *old_fb); 605 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 606 struct drm_framebuffer *fb, 607 int x, int y, 608 enum mode_set_atomic state); 609 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 610 struct drm_display_mode *mode, 611 struct drm_display_mode *adjusted_mode, 612 int x, int y, 613 struct drm_framebuffer *old_fb); 614 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 615 616 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 617 struct drm_framebuffer *old_fb); 618 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 619 struct drm_framebuffer *fb, 620 int x, int y, 621 enum mode_set_atomic state); 622 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 623 struct drm_framebuffer *fb, 624 int x, int y, int atomic); 625 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 626 struct drm_file *file_priv, 627 uint32_t handle, 628 uint32_t width, 629 uint32_t height); 630 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 631 int x, int y); 632 633 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 634 int *vpos, int *hpos); 635 636 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 637 extern struct edid * 638 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 639 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 640 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 641 extern struct radeon_encoder_atom_dig * 642 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 643 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 644 struct radeon_encoder_int_tmds *tmds); 645 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 646 struct radeon_encoder_int_tmds *tmds); 647 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 648 struct radeon_encoder_int_tmds *tmds); 649 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 650 struct radeon_encoder_ext_tmds *tmds); 651 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 652 struct radeon_encoder_ext_tmds *tmds); 653 extern struct radeon_encoder_primary_dac * 654 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 655 extern struct radeon_encoder_tv_dac * 656 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 657 extern struct radeon_encoder_lvds * 658 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 659 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 660 extern struct radeon_encoder_tv_dac * 661 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 662 extern struct radeon_encoder_primary_dac * 663 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 664 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 665 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 666 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 667 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 668 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 669 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 670 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 671 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 672 extern void 673 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 674 extern void 675 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 676 extern void 677 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 678 extern void 679 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 680 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 681 u16 blue, int regno); 682 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 683 u16 *blue, int regno); 684 int radeon_framebuffer_init(struct drm_device *dev, 685 struct radeon_framebuffer *rfb, 686 struct drm_mode_fb_cmd2 *mode_cmd, 687 struct drm_gem_object *obj); 688 689 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 690 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 691 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 692 void radeon_atombios_init_crtc(struct drm_device *dev, 693 struct radeon_crtc *radeon_crtc); 694 void radeon_legacy_init_crtc(struct drm_device *dev, 695 struct radeon_crtc *radeon_crtc); 696 697 void radeon_get_clock_info(struct drm_device *dev); 698 699 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 700 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 701 702 void radeon_enc_destroy(struct drm_encoder *encoder); 703 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 704 void radeon_combios_asic_init(struct drm_device *dev); 705 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 706 const struct drm_display_mode *mode, 707 struct drm_display_mode *adjusted_mode); 708 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 709 struct drm_display_mode *adjusted_mode); 710 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 711 712 /* legacy tv */ 713 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 714 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 715 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 716 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 717 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 718 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 719 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 720 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 721 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 722 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 723 struct drm_display_mode *mode, 724 struct drm_display_mode *adjusted_mode); 725 726 /* fbdev layer */ 727 int radeon_fbdev_init(struct radeon_device *rdev); 728 void radeon_fbdev_fini(struct radeon_device *rdev); 729 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 730 int radeon_fbdev_total_size(struct radeon_device *rdev); 731 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 732 733 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 734 735 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 736 737 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 738 #endif 739