1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Original Authors: 25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 26 * 27 * Kernel port Author: Dave Airlie 28 */ 29 30 #ifndef RADEON_MODE_H 31 #define RADEON_MODE_H 32 33 #include <drm/display/drm_dp_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_encoder.h> 36 #include <drm/drm_fixed.h> 37 #include <drm/drm_modeset_helper_vtables.h> 38 #include <linux/i2c.h> 39 #include <linux/i2c-algo-bit.h> 40 41 struct drm_fb_helper; 42 struct drm_fb_helper_surface_size; 43 struct drm_format_info; 44 45 struct edid; 46 struct drm_edid; 47 struct radeon_bo; 48 struct radeon_device; 49 50 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 51 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 52 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 53 54 #define RADEON_MAX_HPD_PINS 7 55 #define RADEON_MAX_CRTCS 6 56 #define RADEON_MAX_AFMT_BLOCKS 7 57 58 enum radeon_rmx_type { 59 RMX_OFF, 60 RMX_FULL, 61 RMX_CENTER, 62 RMX_ASPECT 63 }; 64 65 enum radeon_tv_std { 66 TV_STD_NTSC, 67 TV_STD_PAL, 68 TV_STD_PAL_M, 69 TV_STD_PAL_60, 70 TV_STD_NTSC_J, 71 TV_STD_SCART_PAL, 72 TV_STD_SECAM, 73 TV_STD_PAL_CN, 74 TV_STD_PAL_N, 75 }; 76 77 enum radeon_underscan_type { 78 UNDERSCAN_OFF, 79 UNDERSCAN_ON, 80 UNDERSCAN_AUTO, 81 }; 82 83 enum radeon_hpd_id { 84 RADEON_HPD_1 = 0, 85 RADEON_HPD_2, 86 RADEON_HPD_3, 87 RADEON_HPD_4, 88 RADEON_HPD_5, 89 RADEON_HPD_6, 90 RADEON_HPD_NONE = 0xff, 91 }; 92 93 enum radeon_output_csc { 94 RADEON_OUTPUT_CSC_BYPASS = 0, 95 RADEON_OUTPUT_CSC_TVRGB = 1, 96 RADEON_OUTPUT_CSC_YCBCR601 = 2, 97 RADEON_OUTPUT_CSC_YCBCR709 = 3, 98 }; 99 100 #define RADEON_MAX_I2C_BUS 16 101 102 /* radeon gpio-based i2c 103 * 1. "mask" reg and bits 104 * grabs the gpio pins for software use 105 * 0=not held 1=held 106 * 2. "a" reg and bits 107 * output pin value 108 * 0=low 1=high 109 * 3. "en" reg and bits 110 * sets the pin direction 111 * 0=input 1=output 112 * 4. "y" reg and bits 113 * input pin value 114 * 0=low 1=high 115 */ 116 struct radeon_i2c_bus_rec { 117 bool valid; 118 /* id used by atom */ 119 uint8_t i2c_id; 120 /* id used by atom */ 121 enum radeon_hpd_id hpd; 122 /* can be used with hw i2c engine */ 123 bool hw_capable; 124 /* uses multi-media i2c engine */ 125 bool mm_i2c; 126 /* regs and bits */ 127 uint32_t mask_clk_reg; 128 uint32_t mask_data_reg; 129 uint32_t a_clk_reg; 130 uint32_t a_data_reg; 131 uint32_t en_clk_reg; 132 uint32_t en_data_reg; 133 uint32_t y_clk_reg; 134 uint32_t y_data_reg; 135 uint32_t mask_clk_mask; 136 uint32_t mask_data_mask; 137 uint32_t a_clk_mask; 138 uint32_t a_data_mask; 139 uint32_t en_clk_mask; 140 uint32_t en_data_mask; 141 uint32_t y_clk_mask; 142 uint32_t y_data_mask; 143 }; 144 145 struct radeon_tmds_pll { 146 uint32_t freq; 147 uint32_t value; 148 }; 149 150 #define RADEON_MAX_BIOS_CONNECTOR 16 151 152 /* pll flags */ 153 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 154 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 155 #define RADEON_PLL_USE_REF_DIV (1 << 2) 156 #define RADEON_PLL_LEGACY (1 << 3) 157 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 158 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 159 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 160 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 161 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 162 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 163 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 164 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 165 #define RADEON_PLL_USE_POST_DIV (1 << 12) 166 #define RADEON_PLL_IS_LCD (1 << 13) 167 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 168 169 struct radeon_pll { 170 /* reference frequency */ 171 uint32_t reference_freq; 172 173 /* fixed dividers */ 174 uint32_t reference_div; 175 uint32_t post_div; 176 177 /* pll in/out limits */ 178 uint32_t pll_in_min; 179 uint32_t pll_in_max; 180 uint32_t pll_out_min; 181 uint32_t pll_out_max; 182 uint32_t lcd_pll_out_min; 183 uint32_t lcd_pll_out_max; 184 uint32_t best_vco; 185 186 /* divider limits */ 187 uint32_t min_ref_div; 188 uint32_t max_ref_div; 189 uint32_t min_post_div; 190 uint32_t max_post_div; 191 uint32_t min_feedback_div; 192 uint32_t max_feedback_div; 193 uint32_t min_frac_feedback_div; 194 uint32_t max_frac_feedback_div; 195 196 /* flags for the current clock */ 197 uint32_t flags; 198 199 /* pll id */ 200 uint32_t id; 201 }; 202 203 struct radeon_i2c_chan { 204 struct i2c_adapter adapter; 205 struct drm_device *dev; 206 struct i2c_algo_bit_data bit; 207 struct radeon_i2c_bus_rec rec; 208 struct drm_dp_aux aux; 209 bool has_aux; 210 struct mutex mutex; 211 }; 212 213 /* mostly for macs, but really any system without connector tables */ 214 enum radeon_connector_table { 215 CT_NONE = 0, 216 CT_GENERIC, 217 CT_IBOOK, 218 CT_POWERBOOK_EXTERNAL, 219 CT_POWERBOOK_INTERNAL, 220 CT_POWERBOOK_VGA, 221 CT_MINI_EXTERNAL, 222 CT_MINI_INTERNAL, 223 CT_IMAC_G5_ISIGHT, 224 CT_EMAC, 225 CT_RN50_POWER, 226 CT_MAC_X800, 227 CT_MAC_G5_9600, 228 CT_SAM440EP, 229 CT_MAC_G4_SILVER 230 }; 231 232 enum radeon_dvo_chip { 233 DVO_SIL164, 234 DVO_SIL1178, 235 }; 236 237 struct radeon_afmt { 238 bool enabled; 239 int offset; 240 bool last_buffer_filled_status; 241 int id; 242 }; 243 244 struct radeon_mode_info { 245 struct atom_context *atom_context; 246 struct card_info *atom_card_info; 247 enum radeon_connector_table connector_table; 248 bool mode_config_initialized; 249 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS]; 250 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS]; 251 /* DVI-I properties */ 252 struct drm_property *coherent_mode_property; 253 /* DAC enable load detect */ 254 struct drm_property *load_detect_property; 255 /* TV standard */ 256 struct drm_property *tv_std_property; 257 /* legacy TMDS PLL detect */ 258 struct drm_property *tmds_pll_property; 259 /* underscan */ 260 struct drm_property *underscan_property; 261 struct drm_property *underscan_hborder_property; 262 struct drm_property *underscan_vborder_property; 263 /* audio */ 264 struct drm_property *audio_property; 265 /* FMT dithering */ 266 struct drm_property *dither_property; 267 /* Output CSC */ 268 struct drm_property *output_csc_property; 269 /* hardcoded DFP edid from BIOS */ 270 const struct drm_edid *bios_hardcoded_edid; 271 272 /* firmware flags */ 273 u16 firmware_flags; 274 /* pointer to backlight encoder */ 275 struct radeon_encoder *bl_encoder; 276 277 /* bitmask for active encoder frontends */ 278 uint32_t active_encoders; 279 }; 280 281 #define RADEON_MAX_BL_LEVEL 0xFF 282 283 struct radeon_backlight_privdata { 284 struct radeon_encoder *encoder; 285 uint8_t negative; 286 }; 287 288 #define MAX_H_CODE_TIMING_LEN 32 289 #define MAX_V_CODE_TIMING_LEN 32 290 291 /* need to store these as reading 292 back code tables is excessive */ 293 struct radeon_tv_regs { 294 uint32_t tv_uv_adr; 295 uint32_t timing_cntl; 296 uint32_t hrestart; 297 uint32_t vrestart; 298 uint32_t frestart; 299 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 300 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 301 }; 302 303 struct radeon_atom_ss { 304 uint16_t percentage; 305 uint16_t percentage_divider; 306 uint8_t type; 307 uint16_t step; 308 uint8_t delay; 309 uint8_t range; 310 uint8_t refdiv; 311 /* asic_ss */ 312 uint16_t rate; 313 uint16_t amount; 314 }; 315 316 enum radeon_flip_status { 317 RADEON_FLIP_NONE, 318 RADEON_FLIP_PENDING, 319 RADEON_FLIP_SUBMITTED 320 }; 321 322 struct radeon_crtc { 323 struct drm_crtc base; 324 int crtc_id; 325 bool enabled; 326 bool can_tile; 327 bool cursor_out_of_bounds; 328 uint32_t crtc_offset; 329 struct drm_gem_object *cursor_bo; 330 uint64_t cursor_addr; 331 int cursor_x; 332 int cursor_y; 333 int cursor_hot_x; 334 int cursor_hot_y; 335 int cursor_width; 336 int cursor_height; 337 int max_cursor_width; 338 int max_cursor_height; 339 uint32_t legacy_display_base_addr; 340 enum radeon_rmx_type rmx_type; 341 u8 h_border; 342 u8 v_border; 343 fixed20_12 vsc; 344 fixed20_12 hsc; 345 struct drm_display_mode native_mode; 346 int pll_id; 347 /* page flipping */ 348 struct workqueue_struct *flip_queue; 349 struct radeon_flip_work *flip_work; 350 enum radeon_flip_status flip_status; 351 /* pll sharing */ 352 struct radeon_atom_ss ss; 353 bool ss_enabled; 354 u32 adjusted_clock; 355 int bpc; 356 u32 pll_reference_div; 357 u32 pll_post_div; 358 u32 pll_flags; 359 struct drm_encoder *encoder; 360 struct drm_connector *connector; 361 /* for dpm */ 362 u32 line_time; 363 u32 wm_low; 364 u32 wm_high; 365 u32 lb_vblank_lead_lines; 366 struct drm_display_mode hw_mode; 367 enum radeon_output_csc output_csc; 368 }; 369 370 struct radeon_encoder_primary_dac { 371 /* legacy primary dac */ 372 uint32_t ps2_pdac_adj; 373 }; 374 375 struct radeon_encoder_lvds { 376 /* legacy lvds */ 377 uint16_t panel_vcc_delay; 378 uint8_t panel_pwr_delay; 379 uint8_t panel_digon_delay; 380 uint8_t panel_blon_delay; 381 uint16_t panel_ref_divider; 382 uint8_t panel_post_divider; 383 uint16_t panel_fb_divider; 384 bool use_bios_dividers; 385 uint32_t lvds_gen_cntl; 386 /* panel mode */ 387 struct drm_display_mode native_mode; 388 struct backlight_device *bl_dev; 389 int dpms_mode; 390 uint8_t backlight_level; 391 }; 392 393 struct radeon_encoder_tv_dac { 394 /* legacy tv dac */ 395 uint32_t ps2_tvdac_adj; 396 uint32_t ntsc_tvdac_adj; 397 uint32_t pal_tvdac_adj; 398 399 int h_pos; 400 int v_pos; 401 int h_size; 402 int supported_tv_stds; 403 bool tv_on; 404 enum radeon_tv_std tv_std; 405 struct radeon_tv_regs tv; 406 }; 407 408 struct radeon_encoder_int_tmds { 409 /* legacy int tmds */ 410 struct radeon_tmds_pll tmds_pll[4]; 411 }; 412 413 struct radeon_encoder_ext_tmds { 414 /* tmds over dvo */ 415 struct radeon_i2c_chan *i2c_bus; 416 uint8_t slave_addr; 417 enum radeon_dvo_chip dvo_chip; 418 }; 419 420 /* spread spectrum */ 421 struct radeon_encoder_atom_dig { 422 bool linkb; 423 /* atom dig */ 424 bool coherent_mode; 425 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 426 /* atom lvds/edp */ 427 uint32_t lcd_misc; 428 uint16_t panel_pwr_delay; 429 uint32_t lcd_ss_id; 430 /* panel mode */ 431 struct drm_display_mode native_mode; 432 struct backlight_device *bl_dev; 433 int dpms_mode; 434 uint8_t backlight_level; 435 int panel_mode; 436 struct radeon_afmt *afmt; 437 struct r600_audio_pin *pin; 438 }; 439 440 struct radeon_encoder_atom_dac { 441 enum radeon_tv_std tv_std; 442 }; 443 444 struct radeon_encoder { 445 struct drm_encoder base; 446 uint32_t encoder_enum; 447 uint32_t encoder_id; 448 uint32_t devices; 449 uint32_t active_device; 450 uint32_t flags; 451 uint32_t pixel_clock; 452 enum radeon_rmx_type rmx_type; 453 enum radeon_underscan_type underscan_type; 454 uint32_t underscan_hborder; 455 uint32_t underscan_vborder; 456 struct drm_display_mode native_mode; 457 void *enc_priv; 458 int audio_polling_active; 459 bool is_ext_encoder; 460 u16 caps; 461 struct radeon_audio_funcs *audio; 462 enum radeon_output_csc output_csc; 463 bool can_mst; 464 uint32_t offset; 465 }; 466 467 struct radeon_connector_atom_dig { 468 uint32_t igp_lane_info; 469 /* displayport */ 470 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 471 u8 dp_sink_type; 472 int dp_clock; 473 int dp_lane_count; 474 bool edp_on; 475 }; 476 477 struct radeon_gpio_rec { 478 bool valid; 479 u8 id; 480 u32 reg; 481 u32 mask; 482 u32 shift; 483 }; 484 485 struct radeon_hpd { 486 enum radeon_hpd_id hpd; 487 u8 plugged_state; 488 struct radeon_gpio_rec gpio; 489 }; 490 491 struct radeon_router { 492 u32 router_id; 493 struct radeon_i2c_bus_rec i2c_info; 494 u8 i2c_addr; 495 /* i2c mux */ 496 bool ddc_valid; 497 u8 ddc_mux_type; 498 u8 ddc_mux_control_pin; 499 u8 ddc_mux_state; 500 /* clock/data mux */ 501 bool cd_valid; 502 u8 cd_mux_type; 503 u8 cd_mux_control_pin; 504 u8 cd_mux_state; 505 }; 506 507 enum radeon_connector_audio { 508 RADEON_AUDIO_DISABLE = 0, 509 RADEON_AUDIO_ENABLE = 1, 510 RADEON_AUDIO_AUTO = 2 511 }; 512 513 enum radeon_connector_dither { 514 RADEON_FMT_DITHER_DISABLE = 0, 515 RADEON_FMT_DITHER_ENABLE = 1, 516 }; 517 518 struct radeon_connector { 519 struct drm_connector base; 520 uint32_t connector_id; 521 uint32_t devices; 522 struct radeon_i2c_chan *ddc_bus; 523 /* some systems have an hdmi and vga port with a shared ddc line */ 524 bool shared_ddc; 525 bool use_digital; 526 /* we need to mind the EDID between detect 527 and get modes due to analog/digital/tvencoder */ 528 struct edid *edid; 529 void *con_priv; 530 bool dac_load_detect; 531 bool detected_by_load; /* if the connection status was determined by load */ 532 bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */ 533 uint16_t connector_object_id; 534 struct radeon_hpd hpd; 535 struct radeon_router router; 536 struct radeon_i2c_chan *router_bus; 537 enum radeon_connector_audio audio; 538 enum radeon_connector_dither dither; 539 int pixelclock_for_modeset; 540 }; 541 542 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 543 ((em) == ATOM_ENCODER_MODE_DP_MST)) 544 545 struct atom_clock_dividers { 546 u32 post_div; 547 union { 548 struct { 549 #ifdef __BIG_ENDIAN 550 u32 reserved : 6; 551 u32 whole_fb_div : 12; 552 u32 frac_fb_div : 14; 553 #else 554 u32 frac_fb_div : 14; 555 u32 whole_fb_div : 12; 556 u32 reserved : 6; 557 #endif 558 }; 559 u32 fb_div; 560 }; 561 u32 ref_div; 562 bool enable_post_div; 563 bool enable_dithen; 564 u32 vco_mode; 565 u32 real_clock; 566 /* added for CI */ 567 u32 post_divider; 568 u32 flags; 569 }; 570 571 struct atom_mpll_param { 572 union { 573 struct { 574 #ifdef __BIG_ENDIAN 575 u32 reserved : 8; 576 u32 clkfrac : 12; 577 u32 clkf : 12; 578 #else 579 u32 clkf : 12; 580 u32 clkfrac : 12; 581 u32 reserved : 8; 582 #endif 583 }; 584 u32 fb_div; 585 }; 586 u32 post_div; 587 u32 bwcntl; 588 u32 dll_speed; 589 u32 vco_mode; 590 u32 yclk_sel; 591 u32 qdr; 592 u32 half_rate; 593 }; 594 595 #define MEM_TYPE_GDDR5 0x50 596 #define MEM_TYPE_GDDR4 0x40 597 #define MEM_TYPE_GDDR3 0x30 598 #define MEM_TYPE_DDR2 0x20 599 #define MEM_TYPE_GDDR1 0x10 600 #define MEM_TYPE_DDR3 0xb0 601 #define MEM_TYPE_MASK 0xf0 602 603 struct atom_memory_info { 604 u8 mem_vendor; 605 u8 mem_type; 606 }; 607 608 #define MAX_AC_TIMING_ENTRIES 16 609 610 struct atom_memory_clock_range_table { 611 u8 num_entries; 612 u8 rsv[3]; 613 u32 mclk[MAX_AC_TIMING_ENTRIES]; 614 }; 615 616 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 617 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 618 619 struct atom_mc_reg_entry { 620 u32 mclk_max; 621 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 622 }; 623 624 struct atom_mc_register_address { 625 u16 s1; 626 u8 pre_reg_data; 627 }; 628 629 struct atom_mc_reg_table { 630 u8 last; 631 u8 num_entries; 632 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 633 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 634 }; 635 636 #define MAX_VOLTAGE_ENTRIES 32 637 638 struct atom_voltage_table_entry { 639 u16 value; 640 u32 smio_low; 641 }; 642 643 struct atom_voltage_table { 644 u32 count; 645 u32 mask_low; 646 u32 phase_delay; 647 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES]; 648 }; 649 650 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ 651 #define DRM_SCANOUTPOS_VALID (1 << 0) 652 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1) 653 #define DRM_SCANOUTPOS_ACCURATE (1 << 2) 654 #define USE_REAL_VBLANKSTART (1 << 30) 655 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 656 657 extern void 658 radeon_add_atom_connector(struct drm_device *dev, 659 uint32_t connector_id, 660 uint32_t supported_device, 661 int connector_type, 662 struct radeon_i2c_bus_rec *i2c_bus, 663 uint32_t igp_lane_info, 664 uint16_t connector_object_id, 665 struct radeon_hpd *hpd, 666 struct radeon_router *router); 667 extern void 668 radeon_add_legacy_connector(struct drm_device *dev, 669 uint32_t connector_id, 670 uint32_t supported_device, 671 int connector_type, 672 struct radeon_i2c_bus_rec *i2c_bus, 673 uint16_t connector_object_id, 674 struct radeon_hpd *hpd); 675 extern uint32_t 676 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 677 uint8_t dac); 678 extern void radeon_link_encoder_connector(struct drm_device *dev); 679 680 extern enum radeon_tv_std 681 radeon_combios_get_tv_info(struct radeon_device *rdev); 682 extern enum radeon_tv_std 683 radeon_atombios_get_tv_info(struct radeon_device *rdev); 684 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 685 u16 *vddc, u16 *vddci, u16 *mvdd); 686 687 extern void 688 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 689 struct drm_encoder *encoder, 690 bool connected); 691 extern void 692 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 693 struct drm_encoder *encoder, 694 bool connected); 695 696 extern struct drm_connector * 697 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 698 extern struct drm_connector * 699 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 700 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 701 u32 pixel_clock); 702 703 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 704 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 705 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 706 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 707 708 extern void radeon_connector_hotplug(struct drm_connector *connector); 709 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 710 const struct drm_display_mode *mode); 711 extern void radeon_dp_set_link_config(struct drm_connector *connector, 712 const struct drm_display_mode *mode); 713 extern void radeon_dp_link_train(struct drm_encoder *encoder, 714 struct drm_connector *connector); 715 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 716 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 717 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 718 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 719 struct drm_connector *connector); 720 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector, 721 u8 power_state); 722 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector); 723 extern ssize_t 724 radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); 725 726 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 727 extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override); 728 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 729 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 730 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 731 int action, uint8_t lane_num, 732 uint8_t lane_set); 733 extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder, 734 int action, uint8_t lane_num, 735 uint8_t lane_set, int fe); 736 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 737 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 738 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le); 739 740 extern void radeon_i2c_init(struct radeon_device *rdev); 741 extern void radeon_i2c_fini(struct radeon_device *rdev); 742 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 743 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 744 extern void radeon_i2c_add(struct radeon_device *rdev, 745 struct radeon_i2c_bus_rec *rec, 746 const char *name); 747 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 748 struct radeon_i2c_bus_rec *i2c_bus); 749 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 750 struct radeon_i2c_bus_rec *rec, 751 const char *name); 752 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 753 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 754 u8 slave_addr, 755 u8 addr, 756 u8 *val); 757 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 758 u8 slave_addr, 759 u8 addr, 760 u8 val); 761 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 762 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 763 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 764 765 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 766 struct radeon_atom_ss *ss, 767 int id); 768 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 769 struct radeon_atom_ss *ss, 770 int id, u32 clock); 771 extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 772 u8 id); 773 774 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 775 uint64_t freq, 776 uint32_t *dot_clock_p, 777 uint32_t *fb_div_p, 778 uint32_t *frac_fb_div_p, 779 uint32_t *ref_div_p, 780 uint32_t *post_div_p); 781 782 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 783 u32 freq, 784 u32 *dot_clock_p, 785 u32 *fb_div_p, 786 u32 *frac_fb_div_p, 787 u32 *ref_div_p, 788 u32 *post_div_p); 789 790 extern void radeon_setup_encoder_clones(struct drm_device *dev); 791 792 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 793 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 794 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 795 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 796 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 797 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 798 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 799 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 800 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 801 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 802 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder); 803 804 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 805 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 806 struct drm_framebuffer *old_fb); 807 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 808 struct drm_framebuffer *fb, 809 int x, int y, 810 enum mode_set_atomic state); 811 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 812 struct drm_display_mode *mode, 813 struct drm_display_mode *adjusted_mode, 814 int x, int y, 815 struct drm_framebuffer *old_fb); 816 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 817 818 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 819 struct drm_framebuffer *old_fb); 820 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 821 struct drm_framebuffer *fb, 822 int x, int y, 823 enum mode_set_atomic state); 824 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 825 struct drm_framebuffer *fb, 826 int x, int y, int atomic); 827 extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 828 struct drm_file *file_priv, 829 uint32_t handle, 830 uint32_t width, 831 uint32_t height, 832 int32_t hot_x, 833 int32_t hot_y); 834 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 835 int x, int y); 836 extern void radeon_cursor_reset(struct drm_crtc *crtc); 837 838 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 839 unsigned int flags, int *vpos, int *hpos, 840 ktime_t *stime, ktime_t *etime, 841 const struct drm_display_mode *mode); 842 843 extern bool 844 radeon_get_crtc_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, 845 int *vpos, int *hpos, 846 ktime_t *stime, ktime_t *etime, 847 const struct drm_display_mode *mode); 848 849 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 850 extern struct edid * 851 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 852 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 853 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 854 extern struct radeon_encoder_atom_dig * 855 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 856 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 857 struct radeon_encoder_int_tmds *tmds); 858 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 859 struct radeon_encoder_int_tmds *tmds); 860 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 861 struct radeon_encoder_int_tmds *tmds); 862 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 863 struct radeon_encoder_ext_tmds *tmds); 864 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 865 struct radeon_encoder_ext_tmds *tmds); 866 extern struct radeon_encoder_primary_dac * 867 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 868 extern struct radeon_encoder_tv_dac * 869 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 870 extern struct radeon_encoder_lvds * 871 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 872 extern struct radeon_encoder_tv_dac * 873 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 874 extern struct radeon_encoder_primary_dac * 875 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 876 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 877 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 878 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 879 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 880 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 881 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 882 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 883 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 884 extern void 885 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 886 extern void 887 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 888 extern void 889 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 890 extern void 891 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 892 int radeon_framebuffer_init(struct drm_device *dev, 893 struct drm_framebuffer *rfb, 894 const struct drm_format_info *info, 895 const struct drm_mode_fb_cmd2 *mode_cmd, 896 struct drm_gem_object *obj); 897 898 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 899 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 900 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 901 void radeon_atombios_init_crtc(struct drm_device *dev, 902 struct radeon_crtc *radeon_crtc); 903 void radeon_legacy_init_crtc(struct drm_device *dev, 904 struct radeon_crtc *radeon_crtc); 905 906 void radeon_get_clock_info(struct drm_device *dev); 907 908 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 909 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 910 911 void radeon_enc_destroy(struct drm_encoder *encoder); 912 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 913 void radeon_combios_asic_init(struct drm_device *dev); 914 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 915 const struct drm_display_mode *mode, 916 struct drm_display_mode *adjusted_mode); 917 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 918 struct drm_display_mode *adjusted_mode); 919 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 920 921 /* legacy tv */ 922 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 923 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 924 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 925 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 926 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 927 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 928 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 929 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 930 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 931 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 932 struct drm_display_mode *mode, 933 struct drm_display_mode *adjusted_mode); 934 935 /* fmt blocks */ 936 void avivo_program_fmt(struct drm_encoder *encoder); 937 void dce3_program_fmt(struct drm_encoder *encoder); 938 void dce4_program_fmt(struct drm_encoder *encoder); 939 void dce8_program_fmt(struct drm_encoder *encoder); 940 941 /* fbdev layer */ 942 #if defined(CONFIG_DRM_FBDEV_EMULATION) 943 int radeon_fbdev_driver_fbdev_probe(struct drm_fb_helper *fb_helper, 944 struct drm_fb_helper_surface_size *sizes); 945 #define RADEON_FBDEV_DRIVER_OPS \ 946 .fbdev_probe = radeon_fbdev_driver_fbdev_probe 947 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 948 #else 949 #define RADEON_FBDEV_DRIVER_OPS \ 950 .fbdev_probe = NULL 951 static inline bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) 952 { 953 return false; 954 } 955 #endif 956 957 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); 958 959 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 960 961 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx); 962 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx); 963 #endif 964