1 // SPDX-License-Identifier: MIT 2 3 #include <drm/drm_crtc_helper.h> 4 #include <drm/drm_device.h> 5 6 #include "radeon.h" 7 8 /* 9 * Integrated TV out support based on the GATOS code by 10 * Federico Ulivi <fulivi@lycos.com> 11 */ 12 13 14 /* 15 * Limits of h/v positions (hPos & vPos) 16 */ 17 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 18 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 19 20 /* 21 * Unit for hPos (in TV clock periods) 22 */ 23 #define H_POS_UNIT 10 24 25 /* 26 * Indexes in h. code timing table for horizontal line position adjustment 27 */ 28 #define H_TABLE_POS1 6 29 #define H_TABLE_POS2 8 30 31 /* 32 * Limits of hor. size (hSize) 33 */ 34 #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 35 36 /* tv standard constants */ 37 #define NTSC_TV_CLOCK_T 233 38 #define NTSC_TV_VFTOTAL 1 39 #define NTSC_TV_LINES_PER_FRAME 525 40 #define NTSC_TV_ZERO_H_SIZE 479166 41 #define NTSC_TV_H_SIZE_UNIT 9478 42 43 #define PAL_TV_CLOCK_T 188 44 #define PAL_TV_VFTOTAL 3 45 #define PAL_TV_LINES_PER_FRAME 625 46 #define PAL_TV_ZERO_H_SIZE 473200 47 #define PAL_TV_H_SIZE_UNIT 9360 48 49 /* tv pll setting for 27 mhz ref clk */ 50 #define NTSC_TV_PLL_M_27 22 51 #define NTSC_TV_PLL_N_27 175 52 #define NTSC_TV_PLL_P_27 5 53 54 #define PAL_TV_PLL_M_27 113 55 #define PAL_TV_PLL_N_27 668 56 #define PAL_TV_PLL_P_27 3 57 58 /* tv pll setting for 14 mhz ref clk */ 59 #define NTSC_TV_PLL_M_14 33 60 #define NTSC_TV_PLL_N_14 693 61 #define NTSC_TV_PLL_P_14 7 62 63 #define PAL_TV_PLL_M_14 19 64 #define PAL_TV_PLL_N_14 353 65 #define PAL_TV_PLL_P_14 5 66 67 #define VERT_LEAD_IN_LINES 2 68 #define FRAC_BITS 0xe 69 #define FRAC_MASK 0x3fff 70 71 struct radeon_tv_mode_constants { 72 uint16_t hor_resolution; 73 uint16_t ver_resolution; 74 enum radeon_tv_std standard; 75 uint16_t hor_total; 76 uint16_t ver_total; 77 uint16_t hor_start; 78 uint16_t hor_syncstart; 79 uint16_t ver_syncstart; 80 unsigned def_restart; 81 uint16_t crtcPLL_N; 82 uint8_t crtcPLL_M; 83 uint8_t crtcPLL_post_div; 84 unsigned pix_to_tv; 85 }; 86 87 static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 88 0x0007, 89 0x003f, 90 0x0263, 91 0x0a24, 92 0x2a6b, 93 0x0a36, 94 0x126d, /* H_TABLE_POS1 */ 95 0x1bfe, 96 0x1a8f, /* H_TABLE_POS2 */ 97 0x1ec7, 98 0x3863, 99 0x1bfe, 100 0x1bfe, 101 0x1a2a, 102 0x1e95, 103 0x0e31, 104 0x201b, 105 0 106 }; 107 108 static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 109 0x2001, 110 0x200d, 111 0x1006, 112 0x0c06, 113 0x1006, 114 0x1818, 115 0x21e3, 116 0x1006, 117 0x0c06, 118 0x1006, 119 0x1817, 120 0x21d4, 121 0x0002, 122 0 123 }; 124 125 static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 126 0x0007, 127 0x0058, 128 0x027c, 129 0x0a31, 130 0x2a77, 131 0x0a95, 132 0x124f, /* H_TABLE_POS1 */ 133 0x1bfe, 134 0x1b22, /* H_TABLE_POS2 */ 135 0x1ef9, 136 0x387c, 137 0x1bfe, 138 0x1bfe, 139 0x1b31, 140 0x1eb5, 141 0x0e43, 142 0x201b, 143 0 144 }; 145 146 static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 147 0x2001, 148 0x200c, 149 0x1005, 150 0x0c05, 151 0x1005, 152 0x1401, 153 0x1821, 154 0x2240, 155 0x1005, 156 0x0c05, 157 0x1005, 158 0x1401, 159 0x1822, 160 0x2230, 161 0x0002, 162 0 163 }; 164 165 /********************************************************************** 166 * 167 * availableModes 168 * 169 * Table of all allowed modes for tv output 170 * 171 **********************************************************************/ 172 static const struct radeon_tv_mode_constants available_tv_modes[] = { 173 { /* NTSC timing for 27 Mhz ref clk */ 174 800, /* horResolution */ 175 600, /* verResolution */ 176 TV_STD_NTSC, /* standard */ 177 990, /* horTotal */ 178 740, /* verTotal */ 179 813, /* horStart */ 180 824, /* horSyncStart */ 181 632, /* verSyncStart */ 182 625592, /* defRestart */ 183 592, /* crtcPLL_N */ 184 91, /* crtcPLL_M */ 185 4, /* crtcPLL_postDiv */ 186 1022, /* pixToTV */ 187 }, 188 { /* PAL timing for 27 Mhz ref clk */ 189 800, /* horResolution */ 190 600, /* verResolution */ 191 TV_STD_PAL, /* standard */ 192 1144, /* horTotal */ 193 706, /* verTotal */ 194 812, /* horStart */ 195 824, /* horSyncStart */ 196 669, /* verSyncStart */ 197 696700, /* defRestart */ 198 1382, /* crtcPLL_N */ 199 231, /* crtcPLL_M */ 200 4, /* crtcPLL_postDiv */ 201 759, /* pixToTV */ 202 }, 203 { /* NTSC timing for 14 Mhz ref clk */ 204 800, /* horResolution */ 205 600, /* verResolution */ 206 TV_STD_NTSC, /* standard */ 207 1018, /* horTotal */ 208 727, /* verTotal */ 209 813, /* horStart */ 210 840, /* horSyncStart */ 211 633, /* verSyncStart */ 212 630627, /* defRestart */ 213 347, /* crtcPLL_N */ 214 14, /* crtcPLL_M */ 215 8, /* crtcPLL_postDiv */ 216 1022, /* pixToTV */ 217 }, 218 { /* PAL timing for 14 Mhz ref clk */ 219 800, /* horResolution */ 220 600, /* verResolution */ 221 TV_STD_PAL, /* standard */ 222 1131, /* horTotal */ 223 742, /* verTotal */ 224 813, /* horStart */ 225 840, /* horSyncStart */ 226 633, /* verSyncStart */ 227 708369, /* defRestart */ 228 211, /* crtcPLL_N */ 229 9, /* crtcPLL_M */ 230 8, /* crtcPLL_postDiv */ 231 759, /* pixToTV */ 232 }, 233 }; 234 235 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) 236 237 static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 238 uint16_t *pll_ref_freq) 239 { 240 struct drm_device *dev = radeon_encoder->base.dev; 241 struct radeon_device *rdev = dev->dev_private; 242 struct radeon_crtc *radeon_crtc; 243 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 244 const struct radeon_tv_mode_constants *const_ptr; 245 struct radeon_pll *pll; 246 247 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 248 if (radeon_crtc->crtc_id == 1) 249 pll = &rdev->clock.p2pll; 250 else 251 pll = &rdev->clock.p1pll; 252 253 if (pll_ref_freq) 254 *pll_ref_freq = pll->reference_freq; 255 256 if (tv_dac->tv_std == TV_STD_NTSC || 257 tv_dac->tv_std == TV_STD_NTSC_J || 258 tv_dac->tv_std == TV_STD_PAL_M) { 259 if (pll->reference_freq == 2700) 260 const_ptr = &available_tv_modes[0]; 261 else 262 const_ptr = &available_tv_modes[2]; 263 } else { 264 if (pll->reference_freq == 2700) 265 const_ptr = &available_tv_modes[1]; 266 else 267 const_ptr = &available_tv_modes[3]; 268 } 269 return const_ptr; 270 } 271 272 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 273 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 274 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 275 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 276 277 static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 278 unsigned n_wait_loops, unsigned cnt_threshold) 279 { 280 struct drm_device *dev = encoder->dev; 281 struct radeon_device *rdev = dev->dev_private; 282 uint32_t save_pll_test; 283 unsigned int i, j; 284 285 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 286 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 287 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 288 289 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 290 for (i = 0; i < n_tests; i++) { 291 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 292 for (j = 0; j < n_wait_loops; j++) 293 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 294 break; 295 } 296 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 297 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 298 } 299 300 301 static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 302 uint16_t addr, uint32_t value) 303 { 304 struct drm_device *dev = radeon_encoder->base.dev; 305 struct radeon_device *rdev = dev->dev_private; 306 uint32_t tmp; 307 int i = 0; 308 309 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 310 311 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 312 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 313 314 do { 315 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 316 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 317 break; 318 i++; 319 } while (i < 10000); 320 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 321 } 322 323 #if 0 /* included for completeness */ 324 static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 325 { 326 struct drm_device *dev = radeon_encoder->base.dev; 327 struct radeon_device *rdev = dev->dev_private; 328 uint32_t tmp; 329 int i = 0; 330 331 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 332 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 333 334 do { 335 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 336 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 337 break; 338 i++; 339 } while (i < 10000); 340 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 341 return RREG32(RADEON_TV_HOST_READ_DATA); 342 } 343 #endif 344 345 static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 346 { 347 uint16_t h_table; 348 349 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 350 case 0: 351 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 352 break; 353 case 1: 354 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 355 break; 356 case 2: 357 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 358 break; 359 default: 360 h_table = 0; 361 break; 362 } 363 return h_table; 364 } 365 366 static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 367 { 368 uint16_t v_table; 369 370 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 371 case 0: 372 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 373 break; 374 case 1: 375 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 376 break; 377 case 2: 378 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 379 break; 380 default: 381 v_table = 0; 382 break; 383 } 384 return v_table; 385 } 386 387 static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 388 { 389 struct drm_device *dev = radeon_encoder->base.dev; 390 struct radeon_device *rdev = dev->dev_private; 391 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 392 uint16_t h_table, v_table; 393 uint32_t tmp; 394 int i; 395 396 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 397 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 398 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 399 400 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 401 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 402 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 403 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 404 break; 405 } 406 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 407 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 408 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 409 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 410 break; 411 } 412 } 413 414 static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 415 { 416 struct drm_device *dev = radeon_encoder->base.dev; 417 struct radeon_device *rdev = dev->dev_private; 418 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 419 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 420 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 421 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 422 } 423 424 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 425 { 426 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 427 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 428 int restart; 429 unsigned int h_total, v_total, f_total; 430 int v_offset, h_offset; 431 u16 p1, p2, h_inc; 432 bool h_changed; 433 const struct radeon_tv_mode_constants *const_ptr; 434 435 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 436 if (!const_ptr) 437 return false; 438 439 h_total = const_ptr->hor_total; 440 v_total = const_ptr->ver_total; 441 442 if (tv_dac->tv_std == TV_STD_NTSC || 443 tv_dac->tv_std == TV_STD_NTSC_J || 444 tv_dac->tv_std == TV_STD_PAL_M || 445 tv_dac->tv_std == TV_STD_PAL_60) 446 f_total = NTSC_TV_VFTOTAL + 1; 447 else 448 f_total = PAL_TV_VFTOTAL + 1; 449 450 /* adjust positions 1&2 in hor. cod timing table */ 451 h_offset = tv_dac->h_pos * H_POS_UNIT; 452 453 if (tv_dac->tv_std == TV_STD_NTSC || 454 tv_dac->tv_std == TV_STD_NTSC_J || 455 tv_dac->tv_std == TV_STD_PAL_M) { 456 h_offset -= 50; 457 p1 = hor_timing_NTSC[H_TABLE_POS1]; 458 p2 = hor_timing_NTSC[H_TABLE_POS2]; 459 } else { 460 p1 = hor_timing_PAL[H_TABLE_POS1]; 461 p2 = hor_timing_PAL[H_TABLE_POS2]; 462 } 463 464 p1 = (u16)((int)p1 + h_offset); 465 p2 = (u16)((int)p2 - h_offset); 466 467 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 468 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 469 470 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 471 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 472 473 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 474 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 475 476 /* adjust restart */ 477 restart = const_ptr->def_restart; 478 479 /* 480 * convert v_pos TV lines to n. of CRTC pixels 481 */ 482 if (tv_dac->tv_std == TV_STD_NTSC || 483 tv_dac->tv_std == TV_STD_NTSC_J || 484 tv_dac->tv_std == TV_STD_PAL_M || 485 tv_dac->tv_std == TV_STD_PAL_60) 486 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 487 else 488 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 489 490 restart -= v_offset + h_offset; 491 492 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 493 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 494 495 tv_dac->tv.hrestart = restart % h_total; 496 restart /= h_total; 497 tv_dac->tv.vrestart = restart % v_total; 498 restart /= v_total; 499 tv_dac->tv.frestart = restart % f_total; 500 501 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 502 (unsigned)tv_dac->tv.frestart, 503 (unsigned)tv_dac->tv.vrestart, 504 (unsigned)tv_dac->tv.hrestart); 505 506 /* compute h_inc from hsize */ 507 if (tv_dac->tv_std == TV_STD_NTSC || 508 tv_dac->tv_std == TV_STD_NTSC_J || 509 tv_dac->tv_std == TV_STD_PAL_M) 510 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 511 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 512 else 513 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 514 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 515 516 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 517 ((u32)h_inc << RADEON_H_INC_SHIFT); 518 519 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 520 521 return h_changed; 522 } 523 524 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 525 struct drm_display_mode *mode, 526 struct drm_display_mode *adjusted_mode) 527 { 528 struct drm_device *dev = encoder->dev; 529 struct radeon_device *rdev = dev->dev_private; 530 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 531 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 532 const struct radeon_tv_mode_constants *const_ptr; 533 struct radeon_crtc *radeon_crtc; 534 int i; 535 uint16_t pll_ref_freq; 536 uint32_t vert_space, flicker_removal, tmp; 537 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 538 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 539 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 540 uint32_t tv_pll_cntl, tv_ftotal; 541 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 542 uint32_t m, n, p; 543 const uint16_t *hor_timing; 544 const uint16_t *vert_timing; 545 546 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 547 if (!const_ptr) 548 return; 549 550 radeon_crtc = to_radeon_crtc(encoder->crtc); 551 552 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 553 RADEON_CRT_FIFO_CE_EN | 554 RADEON_TV_FIFO_CE_EN | 555 RADEON_TV_ON); 556 557 if (!ASIC_IS_R300(rdev)) 558 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 559 560 if (tv_dac->tv_std == TV_STD_NTSC || 561 tv_dac->tv_std == TV_STD_NTSC_J) 562 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 563 564 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 565 RADEON_SYNC_TIP_LEVEL | 566 RADEON_YFLT_EN | 567 RADEON_UVFLT_EN | 568 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 569 570 if (tv_dac->tv_std == TV_STD_NTSC || 571 tv_dac->tv_std == TV_STD_NTSC_J) { 572 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 573 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 574 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 575 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 576 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 577 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 578 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 579 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 580 } else { 581 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 582 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 583 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 584 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 585 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 586 } 587 588 589 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 590 | RADEON_TVOUT_SCALE_EN 591 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 592 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 593 | RADEON_RGB_ATTEN_SEL(0x3) 594 | RADEON_RGB_ATTEN_VAL(0xc)); 595 596 if (radeon_crtc->crtc_id == 1) 597 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 598 else { 599 if (radeon_crtc->rmx_type != RMX_OFF) 600 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 601 else 602 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 603 } 604 605 if (tv_dac->tv_std == TV_STD_NTSC || 606 tv_dac->tv_std == TV_STD_NTSC_J || 607 tv_dac->tv_std == TV_STD_PAL_M || 608 tv_dac->tv_std == TV_STD_PAL_60) 609 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 610 else 611 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 612 613 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 614 tmp &= 0xe3ff0000; 615 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 616 tv_vscaler_cntl1 = tmp; 617 618 if (pll_ref_freq == 2700) 619 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 620 621 if (const_ptr->hor_resolution == 1024) 622 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 623 else 624 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 625 626 /* scale up for int divide */ 627 tmp = const_ptr->ver_total * 2 * 1000; 628 if (tv_dac->tv_std == TV_STD_NTSC || 629 tv_dac->tv_std == TV_STD_NTSC_J || 630 tv_dac->tv_std == TV_STD_PAL_M || 631 tv_dac->tv_std == TV_STD_PAL_60) { 632 tmp /= NTSC_TV_LINES_PER_FRAME; 633 } else { 634 tmp /= PAL_TV_LINES_PER_FRAME; 635 } 636 flicker_removal = (tmp + 500) / 1000; 637 638 if (flicker_removal < 3) 639 flicker_removal = 3; 640 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 641 if (flicker_removal == SLOPE_limit[i]) 642 break; 643 } 644 645 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 646 5001) / 10000 / 8 | ((SLOPE_value[i] * 647 (1 << (FRAC_BITS - 1)) / 8) << 16); 648 tv_y_fall_cntl = 649 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 650 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 651 1024; 652 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 653 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 654 655 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 656 tv_vscaler_cntl2 |= (0x10 << 24) | 657 RADEON_DITHER_MODE | 658 RADEON_Y_OUTPUT_DITHER_EN | 659 RADEON_UV_OUTPUT_DITHER_EN | 660 RADEON_UV_TO_BUF_DITHER_EN; 661 662 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 663 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 664 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 665 tv_dac->tv.timing_cntl = tmp; 666 667 if (tv_dac->tv_std == TV_STD_NTSC || 668 tv_dac->tv_std == TV_STD_NTSC_J || 669 tv_dac->tv_std == TV_STD_PAL_M || 670 tv_dac->tv_std == TV_STD_PAL_60) 671 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 672 else 673 tv_dac_cntl = tv_dac->pal_tvdac_adj; 674 675 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 676 677 if (tv_dac->tv_std == TV_STD_NTSC || 678 tv_dac->tv_std == TV_STD_NTSC_J) 679 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 680 else 681 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 682 683 if (tv_dac->tv_std == TV_STD_NTSC || 684 tv_dac->tv_std == TV_STD_NTSC_J) { 685 if (pll_ref_freq == 2700) { 686 m = NTSC_TV_PLL_M_27; 687 n = NTSC_TV_PLL_N_27; 688 p = NTSC_TV_PLL_P_27; 689 } else { 690 m = NTSC_TV_PLL_M_14; 691 n = NTSC_TV_PLL_N_14; 692 p = NTSC_TV_PLL_P_14; 693 } 694 } else { 695 if (pll_ref_freq == 2700) { 696 m = PAL_TV_PLL_M_27; 697 n = PAL_TV_PLL_N_27; 698 p = PAL_TV_PLL_P_27; 699 } else { 700 m = PAL_TV_PLL_M_14; 701 n = PAL_TV_PLL_N_14; 702 p = PAL_TV_PLL_P_14; 703 } 704 } 705 706 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 707 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 708 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 709 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 710 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 711 712 tv_dac->tv.tv_uv_adr = 0xc8; 713 714 if (tv_dac->tv_std == TV_STD_NTSC || 715 tv_dac->tv_std == TV_STD_NTSC_J || 716 tv_dac->tv_std == TV_STD_PAL_M || 717 tv_dac->tv_std == TV_STD_PAL_60) { 718 tv_ftotal = NTSC_TV_VFTOTAL; 719 hor_timing = hor_timing_NTSC; 720 vert_timing = vert_timing_NTSC; 721 } else { 722 hor_timing = hor_timing_PAL; 723 vert_timing = vert_timing_PAL; 724 tv_ftotal = PAL_TV_VFTOTAL; 725 } 726 727 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 728 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 729 break; 730 } 731 732 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 733 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 734 break; 735 } 736 737 radeon_legacy_tv_init_restarts(encoder); 738 739 /* play with DAC_CNTL */ 740 /* play with GPIOPAD_A */ 741 /* DISP_OUTPUT_CNTL */ 742 /* use reference freq */ 743 744 /* program the TV registers */ 745 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 746 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 747 748 tmp = RREG32(RADEON_TV_DAC_CNTL); 749 tmp &= ~RADEON_TV_DAC_NBLANK; 750 tmp |= RADEON_TV_DAC_BGSLEEP | 751 RADEON_TV_DAC_RDACPD | 752 RADEON_TV_DAC_GDACPD | 753 RADEON_TV_DAC_BDACPD; 754 WREG32(RADEON_TV_DAC_CNTL, tmp); 755 756 /* TV PLL */ 757 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 758 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 759 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 760 761 radeon_wait_pll_lock(encoder, 200, 800, 135); 762 763 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 764 765 radeon_wait_pll_lock(encoder, 300, 160, 27); 766 radeon_wait_pll_lock(encoder, 200, 800, 135); 767 768 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 769 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 770 771 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 773 774 /* TV HV */ 775 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 776 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 777 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 778 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 779 780 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 781 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 782 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 783 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 784 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 785 786 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 787 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 788 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 789 790 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 791 RADEON_CRT_ASYNC_RST)); 792 793 /* TV restarts */ 794 radeon_legacy_write_tv_restarts(radeon_encoder); 795 796 /* tv timings */ 797 radeon_restore_tv_timing_tables(radeon_encoder); 798 799 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 800 801 /* tv std */ 802 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 803 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 804 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 805 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 806 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 807 RADEON_C_GRN_EN | 808 RADEON_CMP_BLU_EN | 809 RADEON_DAC_DITHER_EN)); 810 811 WREG32(RADEON_TV_CRC_CNTL, 0); 812 813 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 814 815 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 816 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 817 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 818 (0x100 << RADEON_Y_GAIN_SHIFT))); 819 820 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 821 822 } 823 824 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 825 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 826 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 827 { 828 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 829 const struct radeon_tv_mode_constants *const_ptr; 830 uint32_t tmp; 831 832 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 833 if (!const_ptr) 834 return; 835 836 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 837 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 838 839 tmp = *h_sync_strt_wid; 840 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 841 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 842 (const_ptr->hor_syncstart & 7); 843 *h_sync_strt_wid = tmp; 844 845 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 846 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 847 848 tmp = *v_sync_strt_wid; 849 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 850 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 851 *v_sync_strt_wid = tmp; 852 } 853 854 static int get_post_div(int value) 855 { 856 int post_div; 857 switch (value) { 858 case 1: post_div = 0; break; 859 case 2: post_div = 1; break; 860 case 3: post_div = 4; break; 861 case 4: post_div = 2; break; 862 case 6: post_div = 6; break; 863 case 8: post_div = 3; break; 864 case 12: post_div = 7; break; 865 case 16: 866 default: post_div = 5; break; 867 } 868 return post_div; 869 } 870 871 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 872 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 873 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 874 { 875 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 876 const struct radeon_tv_mode_constants *const_ptr; 877 878 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 879 if (!const_ptr) 880 return; 881 882 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 883 884 *ppll_ref_div = const_ptr->crtcPLL_M; 885 886 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 887 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 888 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 889 } 890 891 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 892 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 893 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 894 { 895 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 896 const struct radeon_tv_mode_constants *const_ptr; 897 898 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 899 if (!const_ptr) 900 return; 901 902 *htotal2_cntl = (const_ptr->hor_total & 0x7); 903 904 *p2pll_ref_div = const_ptr->crtcPLL_M; 905 906 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 907 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 908 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 909 } 910 911