1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include "radeon.h" 30 #include "atom.h" 31 #include <linux/backlight.h> 32 #ifdef CONFIG_PMAC_BACKLIGHT 33 #include <asm/backlight.h> 34 #endif 35 36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) 37 { 38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 39 struct drm_encoder_helper_funcs *encoder_funcs; 40 41 encoder_funcs = encoder->helper_private; 42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 43 radeon_encoder->active_device = 0; 44 } 45 46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) 47 { 48 struct drm_device *dev = encoder->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 52 int panel_pwr_delay = 2000; 53 bool is_mac = false; 54 uint8_t backlight_level; 55 DRM_DEBUG_KMS("\n"); 56 57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 59 60 if (radeon_encoder->enc_priv) { 61 if (rdev->is_atom_bios) { 62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 63 panel_pwr_delay = lvds->panel_pwr_delay; 64 if (lvds->bl_dev) 65 backlight_level = lvds->backlight_level; 66 } else { 67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 68 panel_pwr_delay = lvds->panel_pwr_delay; 69 if (lvds->bl_dev) 70 backlight_level = lvds->backlight_level; 71 } 72 } 73 74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 75 * Taken from radeonfb. 76 */ 77 if ((rdev->mode_info.connector_table == CT_IBOOK) || 78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 81 is_mac = true; 82 83 switch (mode) { 84 case DRM_MODE_DPMS_ON: 85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN; 87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); 88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 91 mdelay(1); 92 93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 96 97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 98 RADEON_LVDS_BL_MOD_LEVEL_MASK); 99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | 100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON | 101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 102 if (is_mac) 103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 104 mdelay(panel_pwr_delay); 105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 106 break; 107 case DRM_MODE_DPMS_STANDBY: 108 case DRM_MODE_DPMS_SUSPEND: 109 case DRM_MODE_DPMS_OFF: 110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 113 if (is_mac) { 114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 117 } else { 118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 120 } 121 mdelay(panel_pwr_delay); 122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 124 mdelay(panel_pwr_delay); 125 break; 126 } 127 128 if (rdev->is_atom_bios) 129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 130 else 131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 132 133 } 134 135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 136 { 137 struct radeon_device *rdev = encoder->dev->dev_private; 138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 139 DRM_DEBUG("\n"); 140 141 if (radeon_encoder->enc_priv) { 142 if (rdev->is_atom_bios) { 143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 144 lvds->dpms_mode = mode; 145 } else { 146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 147 lvds->dpms_mode = mode; 148 } 149 } 150 151 radeon_legacy_lvds_update(encoder, mode); 152 } 153 154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) 155 { 156 struct radeon_device *rdev = encoder->dev->dev_private; 157 158 if (rdev->is_atom_bios) 159 radeon_atom_output_lock(encoder, true); 160 else 161 radeon_combios_output_lock(encoder, true); 162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 163 } 164 165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 166 { 167 struct radeon_device *rdev = encoder->dev->dev_private; 168 169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); 170 if (rdev->is_atom_bios) 171 radeon_atom_output_lock(encoder, false); 172 else 173 radeon_combios_output_lock(encoder, false); 174 } 175 176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, 177 struct drm_display_mode *mode, 178 struct drm_display_mode *adjusted_mode) 179 { 180 struct drm_device *dev = encoder->dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 185 186 DRM_DEBUG_KMS("\n"); 187 188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 190 191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 192 if (rdev->is_atom_bios) { 193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl 194 * need to call that on resume to set up the reg properly. 195 */ 196 radeon_encoder->pixel_clock = adjusted_mode->clock; 197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 199 } else { 200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 201 if (lvds) { 202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 203 lvds_gen_cntl = lvds->lvds_gen_cntl; 204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 208 } else 209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 210 } 211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 212 lvds_gen_cntl &= ~(RADEON_LVDS_ON | 213 RADEON_LVDS_BLON | 214 RADEON_LVDS_EN | 215 RADEON_LVDS_RST_FM); 216 217 if (ASIC_IS_R300(rdev)) 218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 219 220 if (radeon_crtc->crtc_id == 0) { 221 if (ASIC_IS_R300(rdev)) { 222 if (radeon_encoder->rmx_type != RMX_OFF) 223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 224 } else 225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 226 } else { 227 if (ASIC_IS_R300(rdev)) 228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 229 else 230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 231 } 232 233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); 236 237 if (rdev->family == CHIP_RV410) 238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); 239 240 if (rdev->is_atom_bios) 241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 242 else 243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 244 } 245 246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, 247 const struct drm_display_mode *mode, 248 struct drm_display_mode *adjusted_mode) 249 { 250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 251 252 /* set the active encoder to connector routing */ 253 radeon_encoder_set_active_device(encoder); 254 drm_mode_set_crtcinfo(adjusted_mode, 0); 255 256 /* get the native mode for LVDS */ 257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 258 radeon_panel_mode_fixup(encoder, adjusted_mode); 259 260 return true; 261 } 262 263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { 264 .dpms = radeon_legacy_lvds_dpms, 265 .mode_fixup = radeon_legacy_mode_fixup, 266 .prepare = radeon_legacy_lvds_prepare, 267 .mode_set = radeon_legacy_lvds_mode_set, 268 .commit = radeon_legacy_lvds_commit, 269 .disable = radeon_legacy_encoder_disable, 270 }; 271 272 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 273 274 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) 275 { 276 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 277 uint8_t level; 278 279 /* Convert brightness to hardware level */ 280 if (bd->props.brightness < 0) 281 level = 0; 282 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 283 level = RADEON_MAX_BL_LEVEL; 284 else 285 level = bd->props.brightness; 286 287 if (pdata->negative) 288 level = RADEON_MAX_BL_LEVEL - level; 289 290 return level; 291 } 292 293 u8 294 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 295 { 296 struct drm_device *dev = radeon_encoder->base.dev; 297 struct radeon_device *rdev = dev->dev_private; 298 u8 backlight_level; 299 300 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 301 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 302 303 return backlight_level; 304 } 305 306 void 307 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 308 { 309 struct drm_device *dev = radeon_encoder->base.dev; 310 struct radeon_device *rdev = dev->dev_private; 311 int dpms_mode = DRM_MODE_DPMS_ON; 312 313 if (radeon_encoder->enc_priv) { 314 if (rdev->is_atom_bios) { 315 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 316 if (lvds->backlight_level > 0) 317 dpms_mode = lvds->dpms_mode; 318 else 319 dpms_mode = DRM_MODE_DPMS_OFF; 320 lvds->backlight_level = level; 321 } else { 322 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 323 if (lvds->backlight_level > 0) 324 dpms_mode = lvds->dpms_mode; 325 else 326 dpms_mode = DRM_MODE_DPMS_OFF; 327 lvds->backlight_level = level; 328 } 329 } 330 331 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 332 } 333 334 static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 335 { 336 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 337 struct radeon_encoder *radeon_encoder = pdata->encoder; 338 339 radeon_legacy_set_backlight_level(radeon_encoder, 340 radeon_legacy_lvds_level(bd)); 341 342 return 0; 343 } 344 345 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) 346 { 347 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 348 struct radeon_encoder *radeon_encoder = pdata->encoder; 349 struct drm_device *dev = radeon_encoder->base.dev; 350 struct radeon_device *rdev = dev->dev_private; 351 uint8_t backlight_level; 352 353 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 354 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 355 356 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; 357 } 358 359 static const struct backlight_ops radeon_backlight_ops = { 360 .get_brightness = radeon_legacy_backlight_get_brightness, 361 .update_status = radeon_legacy_backlight_update_status, 362 }; 363 364 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 365 struct drm_connector *drm_connector) 366 { 367 struct drm_device *dev = radeon_encoder->base.dev; 368 struct radeon_device *rdev = dev->dev_private; 369 struct backlight_device *bd; 370 struct backlight_properties props; 371 struct radeon_backlight_privdata *pdata; 372 uint8_t backlight_level; 373 374 if (!radeon_encoder->enc_priv) 375 return; 376 377 #ifdef CONFIG_PMAC_BACKLIGHT 378 if (!pmac_has_backlight_type("ati") && 379 !pmac_has_backlight_type("mnca")) 380 return; 381 #endif 382 383 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 384 if (!pdata) { 385 DRM_ERROR("Memory allocation failed\n"); 386 goto error; 387 } 388 389 memset(&props, 0, sizeof(props)); 390 props.max_brightness = RADEON_MAX_BL_LEVEL; 391 props.type = BACKLIGHT_RAW; 392 bd = backlight_device_register("radeon_bl", &drm_connector->kdev, 393 pdata, &radeon_backlight_ops, &props); 394 if (IS_ERR(bd)) { 395 DRM_ERROR("Backlight registration failed\n"); 396 goto error; 397 } 398 399 pdata->encoder = radeon_encoder; 400 401 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 402 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 403 404 /* First, try to detect backlight level sense based on the assumption 405 * that firmware set it up at full brightness 406 */ 407 if (backlight_level == 0) 408 pdata->negative = true; 409 else if (backlight_level == 0xff) 410 pdata->negative = false; 411 else { 412 /* XXX hack... maybe some day we can figure out in what direction 413 * backlight should work on a given panel? 414 */ 415 pdata->negative = (rdev->family != CHIP_RV200 && 416 rdev->family != CHIP_RV250 && 417 rdev->family != CHIP_RV280 && 418 rdev->family != CHIP_RV350); 419 420 #ifdef CONFIG_PMAC_BACKLIGHT 421 pdata->negative = (pdata->negative || 422 of_machine_is_compatible("PowerBook4,3") || 423 of_machine_is_compatible("PowerBook6,3") || 424 of_machine_is_compatible("PowerBook6,5")); 425 #endif 426 } 427 428 if (rdev->is_atom_bios) { 429 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 430 lvds->bl_dev = bd; 431 } else { 432 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 433 lvds->bl_dev = bd; 434 } 435 436 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); 437 bd->props.power = FB_BLANK_UNBLANK; 438 backlight_update_status(bd); 439 440 DRM_INFO("radeon legacy LVDS backlight initialized\n"); 441 442 return; 443 444 error: 445 kfree(pdata); 446 return; 447 } 448 449 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) 450 { 451 struct drm_device *dev = radeon_encoder->base.dev; 452 struct radeon_device *rdev = dev->dev_private; 453 struct backlight_device *bd = NULL; 454 455 if (!radeon_encoder->enc_priv) 456 return; 457 458 if (rdev->is_atom_bios) { 459 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 460 bd = lvds->bl_dev; 461 lvds->bl_dev = NULL; 462 } else { 463 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 464 bd = lvds->bl_dev; 465 lvds->bl_dev = NULL; 466 } 467 468 if (bd) { 469 struct radeon_backlight_privdata *pdata; 470 471 pdata = bl_get_data(bd); 472 backlight_device_unregister(bd); 473 kfree(pdata); 474 475 DRM_INFO("radeon legacy LVDS backlight unloaded\n"); 476 } 477 } 478 479 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 480 481 void radeon_legacy_backlight_init(struct radeon_encoder *encoder) 482 { 483 } 484 485 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) 486 { 487 } 488 489 #endif 490 491 492 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) 493 { 494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 495 496 if (radeon_encoder->enc_priv) { 497 radeon_legacy_backlight_exit(radeon_encoder); 498 kfree(radeon_encoder->enc_priv); 499 } 500 drm_encoder_cleanup(encoder); 501 kfree(radeon_encoder); 502 } 503 504 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { 505 .destroy = radeon_lvds_enc_destroy, 506 }; 507 508 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) 509 { 510 struct drm_device *dev = encoder->dev; 511 struct radeon_device *rdev = dev->dev_private; 512 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 513 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 514 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 515 516 DRM_DEBUG_KMS("\n"); 517 518 switch (mode) { 519 case DRM_MODE_DPMS_ON: 520 crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 521 dac_cntl &= ~RADEON_DAC_PDWN; 522 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 523 RADEON_DAC_PDWN_G | 524 RADEON_DAC_PDWN_B); 525 break; 526 case DRM_MODE_DPMS_STANDBY: 527 case DRM_MODE_DPMS_SUSPEND: 528 case DRM_MODE_DPMS_OFF: 529 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 530 dac_cntl |= RADEON_DAC_PDWN; 531 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 532 RADEON_DAC_PDWN_G | 533 RADEON_DAC_PDWN_B); 534 break; 535 } 536 537 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 538 WREG32(RADEON_DAC_CNTL, dac_cntl); 539 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 540 541 if (rdev->is_atom_bios) 542 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 543 else 544 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 545 546 } 547 548 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) 549 { 550 struct radeon_device *rdev = encoder->dev->dev_private; 551 552 if (rdev->is_atom_bios) 553 radeon_atom_output_lock(encoder, true); 554 else 555 radeon_combios_output_lock(encoder, true); 556 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 557 } 558 559 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 560 { 561 struct radeon_device *rdev = encoder->dev->dev_private; 562 563 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); 564 565 if (rdev->is_atom_bios) 566 radeon_atom_output_lock(encoder, false); 567 else 568 radeon_combios_output_lock(encoder, false); 569 } 570 571 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, 572 struct drm_display_mode *mode, 573 struct drm_display_mode *adjusted_mode) 574 { 575 struct drm_device *dev = encoder->dev; 576 struct radeon_device *rdev = dev->dev_private; 577 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 578 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 579 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 580 581 DRM_DEBUG_KMS("\n"); 582 583 if (radeon_crtc->crtc_id == 0) { 584 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 585 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 586 ~(RADEON_DISP_DAC_SOURCE_MASK); 587 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 588 } else { 589 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); 590 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 591 } 592 } else { 593 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 594 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 595 ~(RADEON_DISP_DAC_SOURCE_MASK); 596 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 597 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 598 } else { 599 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; 600 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 601 } 602 } 603 604 dac_cntl = (RADEON_DAC_MASK_ALL | 605 RADEON_DAC_VGA_ADR_EN | 606 /* TODO 6-bits */ 607 RADEON_DAC_8BIT_EN); 608 609 WREG32_P(RADEON_DAC_CNTL, 610 dac_cntl, 611 RADEON_DAC_RANGE_CNTL | 612 RADEON_DAC_BLANKING); 613 614 if (radeon_encoder->enc_priv) { 615 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; 616 dac_macro_cntl = p_dac->ps2_pdac_adj; 617 } else 618 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 619 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; 620 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 621 622 if (rdev->is_atom_bios) 623 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 624 else 625 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 626 } 627 628 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, 629 struct drm_connector *connector) 630 { 631 struct drm_device *dev = encoder->dev; 632 struct radeon_device *rdev = dev->dev_private; 633 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 634 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 635 enum drm_connector_status found = connector_status_disconnected; 636 bool color = true; 637 638 /* save the regs we need */ 639 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 640 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 641 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 642 dac_cntl = RREG32(RADEON_DAC_CNTL); 643 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 644 645 tmp = vclk_ecp_cntl & 646 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 647 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 648 649 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 650 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 651 652 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 653 RADEON_DAC_FORCE_DATA_EN; 654 655 if (color) 656 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 657 else 658 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 659 660 if (ASIC_IS_R300(rdev)) 661 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 662 else 663 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 664 665 WREG32(RADEON_DAC_EXT_CNTL, tmp); 666 667 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 668 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 669 WREG32(RADEON_DAC_CNTL, tmp); 670 671 tmp &= ~(RADEON_DAC_PDWN_R | 672 RADEON_DAC_PDWN_G | 673 RADEON_DAC_PDWN_B); 674 675 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 676 677 mdelay(2); 678 679 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 680 found = connector_status_connected; 681 682 /* restore the regs we used */ 683 WREG32(RADEON_DAC_CNTL, dac_cntl); 684 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 685 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 686 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 687 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 688 689 return found; 690 } 691 692 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { 693 .dpms = radeon_legacy_primary_dac_dpms, 694 .mode_fixup = radeon_legacy_mode_fixup, 695 .prepare = radeon_legacy_primary_dac_prepare, 696 .mode_set = radeon_legacy_primary_dac_mode_set, 697 .commit = radeon_legacy_primary_dac_commit, 698 .detect = radeon_legacy_primary_dac_detect, 699 .disable = radeon_legacy_encoder_disable, 700 }; 701 702 703 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { 704 .destroy = radeon_enc_destroy, 705 }; 706 707 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) 708 { 709 struct drm_device *dev = encoder->dev; 710 struct radeon_device *rdev = dev->dev_private; 711 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 712 DRM_DEBUG_KMS("\n"); 713 714 switch (mode) { 715 case DRM_MODE_DPMS_ON: 716 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 717 break; 718 case DRM_MODE_DPMS_STANDBY: 719 case DRM_MODE_DPMS_SUSPEND: 720 case DRM_MODE_DPMS_OFF: 721 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 722 break; 723 } 724 725 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 726 727 if (rdev->is_atom_bios) 728 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 729 else 730 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 731 732 } 733 734 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) 735 { 736 struct radeon_device *rdev = encoder->dev->dev_private; 737 738 if (rdev->is_atom_bios) 739 radeon_atom_output_lock(encoder, true); 740 else 741 radeon_combios_output_lock(encoder, true); 742 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 743 } 744 745 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 746 { 747 struct radeon_device *rdev = encoder->dev->dev_private; 748 749 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); 750 751 if (rdev->is_atom_bios) 752 radeon_atom_output_lock(encoder, true); 753 else 754 radeon_combios_output_lock(encoder, true); 755 } 756 757 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 758 struct drm_display_mode *mode, 759 struct drm_display_mode *adjusted_mode) 760 { 761 struct drm_device *dev = encoder->dev; 762 struct radeon_device *rdev = dev->dev_private; 763 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 764 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 765 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 766 int i; 767 768 DRM_DEBUG_KMS("\n"); 769 770 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 771 tmp &= 0xfffff; 772 if (rdev->family == CHIP_RV280) { 773 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 774 tmp ^= (1 << 22); 775 tmds_pll_cntl ^= (1 << 22); 776 } 777 778 if (radeon_encoder->enc_priv) { 779 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; 780 781 for (i = 0; i < 4; i++) { 782 if (tmds->tmds_pll[i].freq == 0) 783 break; 784 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 785 tmp = tmds->tmds_pll[i].value ; 786 break; 787 } 788 } 789 } 790 791 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { 792 if (tmp & 0xfff00000) 793 tmds_pll_cntl = tmp; 794 else { 795 tmds_pll_cntl &= 0xfff00000; 796 tmds_pll_cntl |= tmp; 797 } 798 } else 799 tmds_pll_cntl = tmp; 800 801 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & 802 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 803 804 if (rdev->family == CHIP_R200 || 805 rdev->family == CHIP_R100 || 806 ASIC_IS_R300(rdev)) 807 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 808 else /* RV chips got this bit reversed */ 809 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; 810 811 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | 812 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 813 RADEON_FP_CRTC_DONT_SHADOW_HEND)); 814 815 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 816 817 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 818 RADEON_FP_DFP_SYNC_SEL | 819 RADEON_FP_CRT_SYNC_SEL | 820 RADEON_FP_CRTC_LOCK_8DOT | 821 RADEON_FP_USE_SHADOW_EN | 822 RADEON_FP_CRTC_USE_SHADOW_VEND | 823 RADEON_FP_CRT_SYNC_ALT); 824 825 if (1) /* FIXME rgbBits == 8 */ 826 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 827 else 828 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 829 830 if (radeon_crtc->crtc_id == 0) { 831 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 832 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 833 if (radeon_encoder->rmx_type != RMX_OFF) 834 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 835 else 836 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 837 } else 838 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 839 } else { 840 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 841 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 842 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 843 } else 844 fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 845 } 846 847 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); 848 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); 849 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 850 851 if (rdev->is_atom_bios) 852 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 853 else 854 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 855 } 856 857 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { 858 .dpms = radeon_legacy_tmds_int_dpms, 859 .mode_fixup = radeon_legacy_mode_fixup, 860 .prepare = radeon_legacy_tmds_int_prepare, 861 .mode_set = radeon_legacy_tmds_int_mode_set, 862 .commit = radeon_legacy_tmds_int_commit, 863 .disable = radeon_legacy_encoder_disable, 864 }; 865 866 867 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { 868 .destroy = radeon_enc_destroy, 869 }; 870 871 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) 872 { 873 struct drm_device *dev = encoder->dev; 874 struct radeon_device *rdev = dev->dev_private; 875 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 876 DRM_DEBUG_KMS("\n"); 877 878 switch (mode) { 879 case DRM_MODE_DPMS_ON: 880 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 881 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 882 break; 883 case DRM_MODE_DPMS_STANDBY: 884 case DRM_MODE_DPMS_SUSPEND: 885 case DRM_MODE_DPMS_OFF: 886 fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 887 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 888 break; 889 } 890 891 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 892 893 if (rdev->is_atom_bios) 894 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 895 else 896 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 897 898 } 899 900 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) 901 { 902 struct radeon_device *rdev = encoder->dev->dev_private; 903 904 if (rdev->is_atom_bios) 905 radeon_atom_output_lock(encoder, true); 906 else 907 radeon_combios_output_lock(encoder, true); 908 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 909 } 910 911 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 912 { 913 struct radeon_device *rdev = encoder->dev->dev_private; 914 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); 915 916 if (rdev->is_atom_bios) 917 radeon_atom_output_lock(encoder, false); 918 else 919 radeon_combios_output_lock(encoder, false); 920 } 921 922 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, 923 struct drm_display_mode *mode, 924 struct drm_display_mode *adjusted_mode) 925 { 926 struct drm_device *dev = encoder->dev; 927 struct radeon_device *rdev = dev->dev_private; 928 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 929 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 930 uint32_t fp2_gen_cntl; 931 932 DRM_DEBUG_KMS("\n"); 933 934 if (rdev->is_atom_bios) { 935 radeon_encoder->pixel_clock = adjusted_mode->clock; 936 atombios_dvo_setup(encoder, ATOM_ENABLE); 937 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 938 } else { 939 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 940 941 if (1) /* FIXME rgbBits == 8 */ 942 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 943 else 944 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 945 946 fp2_gen_cntl &= ~(RADEON_FP2_ON | 947 RADEON_FP2_DVO_EN | 948 RADEON_FP2_DVO_RATE_SEL_SDR); 949 950 /* XXX: these are oem specific */ 951 if (ASIC_IS_R300(rdev)) { 952 if ((dev->pdev->device == 0x4850) && 953 (dev->pdev->subsystem_vendor == 0x1028) && 954 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ 955 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; 956 else 957 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; 958 959 /*if (mode->clock > 165000) 960 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ 961 } 962 if (!radeon_combios_external_tmds_setup(encoder)) 963 radeon_external_tmds_setup(encoder); 964 } 965 966 if (radeon_crtc->crtc_id == 0) { 967 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 968 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 969 if (radeon_encoder->rmx_type != RMX_OFF) 970 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 971 else 972 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 973 } else 974 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 975 } else { 976 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 977 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 978 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 979 } else 980 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 981 } 982 983 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 984 985 if (rdev->is_atom_bios) 986 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 987 else 988 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 989 } 990 991 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 992 { 993 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 994 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 995 if (tmds) { 996 if (tmds->i2c_bus) 997 radeon_i2c_destroy(tmds->i2c_bus); 998 } 999 kfree(radeon_encoder->enc_priv); 1000 drm_encoder_cleanup(encoder); 1001 kfree(radeon_encoder); 1002 } 1003 1004 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { 1005 .dpms = radeon_legacy_tmds_ext_dpms, 1006 .mode_fixup = radeon_legacy_mode_fixup, 1007 .prepare = radeon_legacy_tmds_ext_prepare, 1008 .mode_set = radeon_legacy_tmds_ext_mode_set, 1009 .commit = radeon_legacy_tmds_ext_commit, 1010 .disable = radeon_legacy_encoder_disable, 1011 }; 1012 1013 1014 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { 1015 .destroy = radeon_ext_tmds_enc_destroy, 1016 }; 1017 1018 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) 1019 { 1020 struct drm_device *dev = encoder->dev; 1021 struct radeon_device *rdev = dev->dev_private; 1022 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1023 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 1024 uint32_t tv_master_cntl = 0; 1025 bool is_tv; 1026 DRM_DEBUG_KMS("\n"); 1027 1028 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1029 1030 if (rdev->family == CHIP_R200) 1031 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1032 else { 1033 if (is_tv) 1034 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1035 else 1036 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1037 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1038 } 1039 1040 switch (mode) { 1041 case DRM_MODE_DPMS_ON: 1042 if (rdev->family == CHIP_R200) { 1043 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1044 } else { 1045 if (is_tv) 1046 tv_master_cntl |= RADEON_TV_ON; 1047 else 1048 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 1049 1050 if (rdev->family == CHIP_R420 || 1051 rdev->family == CHIP_R423 || 1052 rdev->family == CHIP_RV410) 1053 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 1054 R420_TV_DAC_GDACPD | 1055 R420_TV_DAC_BDACPD | 1056 RADEON_TV_DAC_BGSLEEP); 1057 else 1058 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 1059 RADEON_TV_DAC_GDACPD | 1060 RADEON_TV_DAC_BDACPD | 1061 RADEON_TV_DAC_BGSLEEP); 1062 } 1063 break; 1064 case DRM_MODE_DPMS_STANDBY: 1065 case DRM_MODE_DPMS_SUSPEND: 1066 case DRM_MODE_DPMS_OFF: 1067 if (rdev->family == CHIP_R200) 1068 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1069 else { 1070 if (is_tv) 1071 tv_master_cntl &= ~RADEON_TV_ON; 1072 else 1073 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1074 1075 if (rdev->family == CHIP_R420 || 1076 rdev->family == CHIP_R423 || 1077 rdev->family == CHIP_RV410) 1078 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 1079 R420_TV_DAC_GDACPD | 1080 R420_TV_DAC_BDACPD | 1081 RADEON_TV_DAC_BGSLEEP); 1082 else 1083 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 1084 RADEON_TV_DAC_GDACPD | 1085 RADEON_TV_DAC_BDACPD | 1086 RADEON_TV_DAC_BGSLEEP); 1087 } 1088 break; 1089 } 1090 1091 if (rdev->family == CHIP_R200) { 1092 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1093 } else { 1094 if (is_tv) 1095 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1096 else 1097 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1098 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1099 } 1100 1101 if (rdev->is_atom_bios) 1102 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1103 else 1104 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1105 1106 } 1107 1108 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) 1109 { 1110 struct radeon_device *rdev = encoder->dev->dev_private; 1111 1112 if (rdev->is_atom_bios) 1113 radeon_atom_output_lock(encoder, true); 1114 else 1115 radeon_combios_output_lock(encoder, true); 1116 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 1117 } 1118 1119 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 1120 { 1121 struct radeon_device *rdev = encoder->dev->dev_private; 1122 1123 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); 1124 1125 if (rdev->is_atom_bios) 1126 radeon_atom_output_lock(encoder, true); 1127 else 1128 radeon_combios_output_lock(encoder, true); 1129 } 1130 1131 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, 1132 struct drm_display_mode *mode, 1133 struct drm_display_mode *adjusted_mode) 1134 { 1135 struct drm_device *dev = encoder->dev; 1136 struct radeon_device *rdev = dev->dev_private; 1137 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1139 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1140 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 1141 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 1142 bool is_tv = false; 1143 1144 DRM_DEBUG_KMS("\n"); 1145 1146 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1147 1148 if (rdev->family != CHIP_R200) { 1149 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1150 if (rdev->family == CHIP_R420 || 1151 rdev->family == CHIP_R423 || 1152 rdev->family == CHIP_RV410) { 1153 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1154 RADEON_TV_DAC_BGADJ_MASK | 1155 R420_TV_DAC_DACADJ_MASK | 1156 R420_TV_DAC_RDACPD | 1157 R420_TV_DAC_GDACPD | 1158 R420_TV_DAC_BDACPD | 1159 R420_TV_DAC_TVENABLE); 1160 } else { 1161 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1162 RADEON_TV_DAC_BGADJ_MASK | 1163 RADEON_TV_DAC_DACADJ_MASK | 1164 RADEON_TV_DAC_RDACPD | 1165 RADEON_TV_DAC_GDACPD | 1166 RADEON_TV_DAC_BDACPD); 1167 } 1168 1169 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 1170 1171 if (is_tv) { 1172 if (tv_dac->tv_std == TV_STD_NTSC || 1173 tv_dac->tv_std == TV_STD_NTSC_J || 1174 tv_dac->tv_std == TV_STD_PAL_M || 1175 tv_dac->tv_std == TV_STD_PAL_60) 1176 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; 1177 else 1178 tv_dac_cntl |= tv_dac->pal_tvdac_adj; 1179 1180 if (tv_dac->tv_std == TV_STD_NTSC || 1181 tv_dac->tv_std == TV_STD_NTSC_J) 1182 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 1183 else 1184 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 1185 } else 1186 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | 1187 tv_dac->ps2_tvdac_adj); 1188 1189 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1190 } 1191 1192 if (ASIC_IS_R300(rdev)) { 1193 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 1194 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1195 } else if (rdev->family != CHIP_R200) 1196 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1197 else if (rdev->family == CHIP_R200) 1198 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1199 1200 if (rdev->family >= CHIP_R200) 1201 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); 1202 1203 if (is_tv) { 1204 uint32_t dac_cntl; 1205 1206 dac_cntl = RREG32(RADEON_DAC_CNTL); 1207 dac_cntl &= ~RADEON_DAC_TVO_EN; 1208 WREG32(RADEON_DAC_CNTL, dac_cntl); 1209 1210 if (ASIC_IS_R300(rdev)) 1211 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; 1212 1213 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; 1214 if (radeon_crtc->crtc_id == 0) { 1215 if (ASIC_IS_R300(rdev)) { 1216 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1217 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | 1218 RADEON_DISP_TV_SOURCE_CRTC); 1219 } 1220 if (rdev->family >= CHIP_R200) { 1221 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; 1222 } else { 1223 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1224 } 1225 } else { 1226 if (ASIC_IS_R300(rdev)) { 1227 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1228 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; 1229 } 1230 if (rdev->family >= CHIP_R200) { 1231 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; 1232 } else { 1233 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1234 } 1235 } 1236 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1237 } else { 1238 1239 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 1240 1241 if (radeon_crtc->crtc_id == 0) { 1242 if (ASIC_IS_R300(rdev)) { 1243 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1244 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1245 } else if (rdev->family == CHIP_R200) { 1246 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1247 RADEON_FP2_DVO_RATE_SEL_SDR); 1248 } else 1249 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1250 } else { 1251 if (ASIC_IS_R300(rdev)) { 1252 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1253 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1254 } else if (rdev->family == CHIP_R200) { 1255 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1256 RADEON_FP2_DVO_RATE_SEL_SDR); 1257 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1258 } else 1259 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1260 } 1261 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1262 } 1263 1264 if (ASIC_IS_R300(rdev)) { 1265 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1266 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1267 } else if (rdev->family != CHIP_R200) 1268 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1269 else if (rdev->family == CHIP_R200) 1270 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1271 1272 if (rdev->family >= CHIP_R200) 1273 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); 1274 1275 if (is_tv) 1276 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); 1277 1278 if (rdev->is_atom_bios) 1279 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1280 else 1281 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1282 1283 } 1284 1285 static bool r300_legacy_tv_detect(struct drm_encoder *encoder, 1286 struct drm_connector *connector) 1287 { 1288 struct drm_device *dev = encoder->dev; 1289 struct radeon_device *rdev = dev->dev_private; 1290 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1291 uint32_t disp_output_cntl, gpiopad_a, tmp; 1292 bool found = false; 1293 1294 /* save regs needed */ 1295 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1296 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1297 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1298 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1299 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1300 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1301 1302 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1303 1304 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); 1305 1306 WREG32(RADEON_CRTC2_GEN_CNTL, 1307 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); 1308 1309 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1310 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1311 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1312 1313 WREG32(RADEON_DAC_EXT_CNTL, 1314 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1315 RADEON_DAC2_FORCE_DATA_EN | 1316 RADEON_DAC_FORCE_DATA_SEL_RGB | 1317 (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); 1318 1319 WREG32(RADEON_TV_DAC_CNTL, 1320 RADEON_TV_DAC_STD_NTSC | 1321 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1322 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1323 1324 RREG32(RADEON_TV_DAC_CNTL); 1325 mdelay(4); 1326 1327 WREG32(RADEON_TV_DAC_CNTL, 1328 RADEON_TV_DAC_NBLANK | 1329 RADEON_TV_DAC_NHOLD | 1330 RADEON_TV_MONITOR_DETECT_EN | 1331 RADEON_TV_DAC_STD_NTSC | 1332 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1333 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1334 1335 RREG32(RADEON_TV_DAC_CNTL); 1336 mdelay(6); 1337 1338 tmp = RREG32(RADEON_TV_DAC_CNTL); 1339 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1340 found = true; 1341 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1342 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1343 found = true; 1344 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1345 } 1346 1347 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1348 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1349 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1350 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1351 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1352 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1353 return found; 1354 } 1355 1356 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, 1357 struct drm_connector *connector) 1358 { 1359 struct drm_device *dev = encoder->dev; 1360 struct radeon_device *rdev = dev->dev_private; 1361 uint32_t tv_dac_cntl, dac_cntl2; 1362 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; 1363 bool found = false; 1364 1365 if (ASIC_IS_R300(rdev)) 1366 return r300_legacy_tv_detect(encoder, connector); 1367 1368 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1369 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1370 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1371 config_cntl = RREG32(RADEON_CONFIG_CNTL); 1372 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); 1373 1374 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 1375 WREG32(RADEON_DAC_CNTL2, tmp); 1376 1377 tmp = tv_master_cntl | RADEON_TV_ON; 1378 tmp &= ~(RADEON_TV_ASYNC_RST | 1379 RADEON_RESTART_PHASE_FIX | 1380 RADEON_CRT_FIFO_CE_EN | 1381 RADEON_TV_FIFO_CE_EN | 1382 RADEON_RE_SYNC_NOW_SEL_MASK); 1383 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 1384 WREG32(RADEON_TV_MASTER_CNTL, tmp); 1385 1386 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 1387 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 1388 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 1389 1390 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 1391 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 1392 else 1393 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 1394 WREG32(RADEON_TV_DAC_CNTL, tmp); 1395 1396 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 1397 RADEON_RED_MX_FORCE_DAC_DATA | 1398 RADEON_GRN_MX_FORCE_DAC_DATA | 1399 RADEON_BLU_MX_FORCE_DAC_DATA | 1400 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 1401 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 1402 1403 mdelay(3); 1404 tmp = RREG32(RADEON_TV_DAC_CNTL); 1405 if (tmp & RADEON_TV_DAC_GDACDET) { 1406 found = true; 1407 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1408 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1409 found = true; 1410 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1411 } 1412 1413 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1414 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1415 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1416 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1417 return found; 1418 } 1419 1420 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1421 struct drm_connector *connector) 1422 { 1423 struct drm_device *dev = encoder->dev; 1424 struct radeon_device *rdev = dev->dev_private; 1425 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1426 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; 1427 enum drm_connector_status found = connector_status_disconnected; 1428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1429 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1430 bool color = true; 1431 struct drm_crtc *crtc; 1432 1433 /* find out if crtc2 is in use or if this encoder is using it */ 1434 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1435 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1436 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { 1437 if (encoder->crtc != crtc) { 1438 return connector_status_disconnected; 1439 } 1440 } 1441 } 1442 1443 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1444 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1445 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { 1446 bool tv_detect; 1447 1448 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) 1449 return connector_status_disconnected; 1450 1451 tv_detect = radeon_legacy_tv_detect(encoder, connector); 1452 if (tv_detect && tv_dac) 1453 found = connector_status_connected; 1454 return found; 1455 } 1456 1457 /* don't probe if the encoder is being used for something else not CRT related */ 1458 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { 1459 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); 1460 return connector_status_disconnected; 1461 } 1462 1463 /* save the regs we need */ 1464 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1465 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0; 1466 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0; 1467 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG); 1468 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1469 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1470 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1471 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1472 1473 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1474 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1475 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1476 1477 if (ASIC_IS_R300(rdev)) 1478 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1479 1480 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1481 tmp |= RADEON_CRTC2_CRT2_ON | 1482 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1483 1484 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 1485 1486 if (ASIC_IS_R300(rdev)) { 1487 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1488 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1489 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1490 } else { 1491 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1492 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1493 } 1494 1495 tmp = RADEON_TV_DAC_NBLANK | 1496 RADEON_TV_DAC_NHOLD | 1497 RADEON_TV_MONITOR_DETECT_EN | 1498 RADEON_TV_DAC_STD_PS2; 1499 1500 WREG32(RADEON_TV_DAC_CNTL, tmp); 1501 1502 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1503 RADEON_DAC2_FORCE_DATA_EN; 1504 1505 if (color) 1506 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1507 else 1508 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1509 1510 if (ASIC_IS_R300(rdev)) 1511 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1512 else 1513 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1514 1515 WREG32(RADEON_DAC_EXT_CNTL, tmp); 1516 1517 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1518 WREG32(RADEON_DAC_CNTL2, tmp); 1519 1520 mdelay(10); 1521 1522 if (ASIC_IS_R300(rdev)) { 1523 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1524 found = connector_status_connected; 1525 } else { 1526 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) 1527 found = connector_status_connected; 1528 } 1529 1530 /* restore regs we used */ 1531 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1532 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1533 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1534 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1535 1536 if (ASIC_IS_R300(rdev)) { 1537 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1538 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1539 } else { 1540 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1541 } 1542 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1543 1544 return found; 1545 1546 } 1547 1548 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { 1549 .dpms = radeon_legacy_tv_dac_dpms, 1550 .mode_fixup = radeon_legacy_mode_fixup, 1551 .prepare = radeon_legacy_tv_dac_prepare, 1552 .mode_set = radeon_legacy_tv_dac_mode_set, 1553 .commit = radeon_legacy_tv_dac_commit, 1554 .detect = radeon_legacy_tv_dac_detect, 1555 .disable = radeon_legacy_encoder_disable, 1556 }; 1557 1558 1559 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { 1560 .destroy = radeon_enc_destroy, 1561 }; 1562 1563 1564 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) 1565 { 1566 struct drm_device *dev = encoder->base.dev; 1567 struct radeon_device *rdev = dev->dev_private; 1568 struct radeon_encoder_int_tmds *tmds = NULL; 1569 bool ret; 1570 1571 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); 1572 1573 if (!tmds) 1574 return NULL; 1575 1576 if (rdev->is_atom_bios) 1577 ret = radeon_atombios_get_tmds_info(encoder, tmds); 1578 else 1579 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); 1580 1581 if (ret == false) 1582 radeon_legacy_get_tmds_info_from_table(encoder, tmds); 1583 1584 return tmds; 1585 } 1586 1587 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) 1588 { 1589 struct drm_device *dev = encoder->base.dev; 1590 struct radeon_device *rdev = dev->dev_private; 1591 struct radeon_encoder_ext_tmds *tmds = NULL; 1592 bool ret; 1593 1594 if (rdev->is_atom_bios) 1595 return NULL; 1596 1597 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); 1598 1599 if (!tmds) 1600 return NULL; 1601 1602 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); 1603 1604 if (ret == false) 1605 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); 1606 1607 return tmds; 1608 } 1609 1610 void 1611 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 1612 { 1613 struct radeon_device *rdev = dev->dev_private; 1614 struct drm_encoder *encoder; 1615 struct radeon_encoder *radeon_encoder; 1616 1617 /* see if we already added it */ 1618 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1619 radeon_encoder = to_radeon_encoder(encoder); 1620 if (radeon_encoder->encoder_enum == encoder_enum) { 1621 radeon_encoder->devices |= supported_device; 1622 return; 1623 } 1624 1625 } 1626 1627 /* add a new one */ 1628 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1629 if (!radeon_encoder) 1630 return; 1631 1632 encoder = &radeon_encoder->base; 1633 if (rdev->flags & RADEON_SINGLE_CRTC) 1634 encoder->possible_crtcs = 0x1; 1635 else 1636 encoder->possible_crtcs = 0x3; 1637 1638 radeon_encoder->enc_priv = NULL; 1639 1640 radeon_encoder->encoder_enum = encoder_enum; 1641 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1642 radeon_encoder->devices = supported_device; 1643 radeon_encoder->rmx_type = RMX_OFF; 1644 1645 switch (radeon_encoder->encoder_id) { 1646 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1647 encoder->possible_crtcs = 0x1; 1648 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); 1649 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1650 if (rdev->is_atom_bios) 1651 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1652 else 1653 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); 1654 radeon_encoder->rmx_type = RMX_FULL; 1655 break; 1656 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1657 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); 1658 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1659 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); 1660 break; 1661 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1662 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); 1663 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); 1664 if (rdev->is_atom_bios) 1665 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); 1666 else 1667 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); 1668 break; 1669 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1670 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); 1671 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); 1672 if (rdev->is_atom_bios) 1673 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); 1674 else 1675 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); 1676 break; 1677 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1678 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); 1679 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); 1680 if (!rdev->is_atom_bios) 1681 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); 1682 break; 1683 } 1684 } 1685