1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 static void radeon_overscan_setup(struct drm_crtc *crtc, 34 struct drm_display_mode *mode) 35 { 36 struct drm_device *dev = crtc->dev; 37 struct radeon_device *rdev = dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 43 } 44 45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 46 struct drm_display_mode *mode) 47 { 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 int xres = mode->hdisplay; 52 int yres = mode->vdisplay; 53 bool hscale = true, vscale = true; 54 int hsync_wid; 55 int vsync_wid; 56 int hsync_start; 57 int blank_width; 58 u32 scale, inc, crtc_more_cntl; 59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 63 64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 65 (RADEON_VERT_STRETCH_RESERVED | 66 RADEON_VERT_AUTO_RATIO_INC); 67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 68 (RADEON_HORZ_FP_LOOP_STRETCH | 69 RADEON_HORZ_AUTO_RATIO_INC); 70 71 crtc_more_cntl = 0; 72 if ((rdev->family == CHIP_RS100) || 73 (rdev->family == CHIP_RS200)) { 74 /* This is to workaround the asic bug for RMX, some versions 75 of BIOS dosen't have this register initialized correctly. */ 76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 77 } 78 79 80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 82 83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 84 if (!hsync_wid) 85 hsync_wid = 1; 86 hsync_start = mode->crtc_hsync_start - 8; 87 88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 89 | ((hsync_wid & 0x3f) << 16) 90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 91 ? RADEON_CRTC_H_SYNC_POL 92 : 0)); 93 94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 95 | ((mode->crtc_vdisplay - 1) << 16)); 96 97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 98 if (!vsync_wid) 99 vsync_wid = 1; 100 101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 102 | ((vsync_wid & 0x1f) << 16) 103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 104 ? RADEON_CRTC_V_SYNC_POL 105 : 0)); 106 107 fp_horz_vert_active = 0; 108 109 if (native_mode->hdisplay == 0 || 110 native_mode->vdisplay == 0) { 111 hscale = false; 112 vscale = false; 113 } else { 114 if (xres > native_mode->hdisplay) 115 xres = native_mode->hdisplay; 116 if (yres > native_mode->vdisplay) 117 yres = native_mode->vdisplay; 118 119 if (xres == native_mode->hdisplay) 120 hscale = false; 121 if (yres == native_mode->vdisplay) 122 vscale = false; 123 } 124 125 switch (radeon_crtc->rmx_type) { 126 case RMX_FULL: 127 case RMX_ASPECT: 128 if (!hscale) 129 fp_horz_stretch |= ((xres/8-1) << 16); 130 else { 131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 133 / native_mode->hdisplay + 1; 134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 135 RADEON_HORZ_STRETCH_BLEND | 136 RADEON_HORZ_STRETCH_ENABLE | 137 ((native_mode->hdisplay/8-1) << 16)); 138 } 139 140 if (!vscale) 141 fp_vert_stretch |= ((yres-1) << 12); 142 else { 143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 145 / native_mode->vdisplay + 1; 146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 147 RADEON_VERT_STRETCH_ENABLE | 148 RADEON_VERT_STRETCH_BLEND | 149 ((native_mode->vdisplay-1) << 12)); 150 } 151 break; 152 case RMX_CENTER: 153 fp_horz_stretch |= ((xres/8-1) << 16); 154 fp_vert_stretch |= ((yres-1) << 12); 155 156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 157 RADEON_CRTC_AUTO_VERT_CENTER_EN); 158 159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 160 if (blank_width > 110) 161 blank_width = 110; 162 163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 165 166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 167 if (!hsync_wid) 168 hsync_wid = 1; 169 170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 171 | ((hsync_wid & 0x3f) << 16) 172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 173 ? RADEON_CRTC_H_SYNC_POL 174 : 0)); 175 176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 177 | ((mode->crtc_vdisplay - 1) << 16)); 178 179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 180 if (!vsync_wid) 181 vsync_wid = 1; 182 183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 184 | ((vsync_wid & 0x1f) << 16) 185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 186 ? RADEON_CRTC_V_SYNC_POL 187 : 0))); 188 189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 190 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 191 break; 192 case RMX_OFF: 193 default: 194 fp_horz_stretch |= ((xres/8-1) << 16); 195 fp_vert_stretch |= ((yres-1) << 12); 196 break; 197 } 198 199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 207 } 208 209 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 210 { 211 struct radeon_device *rdev = dev->dev_private; 212 int i = 0; 213 214 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 215 the cause yet, but this workaround will mask the problem for now. 216 Other chips usually will pass at the very first test, so the 217 workaround shouldn't have any effect on them. */ 218 for (i = 0; 219 (i < 10000 && 220 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 221 i++); 222 } 223 224 static void radeon_pll_write_update(struct drm_device *dev) 225 { 226 struct radeon_device *rdev = dev->dev_private; 227 228 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 229 230 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 231 RADEON_PPLL_ATOMIC_UPDATE_W, 232 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 233 } 234 235 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 236 { 237 struct radeon_device *rdev = dev->dev_private; 238 int i = 0; 239 240 241 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 242 the cause yet, but this workaround will mask the problem for now. 243 Other chips usually will pass at the very first test, so the 244 workaround shouldn't have any effect on them. */ 245 for (i = 0; 246 (i < 10000 && 247 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 248 i++); 249 } 250 251 static void radeon_pll2_write_update(struct drm_device *dev) 252 { 253 struct radeon_device *rdev = dev->dev_private; 254 255 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 256 257 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 258 RADEON_P2PLL_ATOMIC_UPDATE_W, 259 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 260 } 261 262 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 263 uint16_t fb_div) 264 { 265 unsigned int vcoFreq; 266 267 if (!ref_div) 268 return 1; 269 270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 271 272 /* 273 * This is horribly crude: the VCO frequency range is divided into 274 * 3 parts, each part having a fixed PLL gain value. 275 */ 276 if (vcoFreq >= 30000) 277 /* 278 * [300..max] MHz : 7 279 */ 280 return 7; 281 else if (vcoFreq >= 18000) 282 /* 283 * [180..300) MHz : 4 284 */ 285 return 4; 286 else 287 /* 288 * [0..180) MHz : 1 289 */ 290 return 1; 291 } 292 293 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 294 { 295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 296 struct drm_device *dev = crtc->dev; 297 struct radeon_device *rdev = dev->dev_private; 298 uint32_t mask; 299 300 if (radeon_crtc->crtc_id) 301 mask = (RADEON_CRTC2_DISP_DIS | 302 RADEON_CRTC2_VSYNC_DIS | 303 RADEON_CRTC2_HSYNC_DIS | 304 RADEON_CRTC2_DISP_REQ_EN_B); 305 else 306 mask = (RADEON_CRTC_DISPLAY_DIS | 307 RADEON_CRTC_VSYNC_DIS | 308 RADEON_CRTC_HSYNC_DIS); 309 310 switch (mode) { 311 case DRM_MODE_DPMS_ON: 312 radeon_crtc->enabled = true; 313 /* adjust pm to dpms changes BEFORE enabling crtcs */ 314 radeon_pm_compute_clocks(rdev); 315 if (radeon_crtc->crtc_id) 316 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 317 else { 318 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 319 RADEON_CRTC_DISP_REQ_EN_B)); 320 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 321 } 322 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 323 radeon_crtc_load_lut(crtc); 324 break; 325 case DRM_MODE_DPMS_STANDBY: 326 case DRM_MODE_DPMS_SUSPEND: 327 case DRM_MODE_DPMS_OFF: 328 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 329 if (radeon_crtc->crtc_id) 330 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 331 else { 332 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 333 RADEON_CRTC_DISP_REQ_EN_B)); 334 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); 335 } 336 radeon_crtc->enabled = false; 337 /* adjust pm to dpms changes AFTER disabling crtcs */ 338 radeon_pm_compute_clocks(rdev); 339 break; 340 } 341 } 342 343 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 344 struct drm_framebuffer *old_fb) 345 { 346 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 347 } 348 349 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 350 struct drm_framebuffer *fb, 351 int x, int y, enum mode_set_atomic state) 352 { 353 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 354 } 355 356 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 357 struct drm_framebuffer *fb, 358 int x, int y, int atomic) 359 { 360 struct drm_device *dev = crtc->dev; 361 struct radeon_device *rdev = dev->dev_private; 362 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 363 struct radeon_framebuffer *radeon_fb; 364 struct drm_framebuffer *target_fb; 365 struct drm_gem_object *obj; 366 struct radeon_bo *rbo; 367 uint64_t base; 368 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 369 uint32_t crtc_pitch, pitch_pixels; 370 uint32_t tiling_flags; 371 int format; 372 uint32_t gen_cntl_reg, gen_cntl_val; 373 int r; 374 375 DRM_DEBUG_KMS("\n"); 376 /* no fb bound */ 377 if (!atomic && !crtc->fb) { 378 DRM_DEBUG_KMS("No FB bound\n"); 379 return 0; 380 } 381 382 if (atomic) { 383 radeon_fb = to_radeon_framebuffer(fb); 384 target_fb = fb; 385 } 386 else { 387 radeon_fb = to_radeon_framebuffer(crtc->fb); 388 target_fb = crtc->fb; 389 } 390 391 switch (target_fb->bits_per_pixel) { 392 case 8: 393 format = 2; 394 break; 395 case 15: /* 555 */ 396 format = 3; 397 break; 398 case 16: /* 565 */ 399 format = 4; 400 break; 401 case 24: /* RGB */ 402 format = 5; 403 break; 404 case 32: /* xRGB */ 405 format = 6; 406 break; 407 default: 408 return false; 409 } 410 411 /* Pin framebuffer & get tilling informations */ 412 obj = radeon_fb->obj; 413 rbo = gem_to_radeon_bo(obj); 414 r = radeon_bo_reserve(rbo, false); 415 if (unlikely(r != 0)) 416 return r; 417 /* Only 27 bit offset for legacy CRTC */ 418 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 419 &base); 420 if (unlikely(r != 0)) { 421 radeon_bo_unreserve(rbo); 422 return -EINVAL; 423 } 424 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 425 radeon_bo_unreserve(rbo); 426 if (tiling_flags & RADEON_TILING_MICRO) 427 DRM_ERROR("trying to scanout microtiled buffer\n"); 428 429 /* if scanout was in GTT this really wouldn't work */ 430 /* crtc offset is from display base addr not FB location */ 431 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 432 433 base -= radeon_crtc->legacy_display_base_addr; 434 435 crtc_offset_cntl = 0; 436 437 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 438 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + 439 ((target_fb->bits_per_pixel * 8) - 1)) / 440 (target_fb->bits_per_pixel * 8)); 441 crtc_pitch |= crtc_pitch << 16; 442 443 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 444 if (tiling_flags & RADEON_TILING_MACRO) { 445 if (ASIC_IS_R300(rdev)) 446 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 447 R300_CRTC_MICRO_TILE_BUFFER_DIS | 448 R300_CRTC_MACRO_TILE_EN); 449 else 450 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 451 } else { 452 if (ASIC_IS_R300(rdev)) 453 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 454 R300_CRTC_MICRO_TILE_BUFFER_DIS | 455 R300_CRTC_MACRO_TILE_EN); 456 else 457 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 458 } 459 460 if (tiling_flags & RADEON_TILING_MACRO) { 461 if (ASIC_IS_R300(rdev)) { 462 crtc_tile_x0_y0 = x | (y << 16); 463 base &= ~0x7ff; 464 } else { 465 int byteshift = target_fb->bits_per_pixel >> 4; 466 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 467 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 468 crtc_offset_cntl |= (y % 16); 469 } 470 } else { 471 int offset = y * pitch_pixels + x; 472 switch (target_fb->bits_per_pixel) { 473 case 8: 474 offset *= 1; 475 break; 476 case 15: 477 case 16: 478 offset *= 2; 479 break; 480 case 24: 481 offset *= 3; 482 break; 483 case 32: 484 offset *= 4; 485 break; 486 default: 487 return false; 488 } 489 base += offset; 490 } 491 492 base &= ~7; 493 494 if (radeon_crtc->crtc_id == 1) 495 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 496 else 497 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 498 499 gen_cntl_val = RREG32(gen_cntl_reg); 500 gen_cntl_val &= ~(0xf << 8); 501 gen_cntl_val |= (format << 8); 502 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 503 WREG32(gen_cntl_reg, gen_cntl_val); 504 505 crtc_offset = (u32)base; 506 507 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 508 509 if (ASIC_IS_R300(rdev)) { 510 if (radeon_crtc->crtc_id) 511 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 512 else 513 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 514 } 515 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 516 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 517 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 518 519 if (!atomic && fb && fb != crtc->fb) { 520 radeon_fb = to_radeon_framebuffer(fb); 521 rbo = gem_to_radeon_bo(radeon_fb->obj); 522 r = radeon_bo_reserve(rbo, false); 523 if (unlikely(r != 0)) 524 return r; 525 radeon_bo_unpin(rbo); 526 radeon_bo_unreserve(rbo); 527 } 528 529 /* Bytes per pixel may have changed */ 530 radeon_bandwidth_update(rdev); 531 532 return 0; 533 } 534 535 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 536 { 537 struct drm_device *dev = crtc->dev; 538 struct radeon_device *rdev = dev->dev_private; 539 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 540 struct drm_encoder *encoder; 541 int format; 542 int hsync_start; 543 int hsync_wid; 544 int vsync_wid; 545 uint32_t crtc_h_total_disp; 546 uint32_t crtc_h_sync_strt_wid; 547 uint32_t crtc_v_total_disp; 548 uint32_t crtc_v_sync_strt_wid; 549 bool is_tv = false; 550 551 DRM_DEBUG_KMS("\n"); 552 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 553 if (encoder->crtc == crtc) { 554 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 555 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 556 is_tv = true; 557 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 558 break; 559 } 560 } 561 } 562 563 switch (crtc->fb->bits_per_pixel) { 564 case 8: 565 format = 2; 566 break; 567 case 15: /* 555 */ 568 format = 3; 569 break; 570 case 16: /* 565 */ 571 format = 4; 572 break; 573 case 24: /* RGB */ 574 format = 5; 575 break; 576 case 32: /* xRGB */ 577 format = 6; 578 break; 579 default: 580 return false; 581 } 582 583 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 584 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 585 586 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 587 if (!hsync_wid) 588 hsync_wid = 1; 589 hsync_start = mode->crtc_hsync_start - 8; 590 591 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 592 | ((hsync_wid & 0x3f) << 16) 593 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 594 ? RADEON_CRTC_H_SYNC_POL 595 : 0)); 596 597 /* This works for double scan mode. */ 598 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 599 | ((mode->crtc_vdisplay - 1) << 16)); 600 601 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 602 if (!vsync_wid) 603 vsync_wid = 1; 604 605 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 606 | ((vsync_wid & 0x1f) << 16) 607 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 608 ? RADEON_CRTC_V_SYNC_POL 609 : 0)); 610 611 if (radeon_crtc->crtc_id) { 612 uint32_t crtc2_gen_cntl; 613 uint32_t disp2_merge_cntl; 614 615 /* if TV DAC is enabled for another crtc and keep it enabled */ 616 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 617 crtc2_gen_cntl |= ((format << 8) 618 | RADEON_CRTC2_VSYNC_DIS 619 | RADEON_CRTC2_HSYNC_DIS 620 | RADEON_CRTC2_DISP_DIS 621 | RADEON_CRTC2_DISP_REQ_EN_B 622 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 623 ? RADEON_CRTC2_DBL_SCAN_EN 624 : 0) 625 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 626 ? RADEON_CRTC2_CSYNC_EN 627 : 0) 628 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 629 ? RADEON_CRTC2_INTERLACE_EN 630 : 0)); 631 632 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 633 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 634 crtc2_gen_cntl |= RADEON_CRTC2_EN; 635 636 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 637 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 638 639 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 640 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 641 642 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 643 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 644 } else { 645 uint32_t crtc_gen_cntl; 646 uint32_t crtc_ext_cntl; 647 uint32_t disp_merge_cntl; 648 649 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 650 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 651 | (format << 8) 652 | RADEON_CRTC_DISP_REQ_EN_B 653 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 654 ? RADEON_CRTC_DBL_SCAN_EN 655 : 0) 656 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 657 ? RADEON_CRTC_CSYNC_EN 658 : 0) 659 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 660 ? RADEON_CRTC_INTERLACE_EN 661 : 0)); 662 663 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 664 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 665 crtc_gen_cntl |= RADEON_CRTC_EN; 666 667 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 668 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 669 RADEON_CRTC_VSYNC_DIS | 670 RADEON_CRTC_HSYNC_DIS | 671 RADEON_CRTC_DISPLAY_DIS); 672 673 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 674 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 675 676 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 677 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 678 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 679 } 680 681 if (is_tv) 682 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 683 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 684 &crtc_v_sync_strt_wid); 685 686 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 687 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 688 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 689 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 690 691 return true; 692 } 693 694 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 695 { 696 struct drm_device *dev = crtc->dev; 697 struct radeon_device *rdev = dev->dev_private; 698 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 699 struct drm_encoder *encoder; 700 uint32_t feedback_div = 0; 701 uint32_t frac_fb_div = 0; 702 uint32_t reference_div = 0; 703 uint32_t post_divider = 0; 704 uint32_t freq = 0; 705 uint8_t pll_gain; 706 bool use_bios_divs = false; 707 /* PLL registers */ 708 uint32_t pll_ref_div = 0; 709 uint32_t pll_fb_post_div = 0; 710 uint32_t htotal_cntl = 0; 711 bool is_tv = false; 712 struct radeon_pll *pll; 713 714 struct { 715 int divider; 716 int bitvalue; 717 } *post_div, post_divs[] = { 718 /* From RAGE 128 VR/RAGE 128 GL Register 719 * Reference Manual (Technical Reference 720 * Manual P/N RRG-G04100-C Rev. 0.04), page 721 * 3-17 (PLL_DIV_[3:0]). 722 */ 723 { 1, 0 }, /* VCLK_SRC */ 724 { 2, 1 }, /* VCLK_SRC/2 */ 725 { 4, 2 }, /* VCLK_SRC/4 */ 726 { 8, 3 }, /* VCLK_SRC/8 */ 727 { 3, 4 }, /* VCLK_SRC/3 */ 728 { 16, 5 }, /* VCLK_SRC/16 */ 729 { 6, 6 }, /* VCLK_SRC/6 */ 730 { 12, 7 }, /* VCLK_SRC/12 */ 731 { 0, 0 } 732 }; 733 734 if (radeon_crtc->crtc_id) 735 pll = &rdev->clock.p2pll; 736 else 737 pll = &rdev->clock.p1pll; 738 739 pll->flags = RADEON_PLL_LEGACY; 740 741 if (mode->clock > 200000) /* range limits??? */ 742 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 743 else 744 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 745 746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 747 if (encoder->crtc == crtc) { 748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 749 750 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 751 is_tv = true; 752 break; 753 } 754 755 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 756 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 757 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 758 if (!rdev->is_atom_bios) { 759 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 760 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 761 if (lvds) { 762 if (lvds->use_bios_dividers) { 763 pll_ref_div = lvds->panel_ref_divider; 764 pll_fb_post_div = (lvds->panel_fb_divider | 765 (lvds->panel_post_divider << 16)); 766 htotal_cntl = 0; 767 use_bios_divs = true; 768 } 769 } 770 } 771 pll->flags |= RADEON_PLL_USE_REF_DIV; 772 } 773 } 774 } 775 776 DRM_DEBUG_KMS("\n"); 777 778 if (!use_bios_divs) { 779 radeon_compute_pll_legacy(pll, mode->clock, 780 &freq, &feedback_div, &frac_fb_div, 781 &reference_div, &post_divider); 782 783 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 784 if (post_div->divider == post_divider) 785 break; 786 } 787 788 if (!post_div->divider) 789 post_div = &post_divs[0]; 790 791 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 792 (unsigned)freq, 793 feedback_div, 794 reference_div, 795 post_divider); 796 797 pll_ref_div = reference_div; 798 #if defined(__powerpc__) && (0) /* TODO */ 799 /* apparently programming this otherwise causes a hang??? */ 800 if (info->MacModel == RADEON_MAC_IBOOK) 801 pll_fb_post_div = 0x000600ad; 802 else 803 #endif 804 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 805 806 htotal_cntl = mode->htotal & 0x7; 807 808 } 809 810 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 811 pll_ref_div & 0x3ff, 812 pll_fb_post_div & 0x7ff); 813 814 if (radeon_crtc->crtc_id) { 815 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 816 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 817 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 818 819 if (is_tv) { 820 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 821 &pll_ref_div, &pll_fb_post_div, 822 &pixclks_cntl); 823 } 824 825 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 826 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 827 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 828 829 WREG32_PLL_P(RADEON_P2PLL_CNTL, 830 RADEON_P2PLL_RESET 831 | RADEON_P2PLL_ATOMIC_UPDATE_EN 832 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 833 ~(RADEON_P2PLL_RESET 834 | RADEON_P2PLL_ATOMIC_UPDATE_EN 835 | RADEON_P2PLL_PVG_MASK)); 836 837 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 838 pll_ref_div, 839 ~RADEON_P2PLL_REF_DIV_MASK); 840 841 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 842 pll_fb_post_div, 843 ~RADEON_P2PLL_FB0_DIV_MASK); 844 845 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 846 pll_fb_post_div, 847 ~RADEON_P2PLL_POST0_DIV_MASK); 848 849 radeon_pll2_write_update(dev); 850 radeon_pll2_wait_for_read_update_complete(dev); 851 852 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 853 854 WREG32_PLL_P(RADEON_P2PLL_CNTL, 855 0, 856 ~(RADEON_P2PLL_RESET 857 | RADEON_P2PLL_SLEEP 858 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 859 860 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 861 (unsigned)pll_ref_div, 862 (unsigned)pll_fb_post_div, 863 (unsigned)htotal_cntl, 864 RREG32_PLL(RADEON_P2PLL_CNTL)); 865 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 866 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 867 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 868 (unsigned)((pll_fb_post_div & 869 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 870 871 mdelay(50); /* Let the clock to lock */ 872 873 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 874 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 875 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 876 877 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 878 } else { 879 uint32_t pixclks_cntl; 880 881 882 if (is_tv) { 883 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 884 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 885 &pll_fb_post_div, &pixclks_cntl); 886 } 887 888 if (rdev->flags & RADEON_IS_MOBILITY) { 889 /* A temporal workaround for the occasional blanking on certain laptop panels. 890 This appears to related to the PLL divider registers (fail to lock?). 891 It occurs even when all dividers are the same with their old settings. 892 In this case we really don't need to fiddle with PLL registers. 893 By doing this we can avoid the blanking problem with some panels. 894 */ 895 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 896 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 897 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 898 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 899 RADEON_PLL_DIV_SEL, 900 ~(RADEON_PLL_DIV_SEL)); 901 r100_pll_errata_after_index(rdev); 902 return; 903 } 904 } 905 906 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 907 RADEON_VCLK_SRC_SEL_CPUCLK, 908 ~(RADEON_VCLK_SRC_SEL_MASK)); 909 WREG32_PLL_P(RADEON_PPLL_CNTL, 910 RADEON_PPLL_RESET 911 | RADEON_PPLL_ATOMIC_UPDATE_EN 912 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 913 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 914 ~(RADEON_PPLL_RESET 915 | RADEON_PPLL_ATOMIC_UPDATE_EN 916 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 917 | RADEON_PPLL_PVG_MASK)); 918 919 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 920 RADEON_PLL_DIV_SEL, 921 ~(RADEON_PLL_DIV_SEL)); 922 r100_pll_errata_after_index(rdev); 923 924 if (ASIC_IS_R300(rdev) || 925 (rdev->family == CHIP_RS300) || 926 (rdev->family == CHIP_RS400) || 927 (rdev->family == CHIP_RS480)) { 928 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 929 /* When restoring console mode, use saved PPLL_REF_DIV 930 * setting. 931 */ 932 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 933 pll_ref_div, 934 0); 935 } else { 936 /* R300 uses ref_div_acc field as real ref divider */ 937 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 938 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 939 ~R300_PPLL_REF_DIV_ACC_MASK); 940 } 941 } else 942 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 943 pll_ref_div, 944 ~RADEON_PPLL_REF_DIV_MASK); 945 946 WREG32_PLL_P(RADEON_PPLL_DIV_3, 947 pll_fb_post_div, 948 ~RADEON_PPLL_FB3_DIV_MASK); 949 950 WREG32_PLL_P(RADEON_PPLL_DIV_3, 951 pll_fb_post_div, 952 ~RADEON_PPLL_POST3_DIV_MASK); 953 954 radeon_pll_write_update(dev); 955 radeon_pll_wait_for_read_update_complete(dev); 956 957 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 958 959 WREG32_PLL_P(RADEON_PPLL_CNTL, 960 0, 961 ~(RADEON_PPLL_RESET 962 | RADEON_PPLL_SLEEP 963 | RADEON_PPLL_ATOMIC_UPDATE_EN 964 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 965 966 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 967 pll_ref_div, 968 pll_fb_post_div, 969 (unsigned)htotal_cntl, 970 RREG32_PLL(RADEON_PPLL_CNTL)); 971 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 972 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 973 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 974 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 975 976 mdelay(50); /* Let the clock to lock */ 977 978 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 979 RADEON_VCLK_SRC_SEL_PPLLCLK, 980 ~(RADEON_VCLK_SRC_SEL_MASK)); 981 982 if (is_tv) 983 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 984 } 985 } 986 987 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 988 const struct drm_display_mode *mode, 989 struct drm_display_mode *adjusted_mode) 990 { 991 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 992 return false; 993 return true; 994 } 995 996 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 997 struct drm_display_mode *mode, 998 struct drm_display_mode *adjusted_mode, 999 int x, int y, struct drm_framebuffer *old_fb) 1000 { 1001 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1002 1003 /* TODO TV */ 1004 radeon_crtc_set_base(crtc, x, y, old_fb); 1005 radeon_set_crtc_timing(crtc, adjusted_mode); 1006 radeon_set_pll(crtc, adjusted_mode); 1007 radeon_overscan_setup(crtc, adjusted_mode); 1008 if (radeon_crtc->crtc_id == 0) { 1009 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1010 } else { 1011 if (radeon_crtc->rmx_type != RMX_OFF) { 1012 /* FIXME: only first crtc has rmx what should we 1013 * do ? 1014 */ 1015 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1016 } 1017 } 1018 return 0; 1019 } 1020 1021 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1022 { 1023 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1024 struct drm_device *dev = crtc->dev; 1025 struct drm_crtc *crtci; 1026 1027 radeon_crtc->in_mode_set = true; 1028 /* 1029 * The hardware wedges sometimes if you reconfigure one CRTC 1030 * whilst another is running (see fdo bug #24611). 1031 */ 1032 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1033 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1034 } 1035 1036 static void radeon_crtc_commit(struct drm_crtc *crtc) 1037 { 1038 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1039 struct drm_device *dev = crtc->dev; 1040 struct drm_crtc *crtci; 1041 1042 /* 1043 * Reenable the CRTCs that should be running. 1044 */ 1045 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1046 if (crtci->enabled) 1047 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1048 } 1049 radeon_crtc->in_mode_set = false; 1050 } 1051 1052 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1053 .dpms = radeon_crtc_dpms, 1054 .mode_fixup = radeon_crtc_mode_fixup, 1055 .mode_set = radeon_crtc_mode_set, 1056 .mode_set_base = radeon_crtc_set_base, 1057 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1058 .prepare = radeon_crtc_prepare, 1059 .commit = radeon_crtc_commit, 1060 .load_lut = radeon_crtc_load_lut, 1061 }; 1062 1063 1064 void radeon_legacy_init_crtc(struct drm_device *dev, 1065 struct radeon_crtc *radeon_crtc) 1066 { 1067 if (radeon_crtc->crtc_id == 1) 1068 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1069 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1070 } 1071