1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/radeon_drm.h> 29 #include <drm/drm_fixed.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 static void radeon_overscan_setup(struct drm_crtc *crtc, 34 struct drm_display_mode *mode) 35 { 36 struct drm_device *dev = crtc->dev; 37 struct radeon_device *rdev = dev->dev_private; 38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 39 40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); 41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); 42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); 43 } 44 45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, 46 struct drm_display_mode *mode) 47 { 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 int xres = mode->hdisplay; 52 int yres = mode->vdisplay; 53 bool hscale = true, vscale = true; 54 int hsync_wid; 55 int vsync_wid; 56 int hsync_start; 57 int blank_width; 58 u32 scale, inc, crtc_more_cntl; 59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; 63 64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 65 (RADEON_VERT_STRETCH_RESERVED | 66 RADEON_VERT_AUTO_RATIO_INC); 67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & 68 (RADEON_HORZ_FP_LOOP_STRETCH | 69 RADEON_HORZ_AUTO_RATIO_INC); 70 71 crtc_more_cntl = 0; 72 if ((rdev->family == CHIP_RS100) || 73 (rdev->family == CHIP_RS200)) { 74 /* This is to workaround the asic bug for RMX, some versions 75 of BIOS dosen't have this register initialized correctly. */ 76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; 77 } 78 79 80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 82 83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 84 if (!hsync_wid) 85 hsync_wid = 1; 86 hsync_start = mode->crtc_hsync_start - 8; 87 88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff) 89 | ((hsync_wid & 0x3f) << 16) 90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 91 ? RADEON_CRTC_H_SYNC_POL 92 : 0)); 93 94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 95 | ((mode->crtc_vdisplay - 1) << 16)); 96 97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 98 if (!vsync_wid) 99 vsync_wid = 1; 100 101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 102 | ((vsync_wid & 0x1f) << 16) 103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 104 ? RADEON_CRTC_V_SYNC_POL 105 : 0)); 106 107 fp_horz_vert_active = 0; 108 109 if (native_mode->hdisplay == 0 || 110 native_mode->vdisplay == 0) { 111 hscale = false; 112 vscale = false; 113 } else { 114 if (xres > native_mode->hdisplay) 115 xres = native_mode->hdisplay; 116 if (yres > native_mode->vdisplay) 117 yres = native_mode->vdisplay; 118 119 if (xres == native_mode->hdisplay) 120 hscale = false; 121 if (yres == native_mode->vdisplay) 122 vscale = false; 123 } 124 125 switch (radeon_crtc->rmx_type) { 126 case RMX_FULL: 127 case RMX_ASPECT: 128 if (!hscale) 129 fp_horz_stretch |= ((xres/8-1) << 16); 130 else { 131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 133 / native_mode->hdisplay + 1; 134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 135 RADEON_HORZ_STRETCH_BLEND | 136 RADEON_HORZ_STRETCH_ENABLE | 137 ((native_mode->hdisplay/8-1) << 16)); 138 } 139 140 if (!vscale) 141 fp_vert_stretch |= ((yres-1) << 12); 142 else { 143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 145 / native_mode->vdisplay + 1; 146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 147 RADEON_VERT_STRETCH_ENABLE | 148 RADEON_VERT_STRETCH_BLEND | 149 ((native_mode->vdisplay-1) << 12)); 150 } 151 break; 152 case RMX_CENTER: 153 fp_horz_stretch |= ((xres/8-1) << 16); 154 fp_vert_stretch |= ((yres-1) << 12); 155 156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | 157 RADEON_CRTC_AUTO_VERT_CENTER_EN); 158 159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; 160 if (blank_width > 110) 161 blank_width = 110; 162 163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff) 164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 165 166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 167 if (!hsync_wid) 168 hsync_wid = 1; 169 170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) 171 | ((hsync_wid & 0x3f) << 16) 172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 173 ? RADEON_CRTC_H_SYNC_POL 174 : 0)); 175 176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) 177 | ((mode->crtc_vdisplay - 1) << 16)); 178 179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 180 if (!vsync_wid) 181 vsync_wid = 1; 182 183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) 184 | ((vsync_wid & 0x1f) << 16) 185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 186 ? RADEON_CRTC_V_SYNC_POL 187 : 0))); 188 189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | 190 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); 191 break; 192 case RMX_OFF: 193 default: 194 fp_horz_stretch |= ((xres/8-1) << 16); 195 fp_vert_stretch |= ((yres-1) << 12); 196 break; 197 } 198 199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); 200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); 201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); 202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); 203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); 204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); 205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); 206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); 207 } 208 209 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) 210 { 211 struct radeon_device *rdev = dev->dev_private; 212 int i = 0; 213 214 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 215 the cause yet, but this workaround will mask the problem for now. 216 Other chips usually will pass at the very first test, so the 217 workaround shouldn't have any effect on them. */ 218 for (i = 0; 219 (i < 10000 && 220 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 221 i++); 222 } 223 224 static void radeon_pll_write_update(struct drm_device *dev) 225 { 226 struct radeon_device *rdev = dev->dev_private; 227 228 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 229 230 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 231 RADEON_PPLL_ATOMIC_UPDATE_W, 232 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 233 } 234 235 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) 236 { 237 struct radeon_device *rdev = dev->dev_private; 238 int i = 0; 239 240 241 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 242 the cause yet, but this workaround will mask the problem for now. 243 Other chips usually will pass at the very first test, so the 244 workaround shouldn't have any effect on them. */ 245 for (i = 0; 246 (i < 10000 && 247 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 248 i++); 249 } 250 251 static void radeon_pll2_write_update(struct drm_device *dev) 252 { 253 struct radeon_device *rdev = dev->dev_private; 254 255 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 256 257 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 258 RADEON_P2PLL_ATOMIC_UPDATE_W, 259 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 260 } 261 262 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, 263 uint16_t fb_div) 264 { 265 unsigned int vcoFreq; 266 267 if (!ref_div) 268 return 1; 269 270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; 271 272 /* 273 * This is horribly crude: the VCO frequency range is divided into 274 * 3 parts, each part having a fixed PLL gain value. 275 */ 276 if (vcoFreq >= 30000) 277 /* 278 * [300..max] MHz : 7 279 */ 280 return 7; 281 else if (vcoFreq >= 18000) 282 /* 283 * [180..300) MHz : 4 284 */ 285 return 4; 286 else 287 /* 288 * [0..180) MHz : 1 289 */ 290 return 1; 291 } 292 293 static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) 294 { 295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 296 struct drm_device *dev = crtc->dev; 297 struct radeon_device *rdev = dev->dev_private; 298 uint32_t crtc_ext_cntl = 0; 299 uint32_t mask; 300 301 if (radeon_crtc->crtc_id) 302 mask = (RADEON_CRTC2_DISP_DIS | 303 RADEON_CRTC2_VSYNC_DIS | 304 RADEON_CRTC2_HSYNC_DIS | 305 RADEON_CRTC2_DISP_REQ_EN_B); 306 else 307 mask = (RADEON_CRTC_DISPLAY_DIS | 308 RADEON_CRTC_VSYNC_DIS | 309 RADEON_CRTC_HSYNC_DIS); 310 311 /* 312 * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC. 313 * Therefore it is set in the DAC DMPS function. 314 * This is different for GPU's with a single CRTC but a primary and a 315 * TV DAC: here it controls the single CRTC no matter where it is 316 * routed. Therefore we set it here. 317 */ 318 if (rdev->flags & RADEON_SINGLE_CRTC) 319 crtc_ext_cntl = RADEON_CRTC_CRT_ON; 320 321 switch (mode) { 322 case DRM_MODE_DPMS_ON: 323 radeon_crtc->enabled = true; 324 /* adjust pm to dpms changes BEFORE enabling crtcs */ 325 radeon_pm_compute_clocks(rdev); 326 if (radeon_crtc->crtc_id) 327 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); 328 else { 329 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | 330 RADEON_CRTC_DISP_REQ_EN_B)); 331 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 332 } 333 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 334 radeon_crtc_load_lut(crtc); 335 break; 336 case DRM_MODE_DPMS_STANDBY: 337 case DRM_MODE_DPMS_SUSPEND: 338 case DRM_MODE_DPMS_OFF: 339 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 340 if (radeon_crtc->crtc_id) 341 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 342 else { 343 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | 344 RADEON_CRTC_DISP_REQ_EN_B)); 345 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); 346 } 347 radeon_crtc->enabled = false; 348 /* adjust pm to dpms changes AFTER disabling crtcs */ 349 radeon_pm_compute_clocks(rdev); 350 break; 351 } 352 } 353 354 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 355 struct drm_framebuffer *old_fb) 356 { 357 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 358 } 359 360 int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 361 struct drm_framebuffer *fb, 362 int x, int y, enum mode_set_atomic state) 363 { 364 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 365 } 366 367 int radeon_crtc_do_set_base(struct drm_crtc *crtc, 368 struct drm_framebuffer *fb, 369 int x, int y, int atomic) 370 { 371 struct drm_device *dev = crtc->dev; 372 struct radeon_device *rdev = dev->dev_private; 373 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 374 struct radeon_framebuffer *radeon_fb; 375 struct drm_framebuffer *target_fb; 376 struct drm_gem_object *obj; 377 struct radeon_bo *rbo; 378 uint64_t base; 379 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; 380 uint32_t crtc_pitch, pitch_pixels; 381 uint32_t tiling_flags; 382 int format; 383 uint32_t gen_cntl_reg, gen_cntl_val; 384 int r; 385 386 DRM_DEBUG_KMS("\n"); 387 /* no fb bound */ 388 if (!atomic && !crtc->fb) { 389 DRM_DEBUG_KMS("No FB bound\n"); 390 return 0; 391 } 392 393 if (atomic) { 394 radeon_fb = to_radeon_framebuffer(fb); 395 target_fb = fb; 396 } 397 else { 398 radeon_fb = to_radeon_framebuffer(crtc->fb); 399 target_fb = crtc->fb; 400 } 401 402 switch (target_fb->bits_per_pixel) { 403 case 8: 404 format = 2; 405 break; 406 case 15: /* 555 */ 407 format = 3; 408 break; 409 case 16: /* 565 */ 410 format = 4; 411 break; 412 case 24: /* RGB */ 413 format = 5; 414 break; 415 case 32: /* xRGB */ 416 format = 6; 417 break; 418 default: 419 return false; 420 } 421 422 /* Pin framebuffer & get tilling informations */ 423 obj = radeon_fb->obj; 424 rbo = gem_to_radeon_bo(obj); 425 retry: 426 r = radeon_bo_reserve(rbo, false); 427 if (unlikely(r != 0)) 428 return r; 429 /* Only 27 bit offset for legacy CRTC */ 430 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, 431 &base); 432 if (unlikely(r != 0)) { 433 radeon_bo_unreserve(rbo); 434 435 /* On old GPU like RN50 with little vram pining can fails because 436 * current fb is taking all space needed. So instead of unpining 437 * the old buffer after pining the new one, first unpin old one 438 * and then retry pining new one. 439 * 440 * As only master can set mode only master can pin and it is 441 * unlikely the master client will race with itself especialy 442 * on those old gpu with single crtc. 443 * 444 * We don't shutdown the display controller because new buffer 445 * will end up in same spot. 446 */ 447 if (!atomic && fb && fb != crtc->fb) { 448 struct radeon_bo *old_rbo; 449 unsigned long nsize, osize; 450 451 old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj); 452 osize = radeon_bo_size(old_rbo); 453 nsize = radeon_bo_size(rbo); 454 if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) { 455 radeon_bo_unpin(old_rbo); 456 radeon_bo_unreserve(old_rbo); 457 fb = NULL; 458 goto retry; 459 } 460 } 461 return -EINVAL; 462 } 463 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 464 radeon_bo_unreserve(rbo); 465 if (tiling_flags & RADEON_TILING_MICRO) 466 DRM_ERROR("trying to scanout microtiled buffer\n"); 467 468 /* if scanout was in GTT this really wouldn't work */ 469 /* crtc offset is from display base addr not FB location */ 470 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; 471 472 base -= radeon_crtc->legacy_display_base_addr; 473 474 crtc_offset_cntl = 0; 475 476 pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 477 crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + 478 ((target_fb->bits_per_pixel * 8) - 1)) / 479 (target_fb->bits_per_pixel * 8)); 480 crtc_pitch |= crtc_pitch << 16; 481 482 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; 483 if (tiling_flags & RADEON_TILING_MACRO) { 484 if (ASIC_IS_R300(rdev)) 485 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 486 R300_CRTC_MICRO_TILE_BUFFER_DIS | 487 R300_CRTC_MACRO_TILE_EN); 488 else 489 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 490 } else { 491 if (ASIC_IS_R300(rdev)) 492 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 493 R300_CRTC_MICRO_TILE_BUFFER_DIS | 494 R300_CRTC_MACRO_TILE_EN); 495 else 496 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 497 } 498 499 if (tiling_flags & RADEON_TILING_MACRO) { 500 if (ASIC_IS_R300(rdev)) { 501 crtc_tile_x0_y0 = x | (y << 16); 502 base &= ~0x7ff; 503 } else { 504 int byteshift = target_fb->bits_per_pixel >> 4; 505 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; 506 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 507 crtc_offset_cntl |= (y % 16); 508 } 509 } else { 510 int offset = y * pitch_pixels + x; 511 switch (target_fb->bits_per_pixel) { 512 case 8: 513 offset *= 1; 514 break; 515 case 15: 516 case 16: 517 offset *= 2; 518 break; 519 case 24: 520 offset *= 3; 521 break; 522 case 32: 523 offset *= 4; 524 break; 525 default: 526 return false; 527 } 528 base += offset; 529 } 530 531 base &= ~7; 532 533 if (radeon_crtc->crtc_id == 1) 534 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; 535 else 536 gen_cntl_reg = RADEON_CRTC_GEN_CNTL; 537 538 gen_cntl_val = RREG32(gen_cntl_reg); 539 gen_cntl_val &= ~(0xf << 8); 540 gen_cntl_val |= (format << 8); 541 gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; 542 WREG32(gen_cntl_reg, gen_cntl_val); 543 544 crtc_offset = (u32)base; 545 546 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); 547 548 if (ASIC_IS_R300(rdev)) { 549 if (radeon_crtc->crtc_id) 550 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); 551 else 552 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); 553 } 554 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); 555 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); 556 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); 557 558 if (!atomic && fb && fb != crtc->fb) { 559 radeon_fb = to_radeon_framebuffer(fb); 560 rbo = gem_to_radeon_bo(radeon_fb->obj); 561 r = radeon_bo_reserve(rbo, false); 562 if (unlikely(r != 0)) 563 return r; 564 radeon_bo_unpin(rbo); 565 radeon_bo_unreserve(rbo); 566 } 567 568 /* Bytes per pixel may have changed */ 569 radeon_bandwidth_update(rdev); 570 571 return 0; 572 } 573 574 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) 575 { 576 struct drm_device *dev = crtc->dev; 577 struct radeon_device *rdev = dev->dev_private; 578 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 579 struct drm_encoder *encoder; 580 int format; 581 int hsync_start; 582 int hsync_wid; 583 int vsync_wid; 584 uint32_t crtc_h_total_disp; 585 uint32_t crtc_h_sync_strt_wid; 586 uint32_t crtc_v_total_disp; 587 uint32_t crtc_v_sync_strt_wid; 588 bool is_tv = false; 589 590 DRM_DEBUG_KMS("\n"); 591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 592 if (encoder->crtc == crtc) { 593 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 594 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 595 is_tv = true; 596 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); 597 break; 598 } 599 } 600 } 601 602 switch (crtc->fb->bits_per_pixel) { 603 case 8: 604 format = 2; 605 break; 606 case 15: /* 555 */ 607 format = 3; 608 break; 609 case 16: /* 565 */ 610 format = 4; 611 break; 612 case 24: /* RGB */ 613 format = 5; 614 break; 615 case 32: /* xRGB */ 616 format = 6; 617 break; 618 default: 619 return false; 620 } 621 622 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) 623 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); 624 625 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; 626 if (!hsync_wid) 627 hsync_wid = 1; 628 hsync_start = mode->crtc_hsync_start - 8; 629 630 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 631 | ((hsync_wid & 0x3f) << 16) 632 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) 633 ? RADEON_CRTC_H_SYNC_POL 634 : 0)); 635 636 /* This works for double scan mode. */ 637 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) 638 | ((mode->crtc_vdisplay - 1) << 16)); 639 640 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; 641 if (!vsync_wid) 642 vsync_wid = 1; 643 644 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) 645 | ((vsync_wid & 0x1f) << 16) 646 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) 647 ? RADEON_CRTC_V_SYNC_POL 648 : 0)); 649 650 if (radeon_crtc->crtc_id) { 651 uint32_t crtc2_gen_cntl; 652 uint32_t disp2_merge_cntl; 653 654 /* if TV DAC is enabled for another crtc and keep it enabled */ 655 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; 656 crtc2_gen_cntl |= ((format << 8) 657 | RADEON_CRTC2_VSYNC_DIS 658 | RADEON_CRTC2_HSYNC_DIS 659 | RADEON_CRTC2_DISP_DIS 660 | RADEON_CRTC2_DISP_REQ_EN_B 661 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 662 ? RADEON_CRTC2_DBL_SCAN_EN 663 : 0) 664 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 665 ? RADEON_CRTC2_CSYNC_EN 666 : 0) 667 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 668 ? RADEON_CRTC2_INTERLACE_EN 669 : 0)); 670 671 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 672 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 673 crtc2_gen_cntl |= RADEON_CRTC2_EN; 674 675 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 676 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 677 678 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 679 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 680 681 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); 682 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); 683 } else { 684 uint32_t crtc_gen_cntl; 685 uint32_t crtc_ext_cntl; 686 uint32_t disp_merge_cntl; 687 688 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; 689 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN 690 | (format << 8) 691 | RADEON_CRTC_DISP_REQ_EN_B 692 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) 693 ? RADEON_CRTC_DBL_SCAN_EN 694 : 0) 695 | ((mode->flags & DRM_MODE_FLAG_CSYNC) 696 ? RADEON_CRTC_CSYNC_EN 697 : 0) 698 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) 699 ? RADEON_CRTC_INTERLACE_EN 700 : 0)); 701 702 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ 703 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) 704 crtc_gen_cntl |= RADEON_CRTC_EN; 705 706 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 707 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | 708 RADEON_CRTC_VSYNC_DIS | 709 RADEON_CRTC_HSYNC_DIS | 710 RADEON_CRTC_DISPLAY_DIS); 711 712 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 713 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 714 715 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 716 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 717 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 718 } 719 720 if (is_tv) 721 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, 722 &crtc_h_sync_strt_wid, &crtc_v_total_disp, 723 &crtc_v_sync_strt_wid); 724 725 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); 726 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); 727 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); 728 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); 729 730 return true; 731 } 732 733 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 734 { 735 struct drm_device *dev = crtc->dev; 736 struct radeon_device *rdev = dev->dev_private; 737 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 738 struct drm_encoder *encoder; 739 uint32_t feedback_div = 0; 740 uint32_t frac_fb_div = 0; 741 uint32_t reference_div = 0; 742 uint32_t post_divider = 0; 743 uint32_t freq = 0; 744 uint8_t pll_gain; 745 bool use_bios_divs = false; 746 /* PLL registers */ 747 uint32_t pll_ref_div = 0; 748 uint32_t pll_fb_post_div = 0; 749 uint32_t htotal_cntl = 0; 750 bool is_tv = false; 751 struct radeon_pll *pll; 752 753 struct { 754 int divider; 755 int bitvalue; 756 } *post_div, post_divs[] = { 757 /* From RAGE 128 VR/RAGE 128 GL Register 758 * Reference Manual (Technical Reference 759 * Manual P/N RRG-G04100-C Rev. 0.04), page 760 * 3-17 (PLL_DIV_[3:0]). 761 */ 762 { 1, 0 }, /* VCLK_SRC */ 763 { 2, 1 }, /* VCLK_SRC/2 */ 764 { 4, 2 }, /* VCLK_SRC/4 */ 765 { 8, 3 }, /* VCLK_SRC/8 */ 766 { 3, 4 }, /* VCLK_SRC/3 */ 767 { 16, 5 }, /* VCLK_SRC/16 */ 768 { 6, 6 }, /* VCLK_SRC/6 */ 769 { 12, 7 }, /* VCLK_SRC/12 */ 770 { 0, 0 } 771 }; 772 773 if (radeon_crtc->crtc_id) 774 pll = &rdev->clock.p2pll; 775 else 776 pll = &rdev->clock.p1pll; 777 778 pll->flags = RADEON_PLL_LEGACY; 779 780 if (mode->clock > 200000) /* range limits??? */ 781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 782 else 783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 784 785 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 786 if (encoder->crtc == crtc) { 787 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 788 789 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 790 is_tv = true; 791 break; 792 } 793 794 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 796 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 797 if (!rdev->is_atom_bios) { 798 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 800 if (lvds) { 801 if (lvds->use_bios_dividers) { 802 pll_ref_div = lvds->panel_ref_divider; 803 pll_fb_post_div = (lvds->panel_fb_divider | 804 (lvds->panel_post_divider << 16)); 805 htotal_cntl = 0; 806 use_bios_divs = true; 807 } 808 } 809 } 810 pll->flags |= RADEON_PLL_USE_REF_DIV; 811 } 812 } 813 } 814 815 DRM_DEBUG_KMS("\n"); 816 817 if (!use_bios_divs) { 818 radeon_compute_pll_legacy(pll, mode->clock, 819 &freq, &feedback_div, &frac_fb_div, 820 &reference_div, &post_divider); 821 822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 823 if (post_div->divider == post_divider) 824 break; 825 } 826 827 if (!post_div->divider) 828 post_div = &post_divs[0]; 829 830 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", 831 (unsigned)freq, 832 feedback_div, 833 reference_div, 834 post_divider); 835 836 pll_ref_div = reference_div; 837 #if defined(__powerpc__) && (0) /* TODO */ 838 /* apparently programming this otherwise causes a hang??? */ 839 if (info->MacModel == RADEON_MAC_IBOOK) 840 pll_fb_post_div = 0x000600ad; 841 else 842 #endif 843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); 844 845 htotal_cntl = mode->htotal & 0x7; 846 847 } 848 849 pll_gain = radeon_compute_pll_gain(pll->reference_freq, 850 pll_ref_div & 0x3ff, 851 pll_fb_post_div & 0x7ff); 852 853 if (radeon_crtc->crtc_id) { 854 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & 855 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 856 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 857 858 if (is_tv) { 859 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, 860 &pll_ref_div, &pll_fb_post_div, 861 &pixclks_cntl); 862 } 863 864 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 865 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 866 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 867 868 WREG32_PLL_P(RADEON_P2PLL_CNTL, 869 RADEON_P2PLL_RESET 870 | RADEON_P2PLL_ATOMIC_UPDATE_EN 871 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), 872 ~(RADEON_P2PLL_RESET 873 | RADEON_P2PLL_ATOMIC_UPDATE_EN 874 | RADEON_P2PLL_PVG_MASK)); 875 876 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, 877 pll_ref_div, 878 ~RADEON_P2PLL_REF_DIV_MASK); 879 880 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 881 pll_fb_post_div, 882 ~RADEON_P2PLL_FB0_DIV_MASK); 883 884 WREG32_PLL_P(RADEON_P2PLL_DIV_0, 885 pll_fb_post_div, 886 ~RADEON_P2PLL_POST0_DIV_MASK); 887 888 radeon_pll2_write_update(dev); 889 radeon_pll2_wait_for_read_update_complete(dev); 890 891 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); 892 893 WREG32_PLL_P(RADEON_P2PLL_CNTL, 894 0, 895 ~(RADEON_P2PLL_RESET 896 | RADEON_P2PLL_SLEEP 897 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 898 899 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 900 (unsigned)pll_ref_div, 901 (unsigned)pll_fb_post_div, 902 (unsigned)htotal_cntl, 903 RREG32_PLL(RADEON_P2PLL_CNTL)); 904 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", 905 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 906 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, 907 (unsigned)((pll_fb_post_div & 908 RADEON_P2PLL_POST0_DIV_MASK) >> 16)); 909 910 mdelay(50); /* Let the clock to lock */ 911 912 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 913 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 914 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 915 916 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 917 } else { 918 uint32_t pixclks_cntl; 919 920 921 if (is_tv) { 922 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 923 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, 924 &pll_fb_post_div, &pixclks_cntl); 925 } 926 927 if (rdev->flags & RADEON_IS_MOBILITY) { 928 /* A temporal workaround for the occasional blanking on certain laptop panels. 929 This appears to related to the PLL divider registers (fail to lock?). 930 It occurs even when all dividers are the same with their old settings. 931 In this case we really don't need to fiddle with PLL registers. 932 By doing this we can avoid the blanking problem with some panels. 933 */ 934 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 935 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & 936 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 938 RADEON_PLL_DIV_SEL, 939 ~(RADEON_PLL_DIV_SEL)); 940 r100_pll_errata_after_index(rdev); 941 return; 942 } 943 } 944 945 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 946 RADEON_VCLK_SRC_SEL_CPUCLK, 947 ~(RADEON_VCLK_SRC_SEL_MASK)); 948 WREG32_PLL_P(RADEON_PPLL_CNTL, 949 RADEON_PPLL_RESET 950 | RADEON_PPLL_ATOMIC_UPDATE_EN 951 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 952 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), 953 ~(RADEON_PPLL_RESET 954 | RADEON_PPLL_ATOMIC_UPDATE_EN 955 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 956 | RADEON_PPLL_PVG_MASK)); 957 958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, 959 RADEON_PLL_DIV_SEL, 960 ~(RADEON_PLL_DIV_SEL)); 961 r100_pll_errata_after_index(rdev); 962 963 if (ASIC_IS_R300(rdev) || 964 (rdev->family == CHIP_RS300) || 965 (rdev->family == CHIP_RS400) || 966 (rdev->family == CHIP_RS480)) { 967 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 968 /* When restoring console mode, use saved PPLL_REF_DIV 969 * setting. 970 */ 971 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 972 pll_ref_div, 973 0); 974 } else { 975 /* R300 uses ref_div_acc field as real ref divider */ 976 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 977 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 978 ~R300_PPLL_REF_DIV_ACC_MASK); 979 } 980 } else 981 WREG32_PLL_P(RADEON_PPLL_REF_DIV, 982 pll_ref_div, 983 ~RADEON_PPLL_REF_DIV_MASK); 984 985 WREG32_PLL_P(RADEON_PPLL_DIV_3, 986 pll_fb_post_div, 987 ~RADEON_PPLL_FB3_DIV_MASK); 988 989 WREG32_PLL_P(RADEON_PPLL_DIV_3, 990 pll_fb_post_div, 991 ~RADEON_PPLL_POST3_DIV_MASK); 992 993 radeon_pll_write_update(dev); 994 radeon_pll_wait_for_read_update_complete(dev); 995 996 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); 997 998 WREG32_PLL_P(RADEON_PPLL_CNTL, 999 0, 1000 ~(RADEON_PPLL_RESET 1001 | RADEON_PPLL_SLEEP 1002 | RADEON_PPLL_ATOMIC_UPDATE_EN 1003 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 1004 1005 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 1006 pll_ref_div, 1007 pll_fb_post_div, 1008 (unsigned)htotal_cntl, 1009 RREG32_PLL(RADEON_PPLL_CNTL)); 1010 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", 1011 pll_ref_div & RADEON_PPLL_REF_DIV_MASK, 1012 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, 1013 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); 1014 1015 mdelay(50); /* Let the clock to lock */ 1016 1017 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, 1018 RADEON_VCLK_SRC_SEL_PPLLCLK, 1019 ~(RADEON_VCLK_SRC_SEL_MASK)); 1020 1021 if (is_tv) 1022 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1023 } 1024 } 1025 1026 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, 1027 const struct drm_display_mode *mode, 1028 struct drm_display_mode *adjusted_mode) 1029 { 1030 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1031 return false; 1032 return true; 1033 } 1034 1035 static int radeon_crtc_mode_set(struct drm_crtc *crtc, 1036 struct drm_display_mode *mode, 1037 struct drm_display_mode *adjusted_mode, 1038 int x, int y, struct drm_framebuffer *old_fb) 1039 { 1040 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1041 1042 /* TODO TV */ 1043 radeon_crtc_set_base(crtc, x, y, old_fb); 1044 radeon_set_crtc_timing(crtc, adjusted_mode); 1045 radeon_set_pll(crtc, adjusted_mode); 1046 radeon_overscan_setup(crtc, adjusted_mode); 1047 if (radeon_crtc->crtc_id == 0) { 1048 radeon_legacy_rmx_mode_set(crtc, adjusted_mode); 1049 } else { 1050 if (radeon_crtc->rmx_type != RMX_OFF) { 1051 /* FIXME: only first crtc has rmx what should we 1052 * do ? 1053 */ 1054 DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); 1055 } 1056 } 1057 return 0; 1058 } 1059 1060 static void radeon_crtc_prepare(struct drm_crtc *crtc) 1061 { 1062 struct drm_device *dev = crtc->dev; 1063 struct drm_crtc *crtci; 1064 1065 /* 1066 * The hardware wedges sometimes if you reconfigure one CRTC 1067 * whilst another is running (see fdo bug #24611). 1068 */ 1069 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) 1070 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); 1071 } 1072 1073 static void radeon_crtc_commit(struct drm_crtc *crtc) 1074 { 1075 struct drm_device *dev = crtc->dev; 1076 struct drm_crtc *crtci; 1077 1078 /* 1079 * Reenable the CRTCs that should be running. 1080 */ 1081 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { 1082 if (crtci->enabled) 1083 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1084 } 1085 } 1086 1087 static void radeon_crtc_disable(struct drm_crtc *crtc) 1088 { 1089 radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1090 if (crtc->fb) { 1091 int r; 1092 struct radeon_framebuffer *radeon_fb; 1093 struct radeon_bo *rbo; 1094 1095 radeon_fb = to_radeon_framebuffer(crtc->fb); 1096 rbo = gem_to_radeon_bo(radeon_fb->obj); 1097 r = radeon_bo_reserve(rbo, false); 1098 if (unlikely(r)) 1099 DRM_ERROR("failed to reserve rbo before unpin\n"); 1100 else { 1101 radeon_bo_unpin(rbo); 1102 radeon_bo_unreserve(rbo); 1103 } 1104 } 1105 } 1106 1107 static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1108 .dpms = radeon_crtc_dpms, 1109 .mode_fixup = radeon_crtc_mode_fixup, 1110 .mode_set = radeon_crtc_mode_set, 1111 .mode_set_base = radeon_crtc_set_base, 1112 .mode_set_base_atomic = radeon_crtc_set_base_atomic, 1113 .prepare = radeon_crtc_prepare, 1114 .commit = radeon_crtc_commit, 1115 .load_lut = radeon_crtc_load_lut, 1116 .disable = radeon_crtc_disable 1117 }; 1118 1119 1120 void radeon_legacy_init_crtc(struct drm_device *dev, 1121 struct radeon_crtc *radeon_crtc) 1122 { 1123 if (radeon_crtc->crtc_id == 1) 1124 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; 1125 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); 1126 } 1127