1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon.h" 30 #include <drm/radeon_drm.h> 31 #include "radeon_asic.h" 32 33 #include <linux/vga_switcheroo.h> 34 #include <linux/slab.h> 35 #include <linux/pm_runtime.h> 36 37 #include "radeon_kfd.h" 38 39 #if defined(CONFIG_VGA_SWITCHEROO) 40 bool radeon_has_atpx(void); 41 #else 42 static inline bool radeon_has_atpx(void) { return false; } 43 #endif 44 45 /** 46 * radeon_driver_unload_kms - Main unload function for KMS. 47 * 48 * @dev: drm dev pointer 49 * 50 * This is the main unload function for KMS (all asics). 51 * It calls radeon_modeset_fini() to tear down the 52 * displays, and radeon_device_fini() to tear down 53 * the rest of the device (CP, writeback, etc.). 54 * Returns 0 on success. 55 */ 56 void radeon_driver_unload_kms(struct drm_device *dev) 57 { 58 struct radeon_device *rdev = dev->dev_private; 59 60 if (rdev == NULL) 61 return; 62 63 if (rdev->rmmio == NULL) 64 goto done_free; 65 66 if (radeon_is_px(dev)) { 67 pm_runtime_get_sync(dev->dev); 68 pm_runtime_forbid(dev->dev); 69 } 70 71 radeon_kfd_device_fini(rdev); 72 73 radeon_acpi_fini(rdev); 74 75 radeon_modeset_fini(rdev); 76 radeon_device_fini(rdev); 77 78 done_free: 79 kfree(rdev); 80 dev->dev_private = NULL; 81 } 82 83 /** 84 * radeon_driver_load_kms - Main load function for KMS. 85 * 86 * @dev: drm dev pointer 87 * @flags: device flags 88 * 89 * This is the main load function for KMS (all asics). 90 * It calls radeon_device_init() to set up the non-display 91 * parts of the chip (asic init, CP, writeback, etc.), and 92 * radeon_modeset_init() to set up the display parts 93 * (crtcs, encoders, hotplug detect, etc.). 94 * Returns 0 on success, error on failure. 95 */ 96 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 97 { 98 struct radeon_device *rdev; 99 int r, acpi_status; 100 101 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 102 if (rdev == NULL) { 103 return -ENOMEM; 104 } 105 dev->dev_private = (void *)rdev; 106 107 /* update BUS flag */ 108 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) { 109 flags |= RADEON_IS_AGP; 110 } else if (pci_is_pcie(dev->pdev)) { 111 flags |= RADEON_IS_PCIE; 112 } else { 113 flags |= RADEON_IS_PCI; 114 } 115 116 if ((radeon_runtime_pm != 0) && 117 radeon_has_atpx() && 118 ((flags & RADEON_IS_IGP) == 0) && 119 !pci_is_thunderbolt_attached(dev->pdev)) 120 flags |= RADEON_IS_PX; 121 122 /* radeon_device_init should report only fatal error 123 * like memory allocation failure or iomapping failure, 124 * or memory manager initialization failure, it must 125 * properly initialize the GPU MC controller and permit 126 * VRAM allocation 127 */ 128 r = radeon_device_init(rdev, dev, dev->pdev, flags); 129 if (r) { 130 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 131 goto out; 132 } 133 134 /* Again modeset_init should fail only on fatal error 135 * otherwise it should provide enough functionalities 136 * for shadowfb to run 137 */ 138 r = radeon_modeset_init(rdev); 139 if (r) 140 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 141 142 /* Call ACPI methods: require modeset init 143 * but failure is not fatal 144 */ 145 if (!r) { 146 acpi_status = radeon_acpi_init(rdev); 147 if (acpi_status) 148 dev_dbg(&dev->pdev->dev, 149 "Error during ACPI methods call\n"); 150 } 151 152 radeon_kfd_device_probe(rdev); 153 radeon_kfd_device_init(rdev); 154 155 if (radeon_is_px(dev)) { 156 pm_runtime_use_autosuspend(dev->dev); 157 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 158 pm_runtime_set_active(dev->dev); 159 pm_runtime_allow(dev->dev); 160 pm_runtime_mark_last_busy(dev->dev); 161 pm_runtime_put_autosuspend(dev->dev); 162 } 163 164 out: 165 if (r) 166 radeon_driver_unload_kms(dev); 167 168 169 return r; 170 } 171 172 /** 173 * radeon_set_filp_rights - Set filp right. 174 * 175 * @dev: drm dev pointer 176 * @owner: drm file 177 * @applier: drm file 178 * @value: value 179 * 180 * Sets the filp rights for the device (all asics). 181 */ 182 static void radeon_set_filp_rights(struct drm_device *dev, 183 struct drm_file **owner, 184 struct drm_file *applier, 185 uint32_t *value) 186 { 187 struct radeon_device *rdev = dev->dev_private; 188 189 mutex_lock(&rdev->gem.mutex); 190 if (*value == 1) { 191 /* wants rights */ 192 if (!*owner) 193 *owner = applier; 194 } else if (*value == 0) { 195 /* revokes rights */ 196 if (*owner == applier) 197 *owner = NULL; 198 } 199 *value = *owner == applier ? 1 : 0; 200 mutex_unlock(&rdev->gem.mutex); 201 } 202 203 /* 204 * Userspace get information ioctl 205 */ 206 /** 207 * radeon_info_ioctl - answer a device specific request. 208 * 209 * @rdev: radeon device pointer 210 * @data: request object 211 * @filp: drm filp 212 * 213 * This function is used to pass device specific parameters to the userspace 214 * drivers. Examples include: pci device id, pipeline parms, tiling params, 215 * etc. (all asics). 216 * Returns 0 on success, -EINVAL on failure. 217 */ 218 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 219 { 220 struct radeon_device *rdev = dev->dev_private; 221 struct drm_radeon_info *info = data; 222 struct radeon_mode_info *minfo = &rdev->mode_info; 223 uint32_t *value, value_tmp, *value_ptr, value_size; 224 uint64_t value64; 225 struct drm_crtc *crtc; 226 int i, found; 227 228 value_ptr = (uint32_t *)((unsigned long)info->value); 229 value = &value_tmp; 230 value_size = sizeof(uint32_t); 231 232 switch (info->request) { 233 case RADEON_INFO_DEVICE_ID: 234 *value = dev->pdev->device; 235 break; 236 case RADEON_INFO_NUM_GB_PIPES: 237 *value = rdev->num_gb_pipes; 238 break; 239 case RADEON_INFO_NUM_Z_PIPES: 240 *value = rdev->num_z_pipes; 241 break; 242 case RADEON_INFO_ACCEL_WORKING: 243 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 244 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 245 *value = false; 246 else 247 *value = rdev->accel_working; 248 break; 249 case RADEON_INFO_CRTC_FROM_ID: 250 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 251 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 252 return -EFAULT; 253 } 254 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 255 crtc = (struct drm_crtc *)minfo->crtcs[i]; 256 if (crtc && crtc->base.id == *value) { 257 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 258 *value = radeon_crtc->crtc_id; 259 found = 1; 260 break; 261 } 262 } 263 if (!found) { 264 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 265 return -EINVAL; 266 } 267 break; 268 case RADEON_INFO_ACCEL_WORKING2: 269 if (rdev->family == CHIP_HAWAII) { 270 if (rdev->accel_working) { 271 if (rdev->new_fw) 272 *value = 3; 273 else 274 *value = 2; 275 } else { 276 *value = 0; 277 } 278 } else { 279 *value = rdev->accel_working; 280 } 281 break; 282 case RADEON_INFO_TILING_CONFIG: 283 if (rdev->family >= CHIP_BONAIRE) 284 *value = rdev->config.cik.tile_config; 285 else if (rdev->family >= CHIP_TAHITI) 286 *value = rdev->config.si.tile_config; 287 else if (rdev->family >= CHIP_CAYMAN) 288 *value = rdev->config.cayman.tile_config; 289 else if (rdev->family >= CHIP_CEDAR) 290 *value = rdev->config.evergreen.tile_config; 291 else if (rdev->family >= CHIP_RV770) 292 *value = rdev->config.rv770.tile_config; 293 else if (rdev->family >= CHIP_R600) 294 *value = rdev->config.r600.tile_config; 295 else { 296 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 297 return -EINVAL; 298 } 299 break; 300 case RADEON_INFO_WANT_HYPERZ: 301 /* The "value" here is both an input and output parameter. 302 * If the input value is 1, filp requests hyper-z access. 303 * If the input value is 0, filp revokes its hyper-z access. 304 * 305 * When returning, the value is 1 if filp owns hyper-z access, 306 * 0 otherwise. */ 307 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 308 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 309 return -EFAULT; 310 } 311 if (*value >= 2) { 312 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 313 return -EINVAL; 314 } 315 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 316 break; 317 case RADEON_INFO_WANT_CMASK: 318 /* The same logic as Hyper-Z. */ 319 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 320 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 321 return -EFAULT; 322 } 323 if (*value >= 2) { 324 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 325 return -EINVAL; 326 } 327 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 328 break; 329 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 330 /* return clock value in KHz */ 331 if (rdev->asic->get_xclk) 332 *value = radeon_get_xclk(rdev) * 10; 333 else 334 *value = rdev->clock.spll.reference_freq * 10; 335 break; 336 case RADEON_INFO_NUM_BACKENDS: 337 if (rdev->family >= CHIP_BONAIRE) 338 *value = rdev->config.cik.max_backends_per_se * 339 rdev->config.cik.max_shader_engines; 340 else if (rdev->family >= CHIP_TAHITI) 341 *value = rdev->config.si.max_backends_per_se * 342 rdev->config.si.max_shader_engines; 343 else if (rdev->family >= CHIP_CAYMAN) 344 *value = rdev->config.cayman.max_backends_per_se * 345 rdev->config.cayman.max_shader_engines; 346 else if (rdev->family >= CHIP_CEDAR) 347 *value = rdev->config.evergreen.max_backends; 348 else if (rdev->family >= CHIP_RV770) 349 *value = rdev->config.rv770.max_backends; 350 else if (rdev->family >= CHIP_R600) 351 *value = rdev->config.r600.max_backends; 352 else { 353 return -EINVAL; 354 } 355 break; 356 case RADEON_INFO_NUM_TILE_PIPES: 357 if (rdev->family >= CHIP_BONAIRE) 358 *value = rdev->config.cik.max_tile_pipes; 359 else if (rdev->family >= CHIP_TAHITI) 360 *value = rdev->config.si.max_tile_pipes; 361 else if (rdev->family >= CHIP_CAYMAN) 362 *value = rdev->config.cayman.max_tile_pipes; 363 else if (rdev->family >= CHIP_CEDAR) 364 *value = rdev->config.evergreen.max_tile_pipes; 365 else if (rdev->family >= CHIP_RV770) 366 *value = rdev->config.rv770.max_tile_pipes; 367 else if (rdev->family >= CHIP_R600) 368 *value = rdev->config.r600.max_tile_pipes; 369 else { 370 return -EINVAL; 371 } 372 break; 373 case RADEON_INFO_FUSION_GART_WORKING: 374 *value = 1; 375 break; 376 case RADEON_INFO_BACKEND_MAP: 377 if (rdev->family >= CHIP_BONAIRE) 378 *value = rdev->config.cik.backend_map; 379 else if (rdev->family >= CHIP_TAHITI) 380 *value = rdev->config.si.backend_map; 381 else if (rdev->family >= CHIP_CAYMAN) 382 *value = rdev->config.cayman.backend_map; 383 else if (rdev->family >= CHIP_CEDAR) 384 *value = rdev->config.evergreen.backend_map; 385 else if (rdev->family >= CHIP_RV770) 386 *value = rdev->config.rv770.backend_map; 387 else if (rdev->family >= CHIP_R600) 388 *value = rdev->config.r600.backend_map; 389 else { 390 return -EINVAL; 391 } 392 break; 393 case RADEON_INFO_VA_START: 394 /* this is where we report if vm is supported or not */ 395 if (rdev->family < CHIP_CAYMAN) 396 return -EINVAL; 397 *value = RADEON_VA_RESERVED_SIZE; 398 break; 399 case RADEON_INFO_IB_VM_MAX_SIZE: 400 /* this is where we report if vm is supported or not */ 401 if (rdev->family < CHIP_CAYMAN) 402 return -EINVAL; 403 *value = RADEON_IB_VM_MAX_SIZE; 404 break; 405 case RADEON_INFO_MAX_PIPES: 406 if (rdev->family >= CHIP_BONAIRE) 407 *value = rdev->config.cik.max_cu_per_sh; 408 else if (rdev->family >= CHIP_TAHITI) 409 *value = rdev->config.si.max_cu_per_sh; 410 else if (rdev->family >= CHIP_CAYMAN) 411 *value = rdev->config.cayman.max_pipes_per_simd; 412 else if (rdev->family >= CHIP_CEDAR) 413 *value = rdev->config.evergreen.max_pipes; 414 else if (rdev->family >= CHIP_RV770) 415 *value = rdev->config.rv770.max_pipes; 416 else if (rdev->family >= CHIP_R600) 417 *value = rdev->config.r600.max_pipes; 418 else { 419 return -EINVAL; 420 } 421 break; 422 case RADEON_INFO_TIMESTAMP: 423 if (rdev->family < CHIP_R600) { 424 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 425 return -EINVAL; 426 } 427 value = (uint32_t*)&value64; 428 value_size = sizeof(uint64_t); 429 value64 = radeon_get_gpu_clock_counter(rdev); 430 break; 431 case RADEON_INFO_MAX_SE: 432 if (rdev->family >= CHIP_BONAIRE) 433 *value = rdev->config.cik.max_shader_engines; 434 else if (rdev->family >= CHIP_TAHITI) 435 *value = rdev->config.si.max_shader_engines; 436 else if (rdev->family >= CHIP_CAYMAN) 437 *value = rdev->config.cayman.max_shader_engines; 438 else if (rdev->family >= CHIP_CEDAR) 439 *value = rdev->config.evergreen.num_ses; 440 else 441 *value = 1; 442 break; 443 case RADEON_INFO_MAX_SH_PER_SE: 444 if (rdev->family >= CHIP_BONAIRE) 445 *value = rdev->config.cik.max_sh_per_se; 446 else if (rdev->family >= CHIP_TAHITI) 447 *value = rdev->config.si.max_sh_per_se; 448 else 449 return -EINVAL; 450 break; 451 case RADEON_INFO_FASTFB_WORKING: 452 *value = rdev->fastfb_working; 453 break; 454 case RADEON_INFO_RING_WORKING: 455 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 456 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 457 return -EFAULT; 458 } 459 switch (*value) { 460 case RADEON_CS_RING_GFX: 461 case RADEON_CS_RING_COMPUTE: 462 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 463 break; 464 case RADEON_CS_RING_DMA: 465 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 466 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 467 break; 468 case RADEON_CS_RING_UVD: 469 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 470 break; 471 case RADEON_CS_RING_VCE: 472 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 473 break; 474 default: 475 return -EINVAL; 476 } 477 break; 478 case RADEON_INFO_SI_TILE_MODE_ARRAY: 479 if (rdev->family >= CHIP_BONAIRE) { 480 value = rdev->config.cik.tile_mode_array; 481 value_size = sizeof(uint32_t)*32; 482 } else if (rdev->family >= CHIP_TAHITI) { 483 value = rdev->config.si.tile_mode_array; 484 value_size = sizeof(uint32_t)*32; 485 } else { 486 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 487 return -EINVAL; 488 } 489 break; 490 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 491 if (rdev->family >= CHIP_BONAIRE) { 492 value = rdev->config.cik.macrotile_mode_array; 493 value_size = sizeof(uint32_t)*16; 494 } else { 495 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 496 return -EINVAL; 497 } 498 break; 499 case RADEON_INFO_SI_CP_DMA_COMPUTE: 500 *value = 1; 501 break; 502 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 503 if (rdev->family >= CHIP_BONAIRE) { 504 *value = rdev->config.cik.backend_enable_mask; 505 } else if (rdev->family >= CHIP_TAHITI) { 506 *value = rdev->config.si.backend_enable_mask; 507 } else { 508 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 509 } 510 break; 511 case RADEON_INFO_MAX_SCLK: 512 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 513 rdev->pm.dpm_enabled) 514 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 515 else 516 *value = rdev->pm.default_sclk * 10; 517 break; 518 case RADEON_INFO_VCE_FW_VERSION: 519 *value = rdev->vce.fw_version; 520 break; 521 case RADEON_INFO_VCE_FB_VERSION: 522 *value = rdev->vce.fb_version; 523 break; 524 case RADEON_INFO_NUM_BYTES_MOVED: 525 value = (uint32_t*)&value64; 526 value_size = sizeof(uint64_t); 527 value64 = atomic64_read(&rdev->num_bytes_moved); 528 break; 529 case RADEON_INFO_VRAM_USAGE: 530 value = (uint32_t*)&value64; 531 value_size = sizeof(uint64_t); 532 value64 = atomic64_read(&rdev->vram_usage); 533 break; 534 case RADEON_INFO_GTT_USAGE: 535 value = (uint32_t*)&value64; 536 value_size = sizeof(uint64_t); 537 value64 = atomic64_read(&rdev->gtt_usage); 538 break; 539 case RADEON_INFO_ACTIVE_CU_COUNT: 540 if (rdev->family >= CHIP_BONAIRE) 541 *value = rdev->config.cik.active_cus; 542 else if (rdev->family >= CHIP_TAHITI) 543 *value = rdev->config.si.active_cus; 544 else if (rdev->family >= CHIP_CAYMAN) 545 *value = rdev->config.cayman.active_simds; 546 else if (rdev->family >= CHIP_CEDAR) 547 *value = rdev->config.evergreen.active_simds; 548 else if (rdev->family >= CHIP_RV770) 549 *value = rdev->config.rv770.active_simds; 550 else if (rdev->family >= CHIP_R600) 551 *value = rdev->config.r600.active_simds; 552 else 553 *value = 1; 554 break; 555 case RADEON_INFO_CURRENT_GPU_TEMP: 556 /* get temperature in millidegrees C */ 557 if (rdev->asic->pm.get_temperature) 558 *value = radeon_get_temperature(rdev); 559 else 560 *value = 0; 561 break; 562 case RADEON_INFO_CURRENT_GPU_SCLK: 563 /* get sclk in Mhz */ 564 if (rdev->pm.dpm_enabled) 565 *value = radeon_dpm_get_current_sclk(rdev) / 100; 566 else 567 *value = rdev->pm.current_sclk / 100; 568 break; 569 case RADEON_INFO_CURRENT_GPU_MCLK: 570 /* get mclk in Mhz */ 571 if (rdev->pm.dpm_enabled) 572 *value = radeon_dpm_get_current_mclk(rdev) / 100; 573 else 574 *value = rdev->pm.current_mclk / 100; 575 break; 576 case RADEON_INFO_READ_REG: 577 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 578 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 579 return -EFAULT; 580 } 581 if (radeon_get_allowed_info_register(rdev, *value, value)) 582 return -EINVAL; 583 break; 584 case RADEON_INFO_VA_UNMAP_WORKING: 585 *value = true; 586 break; 587 case RADEON_INFO_GPU_RESET_COUNTER: 588 *value = atomic_read(&rdev->gpu_reset_counter); 589 break; 590 default: 591 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 592 return -EINVAL; 593 } 594 if (copy_to_user(value_ptr, (char*)value, value_size)) { 595 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 596 return -EFAULT; 597 } 598 return 0; 599 } 600 601 602 /* 603 * Outdated mess for old drm with Xorg being in charge (void function now). 604 */ 605 /** 606 * radeon_driver_lastclose_kms - drm callback for last close 607 * 608 * @dev: drm dev pointer 609 * 610 * Switch vga_switcheroo state after last close (all asics). 611 */ 612 void radeon_driver_lastclose_kms(struct drm_device *dev) 613 { 614 struct radeon_device *rdev = dev->dev_private; 615 616 radeon_fbdev_restore_mode(rdev); 617 vga_switcheroo_process_delayed_switch(); 618 } 619 620 /** 621 * radeon_driver_open_kms - drm callback for open 622 * 623 * @dev: drm dev pointer 624 * @file_priv: drm file 625 * 626 * On device open, init vm on cayman+ (all asics). 627 * Returns 0 on success, error on failure. 628 */ 629 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 630 { 631 struct radeon_device *rdev = dev->dev_private; 632 int r; 633 634 file_priv->driver_priv = NULL; 635 636 r = pm_runtime_get_sync(dev->dev); 637 if (r < 0) 638 return r; 639 640 /* new gpu have virtual address space support */ 641 if (rdev->family >= CHIP_CAYMAN) { 642 struct radeon_fpriv *fpriv; 643 struct radeon_vm *vm; 644 645 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 646 if (unlikely(!fpriv)) { 647 r = -ENOMEM; 648 goto out_suspend; 649 } 650 651 if (rdev->accel_working) { 652 vm = &fpriv->vm; 653 r = radeon_vm_init(rdev, vm); 654 if (r) { 655 kfree(fpriv); 656 goto out_suspend; 657 } 658 659 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 660 if (r) { 661 radeon_vm_fini(rdev, vm); 662 kfree(fpriv); 663 goto out_suspend; 664 } 665 666 /* map the ib pool buffer read only into 667 * virtual address space */ 668 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 669 rdev->ring_tmp_bo.bo); 670 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 671 RADEON_VA_IB_OFFSET, 672 RADEON_VM_PAGE_READABLE | 673 RADEON_VM_PAGE_SNOOPED); 674 if (r) { 675 radeon_vm_fini(rdev, vm); 676 kfree(fpriv); 677 goto out_suspend; 678 } 679 } 680 file_priv->driver_priv = fpriv; 681 } 682 683 out_suspend: 684 pm_runtime_mark_last_busy(dev->dev); 685 pm_runtime_put_autosuspend(dev->dev); 686 return r; 687 } 688 689 /** 690 * radeon_driver_postclose_kms - drm callback for post close 691 * 692 * @dev: drm dev pointer 693 * @file_priv: drm file 694 * 695 * On device close, tear down hyperz and cmask filps on r1xx-r5xx 696 * (all asics). And tear down vm on cayman+ (all asics). 697 */ 698 void radeon_driver_postclose_kms(struct drm_device *dev, 699 struct drm_file *file_priv) 700 { 701 struct radeon_device *rdev = dev->dev_private; 702 703 pm_runtime_get_sync(dev->dev); 704 705 mutex_lock(&rdev->gem.mutex); 706 if (rdev->hyperz_filp == file_priv) 707 rdev->hyperz_filp = NULL; 708 if (rdev->cmask_filp == file_priv) 709 rdev->cmask_filp = NULL; 710 mutex_unlock(&rdev->gem.mutex); 711 712 radeon_uvd_free_handles(rdev, file_priv); 713 radeon_vce_free_handles(rdev, file_priv); 714 715 /* new gpu have virtual address space support */ 716 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 717 struct radeon_fpriv *fpriv = file_priv->driver_priv; 718 struct radeon_vm *vm = &fpriv->vm; 719 int r; 720 721 if (rdev->accel_working) { 722 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 723 if (!r) { 724 if (vm->ib_bo_va) 725 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 726 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 727 } 728 radeon_vm_fini(rdev, vm); 729 } 730 731 kfree(fpriv); 732 file_priv->driver_priv = NULL; 733 } 734 pm_runtime_mark_last_busy(dev->dev); 735 pm_runtime_put_autosuspend(dev->dev); 736 } 737 738 /* 739 * VBlank related functions. 740 */ 741 /** 742 * radeon_get_vblank_counter_kms - get frame count 743 * 744 * @dev: drm dev pointer 745 * @pipe: crtc to get the frame count from 746 * 747 * Gets the frame count on the requested crtc (all asics). 748 * Returns frame count on success, -EINVAL on failure. 749 */ 750 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 751 { 752 int vpos, hpos, stat; 753 u32 count; 754 struct radeon_device *rdev = dev->dev_private; 755 756 if (pipe >= rdev->num_crtc) { 757 DRM_ERROR("Invalid crtc %u\n", pipe); 758 return -EINVAL; 759 } 760 761 /* The hw increments its frame counter at start of vsync, not at start 762 * of vblank, as is required by DRM core vblank counter handling. 763 * Cook the hw count here to make it appear to the caller as if it 764 * incremented at start of vblank. We measure distance to start of 765 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 766 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 767 * result by 1 to give the proper appearance to caller. 768 */ 769 if (rdev->mode_info.crtcs[pipe]) { 770 /* Repeat readout if needed to provide stable result if 771 * we cross start of vsync during the queries. 772 */ 773 do { 774 count = radeon_get_vblank_counter(rdev, pipe); 775 /* Ask radeon_get_crtc_scanoutpos to return vpos as 776 * distance to start of vblank, instead of regular 777 * vertical scanout pos. 778 */ 779 stat = radeon_get_crtc_scanoutpos( 780 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 781 &vpos, &hpos, NULL, NULL, 782 &rdev->mode_info.crtcs[pipe]->base.hwmode); 783 } while (count != radeon_get_vblank_counter(rdev, pipe)); 784 785 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 786 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 787 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 788 } 789 else { 790 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 791 pipe, vpos); 792 793 /* Bump counter if we are at >= leading edge of vblank, 794 * but before vsync where vpos would turn negative and 795 * the hw counter really increments. 796 */ 797 if (vpos >= 0) 798 count++; 799 } 800 } 801 else { 802 /* Fallback to use value as is. */ 803 count = radeon_get_vblank_counter(rdev, pipe); 804 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 805 } 806 807 return count; 808 } 809 810 /** 811 * radeon_enable_vblank_kms - enable vblank interrupt 812 * 813 * @dev: drm dev pointer 814 * @crtc: crtc to enable vblank interrupt for 815 * 816 * Enable the interrupt on the requested crtc (all asics). 817 * Returns 0 on success, -EINVAL on failure. 818 */ 819 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 820 { 821 struct radeon_device *rdev = dev->dev_private; 822 unsigned long irqflags; 823 int r; 824 825 if (crtc < 0 || crtc >= rdev->num_crtc) { 826 DRM_ERROR("Invalid crtc %d\n", crtc); 827 return -EINVAL; 828 } 829 830 spin_lock_irqsave(&rdev->irq.lock, irqflags); 831 rdev->irq.crtc_vblank_int[crtc] = true; 832 r = radeon_irq_set(rdev); 833 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 834 return r; 835 } 836 837 /** 838 * radeon_disable_vblank_kms - disable vblank interrupt 839 * 840 * @dev: drm dev pointer 841 * @crtc: crtc to disable vblank interrupt for 842 * 843 * Disable the interrupt on the requested crtc (all asics). 844 */ 845 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 846 { 847 struct radeon_device *rdev = dev->dev_private; 848 unsigned long irqflags; 849 850 if (crtc < 0 || crtc >= rdev->num_crtc) { 851 DRM_ERROR("Invalid crtc %d\n", crtc); 852 return; 853 } 854 855 spin_lock_irqsave(&rdev->irq.lock, irqflags); 856 rdev->irq.crtc_vblank_int[crtc] = false; 857 radeon_irq_set(rdev); 858 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 859 } 860 861 /** 862 * radeon_get_vblank_timestamp_kms - get vblank timestamp 863 * 864 * @dev: drm dev pointer 865 * @crtc: crtc to get the timestamp for 866 * @max_error: max error 867 * @vblank_time: time value 868 * @flags: flags passed to the driver 869 * 870 * Gets the timestamp on the requested crtc based on the 871 * scanout position. (all asics). 872 * Returns postive status flags on success, negative error on failure. 873 */ 874 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 875 int *max_error, 876 struct timeval *vblank_time, 877 unsigned flags) 878 { 879 struct drm_crtc *drmcrtc; 880 struct radeon_device *rdev = dev->dev_private; 881 882 if (crtc < 0 || crtc >= dev->num_crtcs) { 883 DRM_ERROR("Invalid crtc %d\n", crtc); 884 return -EINVAL; 885 } 886 887 /* Get associated drm_crtc: */ 888 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 889 if (!drmcrtc) 890 return -EINVAL; 891 892 /* Helper routine in DRM core does all the work: */ 893 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 894 vblank_time, flags, 895 &drmcrtc->hwmode); 896 } 897 898 const struct drm_ioctl_desc radeon_ioctls_kms[] = { 899 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 900 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 901 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 902 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 903 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 904 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 905 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 906 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 907 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 908 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 909 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 910 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 911 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 912 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 913 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 914 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 915 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 916 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 917 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 918 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 919 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 920 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 921 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 922 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 923 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 924 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 925 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 926 /* KMS */ 927 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 928 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 929 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 930 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 931 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), 932 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), 933 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 934 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 935 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 936 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 937 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 938 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 939 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 940 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 941 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 942 }; 943 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 944