1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/slab.h> 32 #include <linux/uaccess.h> 33 #include <linux/vga_switcheroo.h> 34 35 #include <drm/drm_file.h> 36 #include <drm/drm_ioctl.h> 37 #include <drm/radeon_drm.h> 38 39 #include "radeon.h" 40 #include "radeon_asic.h" 41 #include "radeon_drv.h" 42 #include "radeon_kms.h" 43 44 #if defined(CONFIG_VGA_SWITCHEROO) 45 bool radeon_has_atpx(void); 46 #else 47 static inline bool radeon_has_atpx(void) { return false; } 48 #endif 49 50 /** 51 * radeon_driver_unload_kms - Main unload function for KMS. 52 * 53 * @dev: drm dev pointer 54 * 55 * This is the main unload function for KMS (all asics). 56 * It calls radeon_modeset_fini() to tear down the 57 * displays, and radeon_device_fini() to tear down 58 * the rest of the device (CP, writeback, etc.). 59 * Returns 0 on success. 60 */ 61 void radeon_driver_unload_kms(struct drm_device *dev) 62 { 63 struct radeon_device *rdev = dev->dev_private; 64 65 if (rdev == NULL) 66 return; 67 68 if (rdev->rmmio == NULL) 69 goto done_free; 70 71 if (radeon_is_px(dev)) { 72 pm_runtime_get_sync(dev->dev); 73 pm_runtime_forbid(dev->dev); 74 pm_runtime_dont_use_autosuspend(dev->dev); 75 } 76 77 radeon_acpi_fini(rdev); 78 79 radeon_modeset_fini(rdev); 80 radeon_device_fini(rdev); 81 82 if (rdev->agp) 83 arch_phys_wc_del(rdev->agp->agp_mtrr); 84 kfree(rdev->agp); 85 rdev->agp = NULL; 86 87 done_free: 88 dev->dev_private = NULL; 89 } 90 91 /** 92 * radeon_driver_load_kms - Main load function for KMS. 93 * 94 * @dev: drm dev pointer 95 * @flags: device flags 96 * 97 * This is the main load function for KMS (all asics). 98 * It calls radeon_device_init() to set up the non-display 99 * parts of the chip (asic init, CP, writeback, etc.), and 100 * radeon_modeset_init() to set up the display parts 101 * (crtcs, encoders, hotplug detect, etc.). 102 * Returns 0 on success, error on failure. 103 */ 104 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 105 { 106 struct pci_dev *pdev = to_pci_dev(dev->dev); 107 struct radeon_device *rdev = dev->dev_private; 108 int r, acpi_status; 109 110 #ifdef __alpha__ 111 rdev->hose = pdev->sysdata; 112 #endif 113 114 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) 115 rdev->agp = radeon_agp_head_init(dev); 116 if (rdev->agp) { 117 rdev->agp->agp_mtrr = arch_phys_wc_add( 118 rdev->agp->agp_info.aper_base, 119 rdev->agp->agp_info.aper_size * 120 1024 * 1024); 121 } 122 123 /* update BUS flag */ 124 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) { 125 flags |= RADEON_IS_AGP; 126 } else if (pci_is_pcie(pdev)) { 127 flags |= RADEON_IS_PCIE; 128 } else { 129 flags |= RADEON_IS_PCI; 130 } 131 132 if ((radeon_runtime_pm != 0) && 133 radeon_has_atpx() && 134 ((flags & RADEON_IS_IGP) == 0) && 135 !pci_is_thunderbolt_attached(pdev)) 136 flags |= RADEON_IS_PX; 137 138 /* radeon_device_init should report only fatal error 139 * like memory allocation failure or iomapping failure, 140 * or memory manager initialization failure, it must 141 * properly initialize the GPU MC controller and permit 142 * VRAM allocation 143 */ 144 r = radeon_device_init(rdev, dev, pdev, flags); 145 if (r) { 146 dev_err(dev->dev, "Fatal error during GPU init\n"); 147 goto out; 148 } 149 150 /* Again modeset_init should fail only on fatal error 151 * otherwise it should provide enough functionalities 152 * for shadowfb to run 153 */ 154 r = radeon_modeset_init(rdev); 155 if (r) 156 dev_err(dev->dev, "Fatal error during modeset init\n"); 157 158 /* Call ACPI methods: require modeset init 159 * but failure is not fatal 160 */ 161 if (!r) { 162 acpi_status = radeon_acpi_init(rdev); 163 if (acpi_status) 164 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 165 } 166 167 if (radeon_is_px(dev)) { 168 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 169 pm_runtime_use_autosuspend(dev->dev); 170 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 171 pm_runtime_set_active(dev->dev); 172 pm_runtime_allow(dev->dev); 173 pm_runtime_put_autosuspend(dev->dev); 174 } 175 176 out: 177 if (r) 178 radeon_driver_unload_kms(dev); 179 180 181 return r; 182 } 183 184 /** 185 * radeon_set_filp_rights - Set filp right. 186 * 187 * @dev: drm dev pointer 188 * @owner: drm file 189 * @applier: drm file 190 * @value: value 191 * 192 * Sets the filp rights for the device (all asics). 193 */ 194 static void radeon_set_filp_rights(struct drm_device *dev, 195 struct drm_file **owner, 196 struct drm_file *applier, 197 uint32_t *value) 198 { 199 struct radeon_device *rdev = dev->dev_private; 200 201 mutex_lock(&rdev->gem.mutex); 202 if (*value == 1) { 203 /* wants rights */ 204 if (!*owner) 205 *owner = applier; 206 } else if (*value == 0) { 207 /* revokes rights */ 208 if (*owner == applier) 209 *owner = NULL; 210 } 211 *value = *owner == applier ? 1 : 0; 212 mutex_unlock(&rdev->gem.mutex); 213 } 214 215 /* 216 * Userspace get information ioctl 217 */ 218 /** 219 * radeon_info_ioctl - answer a device specific request. 220 * 221 * @dev: drm device pointer 222 * @data: request object 223 * @filp: drm filp 224 * 225 * This function is used to pass device specific parameters to the userspace 226 * drivers. Examples include: pci device id, pipeline parms, tiling params, 227 * etc. (all asics). 228 * Returns 0 on success, -EINVAL on failure. 229 */ 230 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 231 { 232 struct radeon_device *rdev = dev->dev_private; 233 struct drm_radeon_info *info = data; 234 struct radeon_mode_info *minfo = &rdev->mode_info; 235 uint32_t *value, value_tmp, *value_ptr, value_size; 236 struct ttm_resource_manager *man; 237 uint64_t value64; 238 struct drm_crtc *crtc; 239 int i, found; 240 241 value_ptr = (uint32_t *)((unsigned long)info->value); 242 value = &value_tmp; 243 value_size = sizeof(uint32_t); 244 245 switch (info->request) { 246 case RADEON_INFO_DEVICE_ID: 247 *value = to_pci_dev(dev->dev)->device; 248 break; 249 case RADEON_INFO_NUM_GB_PIPES: 250 *value = rdev->num_gb_pipes; 251 break; 252 case RADEON_INFO_NUM_Z_PIPES: 253 *value = rdev->num_z_pipes; 254 break; 255 case RADEON_INFO_ACCEL_WORKING: 256 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 257 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 258 *value = false; 259 else 260 *value = rdev->accel_working; 261 break; 262 case RADEON_INFO_CRTC_FROM_ID: 263 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 264 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 265 return -EFAULT; 266 } 267 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 268 crtc = (struct drm_crtc *)minfo->crtcs[i]; 269 if (crtc && crtc->base.id == *value) { 270 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 271 *value = radeon_crtc->crtc_id; 272 found = 1; 273 break; 274 } 275 } 276 if (!found) { 277 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 278 return -EINVAL; 279 } 280 break; 281 case RADEON_INFO_ACCEL_WORKING2: 282 if (rdev->family == CHIP_HAWAII) { 283 if (rdev->accel_working) { 284 if (rdev->new_fw) 285 *value = 3; 286 else 287 *value = 2; 288 } else { 289 *value = 0; 290 } 291 } else { 292 *value = rdev->accel_working; 293 } 294 break; 295 case RADEON_INFO_TILING_CONFIG: 296 if (rdev->family >= CHIP_BONAIRE) 297 *value = rdev->config.cik.tile_config; 298 else if (rdev->family >= CHIP_TAHITI) 299 *value = rdev->config.si.tile_config; 300 else if (rdev->family >= CHIP_CAYMAN) 301 *value = rdev->config.cayman.tile_config; 302 else if (rdev->family >= CHIP_CEDAR) 303 *value = rdev->config.evergreen.tile_config; 304 else if (rdev->family >= CHIP_RV770) 305 *value = rdev->config.rv770.tile_config; 306 else if (rdev->family >= CHIP_R600) 307 *value = rdev->config.r600.tile_config; 308 else { 309 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 310 return -EINVAL; 311 } 312 break; 313 case RADEON_INFO_WANT_HYPERZ: 314 /* The "value" here is both an input and output parameter. 315 * If the input value is 1, filp requests hyper-z access. 316 * If the input value is 0, filp revokes its hyper-z access. 317 * 318 * When returning, the value is 1 if filp owns hyper-z access, 319 * 0 otherwise. */ 320 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 321 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 322 return -EFAULT; 323 } 324 if (*value >= 2) { 325 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 326 return -EINVAL; 327 } 328 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 329 break; 330 case RADEON_INFO_WANT_CMASK: 331 /* The same logic as Hyper-Z. */ 332 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 333 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 334 return -EFAULT; 335 } 336 if (*value >= 2) { 337 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 338 return -EINVAL; 339 } 340 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 341 break; 342 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 343 /* return clock value in KHz */ 344 if (rdev->asic->get_xclk) 345 *value = radeon_get_xclk(rdev) * 10; 346 else 347 *value = rdev->clock.spll.reference_freq * 10; 348 break; 349 case RADEON_INFO_NUM_BACKENDS: 350 if (rdev->family >= CHIP_BONAIRE) 351 *value = rdev->config.cik.max_backends_per_se * 352 rdev->config.cik.max_shader_engines; 353 else if (rdev->family >= CHIP_TAHITI) 354 *value = rdev->config.si.max_backends_per_se * 355 rdev->config.si.max_shader_engines; 356 else if (rdev->family >= CHIP_CAYMAN) 357 *value = rdev->config.cayman.max_backends_per_se * 358 rdev->config.cayman.max_shader_engines; 359 else if (rdev->family >= CHIP_CEDAR) 360 *value = rdev->config.evergreen.max_backends; 361 else if (rdev->family >= CHIP_RV770) 362 *value = rdev->config.rv770.max_backends; 363 else if (rdev->family >= CHIP_R600) 364 *value = rdev->config.r600.max_backends; 365 else { 366 return -EINVAL; 367 } 368 break; 369 case RADEON_INFO_NUM_TILE_PIPES: 370 if (rdev->family >= CHIP_BONAIRE) 371 *value = rdev->config.cik.max_tile_pipes; 372 else if (rdev->family >= CHIP_TAHITI) 373 *value = rdev->config.si.max_tile_pipes; 374 else if (rdev->family >= CHIP_CAYMAN) 375 *value = rdev->config.cayman.max_tile_pipes; 376 else if (rdev->family >= CHIP_CEDAR) 377 *value = rdev->config.evergreen.max_tile_pipes; 378 else if (rdev->family >= CHIP_RV770) 379 *value = rdev->config.rv770.max_tile_pipes; 380 else if (rdev->family >= CHIP_R600) 381 *value = rdev->config.r600.max_tile_pipes; 382 else { 383 return -EINVAL; 384 } 385 break; 386 case RADEON_INFO_FUSION_GART_WORKING: 387 *value = 1; 388 break; 389 case RADEON_INFO_BACKEND_MAP: 390 if (rdev->family >= CHIP_BONAIRE) 391 *value = rdev->config.cik.backend_map; 392 else if (rdev->family >= CHIP_TAHITI) 393 *value = rdev->config.si.backend_map; 394 else if (rdev->family >= CHIP_CAYMAN) 395 *value = rdev->config.cayman.backend_map; 396 else if (rdev->family >= CHIP_CEDAR) 397 *value = rdev->config.evergreen.backend_map; 398 else if (rdev->family >= CHIP_RV770) 399 *value = rdev->config.rv770.backend_map; 400 else if (rdev->family >= CHIP_R600) 401 *value = rdev->config.r600.backend_map; 402 else { 403 return -EINVAL; 404 } 405 break; 406 case RADEON_INFO_VA_START: 407 /* this is where we report if vm is supported or not */ 408 if (rdev->family < CHIP_CAYMAN) 409 return -EINVAL; 410 *value = RADEON_VA_RESERVED_SIZE; 411 break; 412 case RADEON_INFO_IB_VM_MAX_SIZE: 413 /* this is where we report if vm is supported or not */ 414 if (rdev->family < CHIP_CAYMAN) 415 return -EINVAL; 416 *value = RADEON_IB_VM_MAX_SIZE; 417 break; 418 case RADEON_INFO_MAX_PIPES: 419 if (rdev->family >= CHIP_BONAIRE) 420 *value = rdev->config.cik.max_cu_per_sh; 421 else if (rdev->family >= CHIP_TAHITI) 422 *value = rdev->config.si.max_cu_per_sh; 423 else if (rdev->family >= CHIP_CAYMAN) 424 *value = rdev->config.cayman.max_pipes_per_simd; 425 else if (rdev->family >= CHIP_CEDAR) 426 *value = rdev->config.evergreen.max_pipes; 427 else if (rdev->family >= CHIP_RV770) 428 *value = rdev->config.rv770.max_pipes; 429 else if (rdev->family >= CHIP_R600) 430 *value = rdev->config.r600.max_pipes; 431 else { 432 return -EINVAL; 433 } 434 break; 435 case RADEON_INFO_TIMESTAMP: 436 if (rdev->family < CHIP_R600) { 437 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 438 return -EINVAL; 439 } 440 value = (uint32_t *)&value64; 441 value_size = sizeof(uint64_t); 442 value64 = radeon_get_gpu_clock_counter(rdev); 443 break; 444 case RADEON_INFO_MAX_SE: 445 if (rdev->family >= CHIP_BONAIRE) 446 *value = rdev->config.cik.max_shader_engines; 447 else if (rdev->family >= CHIP_TAHITI) 448 *value = rdev->config.si.max_shader_engines; 449 else if (rdev->family >= CHIP_CAYMAN) 450 *value = rdev->config.cayman.max_shader_engines; 451 else if (rdev->family >= CHIP_CEDAR) 452 *value = rdev->config.evergreen.num_ses; 453 else 454 *value = 1; 455 break; 456 case RADEON_INFO_MAX_SH_PER_SE: 457 if (rdev->family >= CHIP_BONAIRE) 458 *value = rdev->config.cik.max_sh_per_se; 459 else if (rdev->family >= CHIP_TAHITI) 460 *value = rdev->config.si.max_sh_per_se; 461 else 462 return -EINVAL; 463 break; 464 case RADEON_INFO_FASTFB_WORKING: 465 *value = rdev->fastfb_working; 466 break; 467 case RADEON_INFO_RING_WORKING: 468 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 469 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 470 return -EFAULT; 471 } 472 switch (*value) { 473 case RADEON_CS_RING_GFX: 474 case RADEON_CS_RING_COMPUTE: 475 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 476 break; 477 case RADEON_CS_RING_DMA: 478 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 479 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 480 break; 481 case RADEON_CS_RING_UVD: 482 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 483 break; 484 case RADEON_CS_RING_VCE: 485 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 486 break; 487 default: 488 return -EINVAL; 489 } 490 break; 491 case RADEON_INFO_SI_TILE_MODE_ARRAY: 492 if (rdev->family >= CHIP_BONAIRE) { 493 value = rdev->config.cik.tile_mode_array; 494 value_size = sizeof(uint32_t)*32; 495 } else if (rdev->family >= CHIP_TAHITI) { 496 value = rdev->config.si.tile_mode_array; 497 value_size = sizeof(uint32_t)*32; 498 } else { 499 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 500 return -EINVAL; 501 } 502 break; 503 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 504 if (rdev->family >= CHIP_BONAIRE) { 505 value = rdev->config.cik.macrotile_mode_array; 506 value_size = sizeof(uint32_t)*16; 507 } else { 508 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 509 return -EINVAL; 510 } 511 break; 512 case RADEON_INFO_SI_CP_DMA_COMPUTE: 513 *value = 1; 514 break; 515 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 516 if (rdev->family >= CHIP_BONAIRE) { 517 *value = rdev->config.cik.backend_enable_mask; 518 } else if (rdev->family >= CHIP_TAHITI) { 519 *value = rdev->config.si.backend_enable_mask; 520 } else { 521 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 522 return -EINVAL; 523 } 524 break; 525 case RADEON_INFO_MAX_SCLK: 526 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 527 rdev->pm.dpm_enabled) 528 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 529 else 530 *value = rdev->pm.default_sclk * 10; 531 break; 532 case RADEON_INFO_VCE_FW_VERSION: 533 *value = rdev->vce.fw_version; 534 break; 535 case RADEON_INFO_VCE_FB_VERSION: 536 *value = rdev->vce.fb_version; 537 break; 538 case RADEON_INFO_NUM_BYTES_MOVED: 539 value = (uint32_t *)&value64; 540 value_size = sizeof(uint64_t); 541 value64 = atomic64_read(&rdev->num_bytes_moved); 542 break; 543 case RADEON_INFO_VRAM_USAGE: 544 value = (uint32_t *)&value64; 545 value_size = sizeof(uint64_t); 546 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 547 value64 = ttm_resource_manager_usage(man); 548 break; 549 case RADEON_INFO_GTT_USAGE: 550 value = (uint32_t *)&value64; 551 value_size = sizeof(uint64_t); 552 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT); 553 value64 = ttm_resource_manager_usage(man); 554 break; 555 case RADEON_INFO_ACTIVE_CU_COUNT: 556 if (rdev->family >= CHIP_BONAIRE) 557 *value = rdev->config.cik.active_cus; 558 else if (rdev->family >= CHIP_TAHITI) 559 *value = rdev->config.si.active_cus; 560 else if (rdev->family >= CHIP_CAYMAN) 561 *value = rdev->config.cayman.active_simds; 562 else if (rdev->family >= CHIP_CEDAR) 563 *value = rdev->config.evergreen.active_simds; 564 else if (rdev->family >= CHIP_RV770) 565 *value = rdev->config.rv770.active_simds; 566 else if (rdev->family >= CHIP_R600) 567 *value = rdev->config.r600.active_simds; 568 else 569 *value = 1; 570 break; 571 case RADEON_INFO_CURRENT_GPU_TEMP: 572 /* get temperature in millidegrees C */ 573 if (rdev->asic->pm.get_temperature) 574 *value = radeon_get_temperature(rdev); 575 else 576 *value = 0; 577 break; 578 case RADEON_INFO_CURRENT_GPU_SCLK: 579 /* get sclk in Mhz */ 580 if (rdev->pm.dpm_enabled) 581 *value = radeon_dpm_get_current_sclk(rdev) / 100; 582 else 583 *value = rdev->pm.current_sclk / 100; 584 break; 585 case RADEON_INFO_CURRENT_GPU_MCLK: 586 /* get mclk in Mhz */ 587 if (rdev->pm.dpm_enabled) 588 *value = radeon_dpm_get_current_mclk(rdev) / 100; 589 else 590 *value = rdev->pm.current_mclk / 100; 591 break; 592 case RADEON_INFO_READ_REG: 593 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 594 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 595 return -EFAULT; 596 } 597 if (radeon_get_allowed_info_register(rdev, *value, value)) 598 return -EINVAL; 599 break; 600 case RADEON_INFO_VA_UNMAP_WORKING: 601 *value = true; 602 break; 603 case RADEON_INFO_GPU_RESET_COUNTER: 604 *value = atomic_read(&rdev->gpu_reset_counter); 605 break; 606 default: 607 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 608 return -EINVAL; 609 } 610 if (copy_to_user(value_ptr, (char *)value, value_size)) { 611 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 612 return -EFAULT; 613 } 614 return 0; 615 } 616 617 /** 618 * radeon_driver_open_kms - drm callback for open 619 * 620 * @dev: drm dev pointer 621 * @file_priv: drm file 622 * 623 * On device open, init vm on cayman+ (all asics). 624 * Returns 0 on success, error on failure. 625 */ 626 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 627 { 628 struct radeon_device *rdev = dev->dev_private; 629 struct radeon_fpriv *fpriv; 630 struct radeon_vm *vm; 631 int r; 632 633 file_priv->driver_priv = NULL; 634 635 r = pm_runtime_get_sync(dev->dev); 636 if (r < 0) { 637 pm_runtime_put_autosuspend(dev->dev); 638 return r; 639 } 640 641 /* new gpu have virtual address space support */ 642 if (rdev->family >= CHIP_CAYMAN) { 643 644 fpriv = kzalloc_obj(*fpriv); 645 if (unlikely(!fpriv)) { 646 r = -ENOMEM; 647 goto err_suspend; 648 } 649 650 if (rdev->accel_working) { 651 vm = &fpriv->vm; 652 r = radeon_vm_init(rdev, vm); 653 if (r) 654 goto err_fpriv; 655 656 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 657 if (r) 658 goto err_vm_fini; 659 660 /* map the ib pool buffer read only into 661 * virtual address space */ 662 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 663 rdev->ring_tmp_bo.bo); 664 if (!vm->ib_bo_va) { 665 r = -ENOMEM; 666 goto err_vm_fini; 667 } 668 669 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 670 RADEON_VA_IB_OFFSET, 671 RADEON_VM_PAGE_READABLE | 672 RADEON_VM_PAGE_SNOOPED); 673 if (r) 674 goto err_vm_fini; 675 } 676 file_priv->driver_priv = fpriv; 677 } 678 679 pm_runtime_put_autosuspend(dev->dev); 680 return 0; 681 682 err_vm_fini: 683 radeon_vm_fini(rdev, vm); 684 err_fpriv: 685 kfree(fpriv); 686 687 err_suspend: 688 pm_runtime_put_autosuspend(dev->dev); 689 return r; 690 } 691 692 /** 693 * radeon_driver_postclose_kms - drm callback for post close 694 * 695 * @dev: drm dev pointer 696 * @file_priv: drm file 697 * 698 * On device close, tear down hyperz and cmask filps on r1xx-r5xx 699 * (all asics). And tear down vm on cayman+ (all asics). 700 */ 701 void radeon_driver_postclose_kms(struct drm_device *dev, 702 struct drm_file *file_priv) 703 { 704 struct radeon_device *rdev = dev->dev_private; 705 706 pm_runtime_get_sync(dev->dev); 707 708 mutex_lock(&rdev->gem.mutex); 709 if (rdev->hyperz_filp == file_priv) 710 rdev->hyperz_filp = NULL; 711 if (rdev->cmask_filp == file_priv) 712 rdev->cmask_filp = NULL; 713 mutex_unlock(&rdev->gem.mutex); 714 715 radeon_uvd_free_handles(rdev, file_priv); 716 radeon_vce_free_handles(rdev, file_priv); 717 718 /* new gpu have virtual address space support */ 719 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 720 struct radeon_fpriv *fpriv = file_priv->driver_priv; 721 struct radeon_vm *vm = &fpriv->vm; 722 int r; 723 724 if (rdev->accel_working) { 725 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 726 if (!r) { 727 if (vm->ib_bo_va) 728 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 729 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 730 } 731 radeon_vm_fini(rdev, vm); 732 } 733 734 kfree(fpriv); 735 file_priv->driver_priv = NULL; 736 } 737 pm_runtime_put_autosuspend(dev->dev); 738 } 739 740 /* 741 * VBlank related functions. 742 */ 743 /** 744 * radeon_get_vblank_counter_kms - get frame count 745 * 746 * @crtc: crtc to get the frame count from 747 * 748 * Gets the frame count on the requested crtc (all asics). 749 * Returns frame count on success, -EINVAL on failure. 750 */ 751 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc) 752 { 753 struct drm_device *dev = crtc->dev; 754 unsigned int pipe = crtc->index; 755 int vpos, hpos, stat; 756 u32 count; 757 struct radeon_device *rdev = dev->dev_private; 758 759 if (pipe >= rdev->num_crtc) { 760 DRM_ERROR("Invalid crtc %u\n", pipe); 761 return -EINVAL; 762 } 763 764 /* The hw increments its frame counter at start of vsync, not at start 765 * of vblank, as is required by DRM core vblank counter handling. 766 * Cook the hw count here to make it appear to the caller as if it 767 * incremented at start of vblank. We measure distance to start of 768 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 769 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 770 * result by 1 to give the proper appearance to caller. 771 */ 772 if (rdev->mode_info.crtcs[pipe]) { 773 /* Repeat readout if needed to provide stable result if 774 * we cross start of vsync during the queries. 775 */ 776 do { 777 count = radeon_get_vblank_counter(rdev, pipe); 778 /* Ask radeon_get_crtc_scanoutpos to return vpos as 779 * distance to start of vblank, instead of regular 780 * vertical scanout pos. 781 */ 782 stat = radeon_get_crtc_scanoutpos( 783 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 784 &vpos, &hpos, NULL, NULL, 785 &rdev->mode_info.crtcs[pipe]->base.hwmode); 786 } while (count != radeon_get_vblank_counter(rdev, pipe)); 787 788 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 789 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 790 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 791 } 792 else { 793 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n", 794 pipe, vpos); 795 796 /* Bump counter if we are at >= leading edge of vblank, 797 * but before vsync where vpos would turn negative and 798 * the hw counter really increments. 799 */ 800 if (vpos >= 0) 801 count++; 802 } 803 } 804 else { 805 /* Fallback to use value as is. */ 806 count = radeon_get_vblank_counter(rdev, pipe); 807 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 808 } 809 810 return count; 811 } 812 813 /** 814 * radeon_enable_vblank_kms - enable vblank interrupt 815 * 816 * @crtc: crtc to enable vblank interrupt for 817 * 818 * Enable the interrupt on the requested crtc (all asics). 819 * Returns 0 on success, -EINVAL on failure. 820 */ 821 int radeon_enable_vblank_kms(struct drm_crtc *crtc) 822 { 823 struct drm_device *dev = crtc->dev; 824 unsigned int pipe = crtc->index; 825 struct radeon_device *rdev = dev->dev_private; 826 unsigned long irqflags; 827 int r; 828 829 if (pipe >= rdev->num_crtc) { 830 DRM_ERROR("Invalid crtc %d\n", pipe); 831 return -EINVAL; 832 } 833 834 spin_lock_irqsave(&rdev->irq.lock, irqflags); 835 rdev->irq.crtc_vblank_int[pipe] = true; 836 r = radeon_irq_set(rdev); 837 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 838 return r; 839 } 840 841 /** 842 * radeon_disable_vblank_kms - disable vblank interrupt 843 * 844 * @crtc: crtc to disable vblank interrupt for 845 * 846 * Disable the interrupt on the requested crtc (all asics). 847 */ 848 void radeon_disable_vblank_kms(struct drm_crtc *crtc) 849 { 850 struct drm_device *dev = crtc->dev; 851 unsigned int pipe = crtc->index; 852 struct radeon_device *rdev = dev->dev_private; 853 unsigned long irqflags; 854 855 if (pipe >= rdev->num_crtc) { 856 DRM_ERROR("Invalid crtc %d\n", pipe); 857 return; 858 } 859 860 spin_lock_irqsave(&rdev->irq.lock, irqflags); 861 rdev->irq.crtc_vblank_int[pipe] = false; 862 radeon_irq_set(rdev); 863 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 864 } 865