1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon_drm.h" 30 #include "radeon.h" 31 #include "radeon_reg.h" 32 33 /* 34 * Common GART table functions. 35 */ 36 int radeon_gart_table_ram_alloc(struct radeon_device *rdev) 37 { 38 void *ptr; 39 40 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, 41 &rdev->gart.table_addr); 42 if (ptr == NULL) { 43 return -ENOMEM; 44 } 45 #ifdef CONFIG_X86 46 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 47 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 48 set_memory_uc((unsigned long)ptr, 49 rdev->gart.table_size >> PAGE_SHIFT); 50 } 51 #endif 52 rdev->gart.table.ram.ptr = ptr; 53 memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size); 54 return 0; 55 } 56 57 void radeon_gart_table_ram_free(struct radeon_device *rdev) 58 { 59 if (rdev->gart.table.ram.ptr == NULL) { 60 return; 61 } 62 #ifdef CONFIG_X86 63 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 64 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 65 set_memory_wb((unsigned long)rdev->gart.table.ram.ptr, 66 rdev->gart.table_size >> PAGE_SHIFT); 67 } 68 #endif 69 pci_free_consistent(rdev->pdev, rdev->gart.table_size, 70 (void *)rdev->gart.table.ram.ptr, 71 rdev->gart.table_addr); 72 rdev->gart.table.ram.ptr = NULL; 73 rdev->gart.table_addr = 0; 74 } 75 76 int radeon_gart_table_vram_alloc(struct radeon_device *rdev) 77 { 78 int r; 79 80 if (rdev->gart.table.vram.robj == NULL) { 81 r = radeon_object_create(rdev, NULL, 82 rdev->gart.table_size, 83 true, 84 RADEON_GEM_DOMAIN_VRAM, 85 false, &rdev->gart.table.vram.robj); 86 if (r) { 87 return r; 88 } 89 } 90 return 0; 91 } 92 93 int radeon_gart_table_vram_pin(struct radeon_device *rdev) 94 { 95 uint64_t gpu_addr; 96 int r; 97 98 r = radeon_object_pin(rdev->gart.table.vram.robj, 99 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 100 if (r) { 101 radeon_object_unref(&rdev->gart.table.vram.robj); 102 return r; 103 } 104 r = radeon_object_kmap(rdev->gart.table.vram.robj, 105 (void **)&rdev->gart.table.vram.ptr); 106 if (r) { 107 radeon_object_unpin(rdev->gart.table.vram.robj); 108 radeon_object_unref(&rdev->gart.table.vram.robj); 109 DRM_ERROR("radeon: failed to map gart vram table.\n"); 110 return r; 111 } 112 rdev->gart.table_addr = gpu_addr; 113 return 0; 114 } 115 116 void radeon_gart_table_vram_free(struct radeon_device *rdev) 117 { 118 if (rdev->gart.table.vram.robj == NULL) { 119 return; 120 } 121 radeon_object_kunmap(rdev->gart.table.vram.robj); 122 radeon_object_unpin(rdev->gart.table.vram.robj); 123 radeon_object_unref(&rdev->gart.table.vram.robj); 124 } 125 126 127 128 129 /* 130 * Common gart functions. 131 */ 132 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 133 int pages) 134 { 135 unsigned t; 136 unsigned p; 137 int i, j; 138 139 if (!rdev->gart.ready) { 140 WARN(1, "trying to unbind memory to unitialized GART !\n"); 141 return; 142 } 143 t = offset / RADEON_GPU_PAGE_SIZE; 144 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 145 for (i = 0; i < pages; i++, p++) { 146 if (rdev->gart.pages[p]) { 147 pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], 148 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 149 rdev->gart.pages[p] = NULL; 150 rdev->gart.pages_addr[p] = 0; 151 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 152 radeon_gart_set_page(rdev, t, 0); 153 } 154 } 155 } 156 mb(); 157 radeon_gart_tlb_flush(rdev); 158 } 159 160 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 161 int pages, struct page **pagelist) 162 { 163 unsigned t; 164 unsigned p; 165 uint64_t page_base; 166 int i, j; 167 168 if (!rdev->gart.ready) { 169 DRM_ERROR("trying to bind memory to unitialized GART !\n"); 170 return -EINVAL; 171 } 172 t = offset / RADEON_GPU_PAGE_SIZE; 173 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 174 175 for (i = 0; i < pages; i++, p++) { 176 /* we need to support large memory configurations */ 177 /* assume that unbind have already been call on the range */ 178 rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i], 179 0, PAGE_SIZE, 180 PCI_DMA_BIDIRECTIONAL); 181 if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { 182 /* FIXME: failed to map page (return -ENOMEM?) */ 183 radeon_gart_unbind(rdev, offset, pages); 184 return -ENOMEM; 185 } 186 rdev->gart.pages[p] = pagelist[i]; 187 page_base = rdev->gart.pages_addr[p]; 188 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 189 radeon_gart_set_page(rdev, t, page_base); 190 page_base += RADEON_GPU_PAGE_SIZE; 191 } 192 } 193 mb(); 194 radeon_gart_tlb_flush(rdev); 195 return 0; 196 } 197 198 int radeon_gart_init(struct radeon_device *rdev) 199 { 200 if (rdev->gart.pages) { 201 return 0; 202 } 203 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ 204 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { 205 DRM_ERROR("Page size is smaller than GPU page size!\n"); 206 return -EINVAL; 207 } 208 /* Compute table size */ 209 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; 210 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; 211 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 212 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 213 /* Allocate pages table */ 214 rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages, 215 GFP_KERNEL); 216 if (rdev->gart.pages == NULL) { 217 radeon_gart_fini(rdev); 218 return -ENOMEM; 219 } 220 rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) * 221 rdev->gart.num_cpu_pages, GFP_KERNEL); 222 if (rdev->gart.pages_addr == NULL) { 223 radeon_gart_fini(rdev); 224 return -ENOMEM; 225 } 226 return 0; 227 } 228 229 void radeon_gart_fini(struct radeon_device *rdev) 230 { 231 if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { 232 /* unbind pages */ 233 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); 234 } 235 rdev->gart.ready = false; 236 kfree(rdev->gart.pages); 237 kfree(rdev->gart.pages_addr); 238 rdev->gart.pages = NULL; 239 rdev->gart.pages_addr = NULL; 240 } 241