1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon_drm.h" 30 #include "radeon.h" 31 #include "radeon_reg.h" 32 33 /* 34 * Common GART table functions. 35 */ 36 int radeon_gart_table_ram_alloc(struct radeon_device *rdev) 37 { 38 void *ptr; 39 40 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, 41 &rdev->gart.table_addr); 42 if (ptr == NULL) { 43 return -ENOMEM; 44 } 45 #ifdef CONFIG_X86 46 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 47 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 48 set_memory_uc((unsigned long)ptr, 49 rdev->gart.table_size >> PAGE_SHIFT); 50 } 51 #endif 52 rdev->gart.table.ram.ptr = ptr; 53 memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size); 54 return 0; 55 } 56 57 void radeon_gart_table_ram_free(struct radeon_device *rdev) 58 { 59 if (rdev->gart.table.ram.ptr == NULL) { 60 return; 61 } 62 #ifdef CONFIG_X86 63 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 64 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 65 set_memory_wb((unsigned long)rdev->gart.table.ram.ptr, 66 rdev->gart.table_size >> PAGE_SHIFT); 67 } 68 #endif 69 pci_free_consistent(rdev->pdev, rdev->gart.table_size, 70 (void *)rdev->gart.table.ram.ptr, 71 rdev->gart.table_addr); 72 rdev->gart.table.ram.ptr = NULL; 73 rdev->gart.table_addr = 0; 74 } 75 76 int radeon_gart_table_vram_alloc(struct radeon_device *rdev) 77 { 78 int r; 79 80 if (rdev->gart.table.vram.robj == NULL) { 81 r = radeon_bo_create(rdev, rdev->gart.table_size, 82 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 83 &rdev->gart.table.vram.robj); 84 if (r) { 85 return r; 86 } 87 } 88 return 0; 89 } 90 91 int radeon_gart_table_vram_pin(struct radeon_device *rdev) 92 { 93 uint64_t gpu_addr; 94 int r; 95 96 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 97 if (unlikely(r != 0)) 98 return r; 99 r = radeon_bo_pin(rdev->gart.table.vram.robj, 100 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 101 if (r) { 102 radeon_bo_unreserve(rdev->gart.table.vram.robj); 103 return r; 104 } 105 r = radeon_bo_kmap(rdev->gart.table.vram.robj, 106 (void **)&rdev->gart.table.vram.ptr); 107 if (r) 108 radeon_bo_unpin(rdev->gart.table.vram.robj); 109 radeon_bo_unreserve(rdev->gart.table.vram.robj); 110 rdev->gart.table_addr = gpu_addr; 111 return r; 112 } 113 114 void radeon_gart_table_vram_free(struct radeon_device *rdev) 115 { 116 int r; 117 118 if (rdev->gart.table.vram.robj == NULL) { 119 return; 120 } 121 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 122 if (likely(r == 0)) { 123 radeon_bo_kunmap(rdev->gart.table.vram.robj); 124 radeon_bo_unpin(rdev->gart.table.vram.robj); 125 radeon_bo_unreserve(rdev->gart.table.vram.robj); 126 } 127 radeon_bo_unref(&rdev->gart.table.vram.robj); 128 } 129 130 131 132 133 /* 134 * Common gart functions. 135 */ 136 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 137 int pages) 138 { 139 unsigned t; 140 unsigned p; 141 int i, j; 142 u64 page_base; 143 144 if (!rdev->gart.ready) { 145 WARN(1, "trying to unbind memory to unitialized GART !\n"); 146 return; 147 } 148 t = offset / RADEON_GPU_PAGE_SIZE; 149 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 150 for (i = 0; i < pages; i++, p++) { 151 if (rdev->gart.pages[p]) { 152 if (!rdev->gart.ttm_alloced[p]) 153 pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], 154 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 155 rdev->gart.pages[p] = NULL; 156 rdev->gart.pages_addr[p] = rdev->dummy_page.addr; 157 page_base = rdev->gart.pages_addr[p]; 158 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 159 radeon_gart_set_page(rdev, t, page_base); 160 page_base += RADEON_GPU_PAGE_SIZE; 161 } 162 } 163 } 164 mb(); 165 radeon_gart_tlb_flush(rdev); 166 } 167 168 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 169 int pages, struct page **pagelist, dma_addr_t *dma_addr) 170 { 171 unsigned t; 172 unsigned p; 173 uint64_t page_base; 174 int i, j; 175 176 if (!rdev->gart.ready) { 177 WARN(1, "trying to bind memory to unitialized GART !\n"); 178 return -EINVAL; 179 } 180 t = offset / RADEON_GPU_PAGE_SIZE; 181 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 182 183 for (i = 0; i < pages; i++, p++) { 184 /* we reverted the patch using dma_addr in TTM for now but this 185 * code stops building on alpha so just comment it out for now */ 186 if (0) { /*dma_addr[i] != DMA_ERROR_CODE) */ 187 rdev->gart.ttm_alloced[p] = true; 188 rdev->gart.pages_addr[p] = dma_addr[i]; 189 } else { 190 /* we need to support large memory configurations */ 191 /* assume that unbind have already been call on the range */ 192 rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i], 193 0, PAGE_SIZE, 194 PCI_DMA_BIDIRECTIONAL); 195 if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { 196 /* FIXME: failed to map page (return -ENOMEM?) */ 197 radeon_gart_unbind(rdev, offset, pages); 198 return -ENOMEM; 199 } 200 } 201 rdev->gart.pages[p] = pagelist[i]; 202 page_base = rdev->gart.pages_addr[p]; 203 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 204 radeon_gart_set_page(rdev, t, page_base); 205 page_base += RADEON_GPU_PAGE_SIZE; 206 } 207 } 208 mb(); 209 radeon_gart_tlb_flush(rdev); 210 return 0; 211 } 212 213 void radeon_gart_restore(struct radeon_device *rdev) 214 { 215 int i, j, t; 216 u64 page_base; 217 218 for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) { 219 page_base = rdev->gart.pages_addr[i]; 220 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 221 radeon_gart_set_page(rdev, t, page_base); 222 page_base += RADEON_GPU_PAGE_SIZE; 223 } 224 } 225 mb(); 226 radeon_gart_tlb_flush(rdev); 227 } 228 229 int radeon_gart_init(struct radeon_device *rdev) 230 { 231 int r, i; 232 233 if (rdev->gart.pages) { 234 return 0; 235 } 236 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ 237 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { 238 DRM_ERROR("Page size is smaller than GPU page size!\n"); 239 return -EINVAL; 240 } 241 r = radeon_dummy_page_init(rdev); 242 if (r) 243 return r; 244 /* Compute table size */ 245 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; 246 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; 247 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 248 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 249 /* Allocate pages table */ 250 rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages, 251 GFP_KERNEL); 252 if (rdev->gart.pages == NULL) { 253 radeon_gart_fini(rdev); 254 return -ENOMEM; 255 } 256 rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) * 257 rdev->gart.num_cpu_pages, GFP_KERNEL); 258 if (rdev->gart.pages_addr == NULL) { 259 radeon_gart_fini(rdev); 260 return -ENOMEM; 261 } 262 rdev->gart.ttm_alloced = kzalloc(sizeof(bool) * 263 rdev->gart.num_cpu_pages, GFP_KERNEL); 264 if (rdev->gart.ttm_alloced == NULL) { 265 radeon_gart_fini(rdev); 266 return -ENOMEM; 267 } 268 /* set GART entry to point to the dummy page by default */ 269 for (i = 0; i < rdev->gart.num_cpu_pages; i++) { 270 rdev->gart.pages_addr[i] = rdev->dummy_page.addr; 271 } 272 return 0; 273 } 274 275 void radeon_gart_fini(struct radeon_device *rdev) 276 { 277 if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { 278 /* unbind pages */ 279 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); 280 } 281 rdev->gart.ready = false; 282 kfree(rdev->gart.pages); 283 kfree(rdev->gart.pages_addr); 284 kfree(rdev->gart.ttm_alloced); 285 rdev->gart.pages = NULL; 286 rdev->gart.pages_addr = NULL; 287 rdev->gart.ttm_alloced = NULL; 288 289 radeon_dummy_page_fini(rdev); 290 } 291