1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/vmalloc.h> 30 31 #include <drm/drm_pci.h> 32 #include <drm/radeon_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "radeon.h" 37 38 /* 39 * GART 40 * The GART (Graphics Aperture Remapping Table) is an aperture 41 * in the GPU's address space. System pages can be mapped into 42 * the aperture and look like contiguous pages from the GPU's 43 * perspective. A page table maps the pages in the aperture 44 * to the actual backing pages in system memory. 45 * 46 * Radeon GPUs support both an internal GART, as described above, 47 * and AGP. AGP works similarly, but the GART table is configured 48 * and maintained by the northbridge rather than the driver. 49 * Radeon hw has a separate AGP aperture that is programmed to 50 * point to the AGP aperture provided by the northbridge and the 51 * requests are passed through to the northbridge aperture. 52 * Both AGP and internal GART can be used at the same time, however 53 * that is not currently supported by the driver. 54 * 55 * This file handles the common internal GART management. 56 */ 57 58 /* 59 * Common GART table functions. 60 */ 61 /** 62 * radeon_gart_table_ram_alloc - allocate system ram for gart page table 63 * 64 * @rdev: radeon_device pointer 65 * 66 * Allocate system memory for GART page table 67 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 68 * gart table to be in system memory. 69 * Returns 0 for success, -ENOMEM for failure. 70 */ 71 int radeon_gart_table_ram_alloc(struct radeon_device *rdev) 72 { 73 void *ptr; 74 75 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, 76 &rdev->gart.table_addr); 77 if (ptr == NULL) { 78 return -ENOMEM; 79 } 80 #ifdef CONFIG_X86 81 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 82 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 83 set_memory_uc((unsigned long)ptr, 84 rdev->gart.table_size >> PAGE_SHIFT); 85 } 86 #endif 87 rdev->gart.ptr = ptr; 88 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); 89 return 0; 90 } 91 92 /** 93 * radeon_gart_table_ram_free - free system ram for gart page table 94 * 95 * @rdev: radeon_device pointer 96 * 97 * Free system memory for GART page table 98 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 99 * gart table to be in system memory. 100 */ 101 void radeon_gart_table_ram_free(struct radeon_device *rdev) 102 { 103 if (rdev->gart.ptr == NULL) { 104 return; 105 } 106 #ifdef CONFIG_X86 107 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || 108 rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { 109 set_memory_wb((unsigned long)rdev->gart.ptr, 110 rdev->gart.table_size >> PAGE_SHIFT); 111 } 112 #endif 113 pci_free_consistent(rdev->pdev, rdev->gart.table_size, 114 (void *)rdev->gart.ptr, 115 rdev->gart.table_addr); 116 rdev->gart.ptr = NULL; 117 rdev->gart.table_addr = 0; 118 } 119 120 /** 121 * radeon_gart_table_vram_alloc - allocate vram for gart page table 122 * 123 * @rdev: radeon_device pointer 124 * 125 * Allocate video memory for GART page table 126 * (pcie r4xx, r5xx+). These asics require the 127 * gart table to be in video memory. 128 * Returns 0 for success, error for failure. 129 */ 130 int radeon_gart_table_vram_alloc(struct radeon_device *rdev) 131 { 132 int r; 133 134 if (rdev->gart.robj == NULL) { 135 r = radeon_bo_create(rdev, rdev->gart.table_size, 136 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 137 0, NULL, NULL, &rdev->gart.robj); 138 if (r) { 139 return r; 140 } 141 } 142 return 0; 143 } 144 145 /** 146 * radeon_gart_table_vram_pin - pin gart page table in vram 147 * 148 * @rdev: radeon_device pointer 149 * 150 * Pin the GART page table in vram so it will not be moved 151 * by the memory manager (pcie r4xx, r5xx+). These asics require the 152 * gart table to be in video memory. 153 * Returns 0 for success, error for failure. 154 */ 155 int radeon_gart_table_vram_pin(struct radeon_device *rdev) 156 { 157 uint64_t gpu_addr; 158 int r; 159 160 r = radeon_bo_reserve(rdev->gart.robj, false); 161 if (unlikely(r != 0)) 162 return r; 163 r = radeon_bo_pin(rdev->gart.robj, 164 RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 165 if (r) { 166 radeon_bo_unreserve(rdev->gart.robj); 167 return r; 168 } 169 r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr); 170 if (r) 171 radeon_bo_unpin(rdev->gart.robj); 172 radeon_bo_unreserve(rdev->gart.robj); 173 rdev->gart.table_addr = gpu_addr; 174 175 if (!r) { 176 int i; 177 178 /* We might have dropped some GART table updates while it wasn't 179 * mapped, restore all entries 180 */ 181 for (i = 0; i < rdev->gart.num_gpu_pages; i++) 182 radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]); 183 mb(); 184 radeon_gart_tlb_flush(rdev); 185 } 186 187 return r; 188 } 189 190 /** 191 * radeon_gart_table_vram_unpin - unpin gart page table in vram 192 * 193 * @rdev: radeon_device pointer 194 * 195 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 196 * These asics require the gart table to be in video memory. 197 */ 198 void radeon_gart_table_vram_unpin(struct radeon_device *rdev) 199 { 200 int r; 201 202 if (rdev->gart.robj == NULL) { 203 return; 204 } 205 r = radeon_bo_reserve(rdev->gart.robj, false); 206 if (likely(r == 0)) { 207 radeon_bo_kunmap(rdev->gart.robj); 208 radeon_bo_unpin(rdev->gart.robj); 209 radeon_bo_unreserve(rdev->gart.robj); 210 rdev->gart.ptr = NULL; 211 } 212 } 213 214 /** 215 * radeon_gart_table_vram_free - free gart page table vram 216 * 217 * @rdev: radeon_device pointer 218 * 219 * Free the video memory used for the GART page table 220 * (pcie r4xx, r5xx+). These asics require the gart table to 221 * be in video memory. 222 */ 223 void radeon_gart_table_vram_free(struct radeon_device *rdev) 224 { 225 if (rdev->gart.robj == NULL) { 226 return; 227 } 228 radeon_bo_unref(&rdev->gart.robj); 229 } 230 231 /* 232 * Common gart functions. 233 */ 234 /** 235 * radeon_gart_unbind - unbind pages from the gart page table 236 * 237 * @rdev: radeon_device pointer 238 * @offset: offset into the GPU's gart aperture 239 * @pages: number of pages to unbind 240 * 241 * Unbinds the requested pages from the gart page table and 242 * replaces them with the dummy page (all asics). 243 */ 244 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 245 int pages) 246 { 247 unsigned t; 248 unsigned p; 249 int i, j; 250 251 if (!rdev->gart.ready) { 252 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 253 return; 254 } 255 t = offset / RADEON_GPU_PAGE_SIZE; 256 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 257 for (i = 0; i < pages; i++, p++) { 258 if (rdev->gart.pages[p]) { 259 rdev->gart.pages[p] = NULL; 260 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 261 rdev->gart.pages_entry[t] = rdev->dummy_page.entry; 262 if (rdev->gart.ptr) { 263 radeon_gart_set_page(rdev, t, 264 rdev->dummy_page.entry); 265 } 266 } 267 } 268 } 269 if (rdev->gart.ptr) { 270 mb(); 271 radeon_gart_tlb_flush(rdev); 272 } 273 } 274 275 /** 276 * radeon_gart_bind - bind pages into the gart page table 277 * 278 * @rdev: radeon_device pointer 279 * @offset: offset into the GPU's gart aperture 280 * @pages: number of pages to bind 281 * @pagelist: pages to bind 282 * @dma_addr: DMA addresses of pages 283 * @flags: RADEON_GART_PAGE_* flags 284 * 285 * Binds the requested pages to the gart page table 286 * (all asics). 287 * Returns 0 for success, -EINVAL for failure. 288 */ 289 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 290 int pages, struct page **pagelist, dma_addr_t *dma_addr, 291 uint32_t flags) 292 { 293 unsigned t; 294 unsigned p; 295 uint64_t page_base, page_entry; 296 int i, j; 297 298 if (!rdev->gart.ready) { 299 WARN(1, "trying to bind memory to uninitialized GART !\n"); 300 return -EINVAL; 301 } 302 t = offset / RADEON_GPU_PAGE_SIZE; 303 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 304 305 for (i = 0; i < pages; i++, p++) { 306 rdev->gart.pages[p] = pagelist[i]; 307 page_base = dma_addr[i]; 308 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { 309 page_entry = radeon_gart_get_page_entry(page_base, flags); 310 rdev->gart.pages_entry[t] = page_entry; 311 if (rdev->gart.ptr) { 312 radeon_gart_set_page(rdev, t, page_entry); 313 } 314 page_base += RADEON_GPU_PAGE_SIZE; 315 } 316 } 317 if (rdev->gart.ptr) { 318 mb(); 319 radeon_gart_tlb_flush(rdev); 320 } 321 return 0; 322 } 323 324 /** 325 * radeon_gart_init - init the driver info for managing the gart 326 * 327 * @rdev: radeon_device pointer 328 * 329 * Allocate the dummy page and init the gart driver info (all asics). 330 * Returns 0 for success, error for failure. 331 */ 332 int radeon_gart_init(struct radeon_device *rdev) 333 { 334 int r, i; 335 336 if (rdev->gart.pages) { 337 return 0; 338 } 339 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ 340 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { 341 DRM_ERROR("Page size is smaller than GPU page size!\n"); 342 return -EINVAL; 343 } 344 r = radeon_dummy_page_init(rdev); 345 if (r) 346 return r; 347 /* Compute table size */ 348 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; 349 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE; 350 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 351 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 352 /* Allocate pages table */ 353 rdev->gart.pages = vzalloc(array_size(sizeof(void *), 354 rdev->gart.num_cpu_pages)); 355 if (rdev->gart.pages == NULL) { 356 radeon_gart_fini(rdev); 357 return -ENOMEM; 358 } 359 rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t), 360 rdev->gart.num_gpu_pages)); 361 if (rdev->gart.pages_entry == NULL) { 362 radeon_gart_fini(rdev); 363 return -ENOMEM; 364 } 365 /* set GART entry to point to the dummy page by default */ 366 for (i = 0; i < rdev->gart.num_gpu_pages; i++) 367 rdev->gart.pages_entry[i] = rdev->dummy_page.entry; 368 return 0; 369 } 370 371 /** 372 * radeon_gart_fini - tear down the driver info for managing the gart 373 * 374 * @rdev: radeon_device pointer 375 * 376 * Tear down the gart driver info and free the dummy page (all asics). 377 */ 378 void radeon_gart_fini(struct radeon_device *rdev) 379 { 380 if (rdev->gart.ready) { 381 /* unbind pages */ 382 radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); 383 } 384 rdev->gart.ready = false; 385 vfree(rdev->gart.pages); 386 vfree(rdev->gart.pages_entry); 387 rdev->gart.pages = NULL; 388 rdev->gart.pages_entry = NULL; 389 390 radeon_dummy_page_fini(rdev); 391 } 392