1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include "drm_crtc_helper.h" 42 /* 43 * KMS wrapper. 44 * - 2.0.0 - initial interface 45 * - 2.1.0 - add square tiling interface 46 * - 2.2.0 - add r6xx/r7xx const buffer support 47 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 48 * - 2.4.0 - add crtc id query 49 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 50 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 51 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 52 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 53 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 54 * 2.10.0 - fusion 2D tiling 55 * 2.11.0 - backend map, initial compute support for the CS checker 56 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 57 * 2.13.0 - virtual memory support, streamout 58 * 2.14.0 - add evergreen tiling informations 59 * 2.15.0 - add max_pipes query 60 * 2.16.0 - fix evergreen 2D tiled surface calculation 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 62 * 2.18.0 - r600-eg: allow "invalid" DB formats 63 * 2.19.0 - r600-eg: MSAA textures 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 65 * 2.21.0 - r600-r700: FMASK and CMASK 66 * 2.22.0 - r600 only: RESOLVE_BOX allowed 67 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 68 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 69 * 2.25.0 - eg+: new info request for num SE and num SH 70 * 2.26.0 - r600-eg: fix htile size computation 71 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 72 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 73 * 2.29.0 - R500 FP16 color clear registers 74 * 2.30.0 - fix for FMASK texturing 75 * 2.31.0 - Add fastfb support for rs690 76 * 2.32.0 - new info request for rings working 77 * 2.33.0 - Add SI tiling mode array query 78 * 2.34.0 - Add CIK tiling mode array query 79 * 2.35.0 - Add CIK macrotile mode array query 80 */ 81 #define KMS_DRIVER_MAJOR 2 82 #define KMS_DRIVER_MINOR 35 83 #define KMS_DRIVER_PATCHLEVEL 0 84 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 85 int radeon_driver_unload_kms(struct drm_device *dev); 86 void radeon_driver_lastclose_kms(struct drm_device *dev); 87 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 88 void radeon_driver_postclose_kms(struct drm_device *dev, 89 struct drm_file *file_priv); 90 void radeon_driver_preclose_kms(struct drm_device *dev, 91 struct drm_file *file_priv); 92 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 93 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 94 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); 95 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 96 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 97 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 98 int *max_error, 99 struct timeval *vblank_time, 100 unsigned flags); 101 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 102 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 103 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 104 irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS); 105 void radeon_gem_object_free(struct drm_gem_object *obj); 106 int radeon_gem_object_open(struct drm_gem_object *obj, 107 struct drm_file *file_priv); 108 void radeon_gem_object_close(struct drm_gem_object *obj, 109 struct drm_file *file_priv); 110 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 111 int *vpos, int *hpos, ktime_t *stime, 112 ktime_t *etime); 113 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 114 extern int radeon_max_kms_ioctl; 115 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 116 int radeon_mode_dumb_mmap(struct drm_file *filp, 117 struct drm_device *dev, 118 uint32_t handle, uint64_t *offset_p); 119 int radeon_mode_dumb_create(struct drm_file *file_priv, 120 struct drm_device *dev, 121 struct drm_mode_create_dumb *args); 122 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 123 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 124 size_t size, 125 struct sg_table *sg); 126 int radeon_gem_prime_pin(struct drm_gem_object *obj); 127 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 128 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 129 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 130 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 131 unsigned long arg); 132 133 #if defined(CONFIG_DEBUG_FS) 134 int radeon_debugfs_init(struct drm_minor *minor); 135 void radeon_debugfs_cleanup(struct drm_minor *minor); 136 #endif 137 138 /* atpx handler */ 139 #if defined(CONFIG_VGA_SWITCHEROO) 140 void radeon_register_atpx_handler(void); 141 void radeon_unregister_atpx_handler(void); 142 bool radeon_is_px(void); 143 #else 144 static inline void radeon_register_atpx_handler(void) {} 145 static inline void radeon_unregister_atpx_handler(void) {} 146 static inline bool radeon_is_px(void) { return false; } 147 #endif 148 149 int radeon_no_wb; 150 int radeon_modeset = -1; 151 int radeon_dynclks = -1; 152 int radeon_r4xx_atom = 0; 153 int radeon_agpmode = 0; 154 int radeon_vram_limit = 0; 155 int radeon_gart_size = -1; /* auto */ 156 int radeon_benchmarking = 0; 157 int radeon_testing = 0; 158 int radeon_connector_table = 0; 159 int radeon_tv = 1; 160 int radeon_audio = -1; 161 int radeon_disp_priority = 0; 162 int radeon_hw_i2c = 0; 163 int radeon_pcie_gen2 = -1; 164 int radeon_msi = -1; 165 int radeon_lockup_timeout = 10000; 166 int radeon_fastfb = 0; 167 int radeon_dpm = -1; 168 int radeon_aspm = -1; 169 int radeon_runtime_pm = -1; 170 171 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 172 module_param_named(no_wb, radeon_no_wb, int, 0444); 173 174 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 175 module_param_named(modeset, radeon_modeset, int, 0400); 176 177 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 178 module_param_named(dynclks, radeon_dynclks, int, 0444); 179 180 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 181 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 182 183 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); 184 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 185 186 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 187 module_param_named(agpmode, radeon_agpmode, int, 0444); 188 189 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 190 module_param_named(gartsize, radeon_gart_size, int, 0600); 191 192 MODULE_PARM_DESC(benchmark, "Run benchmark"); 193 module_param_named(benchmark, radeon_benchmarking, int, 0444); 194 195 MODULE_PARM_DESC(test, "Run tests"); 196 module_param_named(test, radeon_testing, int, 0444); 197 198 MODULE_PARM_DESC(connector_table, "Force connector table"); 199 module_param_named(connector_table, radeon_connector_table, int, 0444); 200 201 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 202 module_param_named(tv, radeon_tv, int, 0444); 203 204 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 205 module_param_named(audio, radeon_audio, int, 0444); 206 207 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 208 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 209 210 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 211 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 212 213 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 214 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 215 216 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 217 module_param_named(msi, radeon_msi, int, 0444); 218 219 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 220 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 221 222 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 223 module_param_named(fastfb, radeon_fastfb, int, 0444); 224 225 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 226 module_param_named(dpm, radeon_dpm, int, 0444); 227 228 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 229 module_param_named(aspm, radeon_aspm, int, 0444); 230 231 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 232 module_param_named(runpm, radeon_runtime_pm, int, 0444); 233 234 static struct pci_device_id pciidlist[] = { 235 radeon_PCI_IDS 236 }; 237 238 MODULE_DEVICE_TABLE(pci, pciidlist); 239 240 #ifdef CONFIG_DRM_RADEON_UMS 241 242 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 243 { 244 drm_radeon_private_t *dev_priv = dev->dev_private; 245 246 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 247 return 0; 248 249 /* Disable *all* interrupts */ 250 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 251 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 252 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 253 return 0; 254 } 255 256 static int radeon_resume(struct drm_device *dev) 257 { 258 drm_radeon_private_t *dev_priv = dev->dev_private; 259 260 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 261 return 0; 262 263 /* Restore interrupt registers */ 264 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 265 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 266 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 267 return 0; 268 } 269 270 271 static const struct file_operations radeon_driver_old_fops = { 272 .owner = THIS_MODULE, 273 .open = drm_open, 274 .release = drm_release, 275 .unlocked_ioctl = drm_ioctl, 276 .mmap = drm_mmap, 277 .poll = drm_poll, 278 .read = drm_read, 279 #ifdef CONFIG_COMPAT 280 .compat_ioctl = radeon_compat_ioctl, 281 #endif 282 .llseek = noop_llseek, 283 }; 284 285 static struct drm_driver driver_old = { 286 .driver_features = 287 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 288 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 289 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 290 .load = radeon_driver_load, 291 .firstopen = radeon_driver_firstopen, 292 .open = radeon_driver_open, 293 .preclose = radeon_driver_preclose, 294 .postclose = radeon_driver_postclose, 295 .lastclose = radeon_driver_lastclose, 296 .unload = radeon_driver_unload, 297 .suspend = radeon_suspend, 298 .resume = radeon_resume, 299 .get_vblank_counter = radeon_get_vblank_counter, 300 .enable_vblank = radeon_enable_vblank, 301 .disable_vblank = radeon_disable_vblank, 302 .master_create = radeon_master_create, 303 .master_destroy = radeon_master_destroy, 304 .irq_preinstall = radeon_driver_irq_preinstall, 305 .irq_postinstall = radeon_driver_irq_postinstall, 306 .irq_uninstall = radeon_driver_irq_uninstall, 307 .irq_handler = radeon_driver_irq_handler, 308 .ioctls = radeon_ioctls, 309 .dma_ioctl = radeon_cp_buffers, 310 .fops = &radeon_driver_old_fops, 311 .name = DRIVER_NAME, 312 .desc = DRIVER_DESC, 313 .date = DRIVER_DATE, 314 .major = DRIVER_MAJOR, 315 .minor = DRIVER_MINOR, 316 .patchlevel = DRIVER_PATCHLEVEL, 317 }; 318 319 #endif 320 321 static struct drm_driver kms_driver; 322 323 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 324 { 325 struct apertures_struct *ap; 326 bool primary = false; 327 328 ap = alloc_apertures(1); 329 if (!ap) 330 return -ENOMEM; 331 332 ap->ranges[0].base = pci_resource_start(pdev, 0); 333 ap->ranges[0].size = pci_resource_len(pdev, 0); 334 335 #ifdef CONFIG_X86 336 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 337 #endif 338 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 339 kfree(ap); 340 341 return 0; 342 } 343 344 static int radeon_pci_probe(struct pci_dev *pdev, 345 const struct pci_device_id *ent) 346 { 347 int ret; 348 349 /* Get rid of things like offb */ 350 ret = radeon_kick_out_firmware_fb(pdev); 351 if (ret) 352 return ret; 353 354 return drm_get_pci_dev(pdev, ent, &kms_driver); 355 } 356 357 static void 358 radeon_pci_remove(struct pci_dev *pdev) 359 { 360 struct drm_device *dev = pci_get_drvdata(pdev); 361 362 drm_put_dev(dev); 363 } 364 365 static int radeon_pmops_suspend(struct device *dev) 366 { 367 struct pci_dev *pdev = to_pci_dev(dev); 368 struct drm_device *drm_dev = pci_get_drvdata(pdev); 369 return radeon_suspend_kms(drm_dev, true, true); 370 } 371 372 static int radeon_pmops_resume(struct device *dev) 373 { 374 struct pci_dev *pdev = to_pci_dev(dev); 375 struct drm_device *drm_dev = pci_get_drvdata(pdev); 376 return radeon_resume_kms(drm_dev, true, true); 377 } 378 379 static int radeon_pmops_freeze(struct device *dev) 380 { 381 struct pci_dev *pdev = to_pci_dev(dev); 382 struct drm_device *drm_dev = pci_get_drvdata(pdev); 383 return radeon_suspend_kms(drm_dev, false, true); 384 } 385 386 static int radeon_pmops_thaw(struct device *dev) 387 { 388 struct pci_dev *pdev = to_pci_dev(dev); 389 struct drm_device *drm_dev = pci_get_drvdata(pdev); 390 return radeon_resume_kms(drm_dev, false, true); 391 } 392 393 static int radeon_pmops_runtime_suspend(struct device *dev) 394 { 395 struct pci_dev *pdev = to_pci_dev(dev); 396 struct drm_device *drm_dev = pci_get_drvdata(pdev); 397 int ret; 398 399 if (radeon_runtime_pm == 0) 400 return -EINVAL; 401 402 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 403 drm_kms_helper_poll_disable(drm_dev); 404 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 405 406 ret = radeon_suspend_kms(drm_dev, false, false); 407 pci_save_state(pdev); 408 pci_disable_device(pdev); 409 pci_set_power_state(pdev, PCI_D3cold); 410 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 411 412 return 0; 413 } 414 415 static int radeon_pmops_runtime_resume(struct device *dev) 416 { 417 struct pci_dev *pdev = to_pci_dev(dev); 418 struct drm_device *drm_dev = pci_get_drvdata(pdev); 419 int ret; 420 421 if (radeon_runtime_pm == 0) 422 return -EINVAL; 423 424 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 425 426 pci_set_power_state(pdev, PCI_D0); 427 pci_restore_state(pdev); 428 ret = pci_enable_device(pdev); 429 if (ret) 430 return ret; 431 pci_set_master(pdev); 432 433 ret = radeon_resume_kms(drm_dev, false, false); 434 drm_kms_helper_poll_enable(drm_dev); 435 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 436 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 437 return 0; 438 } 439 440 static int radeon_pmops_runtime_idle(struct device *dev) 441 { 442 struct pci_dev *pdev = to_pci_dev(dev); 443 struct drm_device *drm_dev = pci_get_drvdata(pdev); 444 struct drm_crtc *crtc; 445 446 if (radeon_runtime_pm == 0) 447 return -EBUSY; 448 449 /* are we PX enabled? */ 450 if (radeon_runtime_pm == -1 && !radeon_is_px()) { 451 DRM_DEBUG_DRIVER("failing to power off - not px\n"); 452 return -EBUSY; 453 } 454 455 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 456 if (crtc->enabled) { 457 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 458 return -EBUSY; 459 } 460 } 461 462 pm_runtime_mark_last_busy(dev); 463 pm_runtime_autosuspend(dev); 464 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 465 return 1; 466 } 467 468 long radeon_drm_ioctl(struct file *filp, 469 unsigned int cmd, unsigned long arg) 470 { 471 struct drm_file *file_priv = filp->private_data; 472 struct drm_device *dev; 473 long ret; 474 dev = file_priv->minor->dev; 475 ret = pm_runtime_get_sync(dev->dev); 476 if (ret < 0) 477 return ret; 478 479 ret = drm_ioctl(filp, cmd, arg); 480 481 pm_runtime_mark_last_busy(dev->dev); 482 pm_runtime_put_autosuspend(dev->dev); 483 return ret; 484 } 485 486 static const struct dev_pm_ops radeon_pm_ops = { 487 .suspend = radeon_pmops_suspend, 488 .resume = radeon_pmops_resume, 489 .freeze = radeon_pmops_freeze, 490 .thaw = radeon_pmops_thaw, 491 .poweroff = radeon_pmops_freeze, 492 .restore = radeon_pmops_resume, 493 .runtime_suspend = radeon_pmops_runtime_suspend, 494 .runtime_resume = radeon_pmops_runtime_resume, 495 .runtime_idle = radeon_pmops_runtime_idle, 496 }; 497 498 static const struct file_operations radeon_driver_kms_fops = { 499 .owner = THIS_MODULE, 500 .open = drm_open, 501 .release = drm_release, 502 .unlocked_ioctl = radeon_drm_ioctl, 503 .mmap = radeon_mmap, 504 .poll = drm_poll, 505 .read = drm_read, 506 #ifdef CONFIG_COMPAT 507 .compat_ioctl = radeon_kms_compat_ioctl, 508 #endif 509 }; 510 511 static struct drm_driver kms_driver = { 512 .driver_features = 513 DRIVER_USE_AGP | 514 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 515 DRIVER_PRIME | DRIVER_RENDER, 516 .dev_priv_size = 0, 517 .load = radeon_driver_load_kms, 518 .open = radeon_driver_open_kms, 519 .preclose = radeon_driver_preclose_kms, 520 .postclose = radeon_driver_postclose_kms, 521 .lastclose = radeon_driver_lastclose_kms, 522 .unload = radeon_driver_unload_kms, 523 .get_vblank_counter = radeon_get_vblank_counter_kms, 524 .enable_vblank = radeon_enable_vblank_kms, 525 .disable_vblank = radeon_disable_vblank_kms, 526 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 527 .get_scanout_position = radeon_get_crtc_scanoutpos, 528 #if defined(CONFIG_DEBUG_FS) 529 .debugfs_init = radeon_debugfs_init, 530 .debugfs_cleanup = radeon_debugfs_cleanup, 531 #endif 532 .irq_preinstall = radeon_driver_irq_preinstall_kms, 533 .irq_postinstall = radeon_driver_irq_postinstall_kms, 534 .irq_uninstall = radeon_driver_irq_uninstall_kms, 535 .irq_handler = radeon_driver_irq_handler_kms, 536 .ioctls = radeon_ioctls_kms, 537 .gem_free_object = radeon_gem_object_free, 538 .gem_open_object = radeon_gem_object_open, 539 .gem_close_object = radeon_gem_object_close, 540 .dumb_create = radeon_mode_dumb_create, 541 .dumb_map_offset = radeon_mode_dumb_mmap, 542 .dumb_destroy = drm_gem_dumb_destroy, 543 .fops = &radeon_driver_kms_fops, 544 545 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 546 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 547 .gem_prime_export = drm_gem_prime_export, 548 .gem_prime_import = drm_gem_prime_import, 549 .gem_prime_pin = radeon_gem_prime_pin, 550 .gem_prime_unpin = radeon_gem_prime_unpin, 551 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 552 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 553 .gem_prime_vmap = radeon_gem_prime_vmap, 554 .gem_prime_vunmap = radeon_gem_prime_vunmap, 555 556 .name = DRIVER_NAME, 557 .desc = DRIVER_DESC, 558 .date = DRIVER_DATE, 559 .major = KMS_DRIVER_MAJOR, 560 .minor = KMS_DRIVER_MINOR, 561 .patchlevel = KMS_DRIVER_PATCHLEVEL, 562 }; 563 564 static struct drm_driver *driver; 565 static struct pci_driver *pdriver; 566 567 #ifdef CONFIG_DRM_RADEON_UMS 568 static struct pci_driver radeon_pci_driver = { 569 .name = DRIVER_NAME, 570 .id_table = pciidlist, 571 }; 572 #endif 573 574 static struct pci_driver radeon_kms_pci_driver = { 575 .name = DRIVER_NAME, 576 .id_table = pciidlist, 577 .probe = radeon_pci_probe, 578 .remove = radeon_pci_remove, 579 .driver.pm = &radeon_pm_ops, 580 }; 581 582 static int __init radeon_init(void) 583 { 584 #ifdef CONFIG_VGA_CONSOLE 585 if (vgacon_text_force() && radeon_modeset == -1) { 586 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 587 radeon_modeset = 0; 588 } 589 #endif 590 /* set to modesetting by default if not nomodeset */ 591 if (radeon_modeset == -1) 592 radeon_modeset = 1; 593 594 if (radeon_modeset == 1) { 595 DRM_INFO("radeon kernel modesetting enabled.\n"); 596 driver = &kms_driver; 597 pdriver = &radeon_kms_pci_driver; 598 driver->driver_features |= DRIVER_MODESET; 599 driver->num_ioctls = radeon_max_kms_ioctl; 600 radeon_register_atpx_handler(); 601 602 } else { 603 #ifdef CONFIG_DRM_RADEON_UMS 604 DRM_INFO("radeon userspace modesetting enabled.\n"); 605 driver = &driver_old; 606 pdriver = &radeon_pci_driver; 607 driver->driver_features &= ~DRIVER_MODESET; 608 driver->num_ioctls = radeon_max_ioctl; 609 #else 610 DRM_ERROR("No UMS support in radeon module!\n"); 611 return -EINVAL; 612 #endif 613 } 614 615 /* let modprobe override vga console setting */ 616 return drm_pci_init(driver, pdriver); 617 } 618 619 static void __exit radeon_exit(void) 620 { 621 drm_pci_exit(driver, pdriver); 622 radeon_unregister_atpx_handler(); 623 } 624 625 module_init(radeon_init); 626 module_exit(radeon_exit); 627 628 MODULE_AUTHOR(DRIVER_AUTHOR); 629 MODULE_DESCRIPTION(DRIVER_DESC); 630 MODULE_LICENSE("GPL and additional rights"); 631