1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/compat.h> 42 #include <drm/drm_gem.h> 43 #include <drm/drm_fb_helper.h> 44 45 #include <drm/drm_crtc_helper.h> 46 #include "radeon_kfd.h" 47 48 /* 49 * KMS wrapper. 50 * - 2.0.0 - initial interface 51 * - 2.1.0 - add square tiling interface 52 * - 2.2.0 - add r6xx/r7xx const buffer support 53 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 54 * - 2.4.0 - add crtc id query 55 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 56 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 57 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 58 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 59 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 60 * 2.10.0 - fusion 2D tiling 61 * 2.11.0 - backend map, initial compute support for the CS checker 62 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 63 * 2.13.0 - virtual memory support, streamout 64 * 2.14.0 - add evergreen tiling informations 65 * 2.15.0 - add max_pipes query 66 * 2.16.0 - fix evergreen 2D tiled surface calculation 67 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 68 * 2.18.0 - r600-eg: allow "invalid" DB formats 69 * 2.19.0 - r600-eg: MSAA textures 70 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 71 * 2.21.0 - r600-r700: FMASK and CMASK 72 * 2.22.0 - r600 only: RESOLVE_BOX allowed 73 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 74 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 75 * 2.25.0 - eg+: new info request for num SE and num SH 76 * 2.26.0 - r600-eg: fix htile size computation 77 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 78 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 79 * 2.29.0 - R500 FP16 color clear registers 80 * 2.30.0 - fix for FMASK texturing 81 * 2.31.0 - Add fastfb support for rs690 82 * 2.32.0 - new info request for rings working 83 * 2.33.0 - Add SI tiling mode array query 84 * 2.34.0 - Add CIK tiling mode array query 85 * 2.35.0 - Add CIK macrotile mode array query 86 * 2.36.0 - Fix CIK DCE tiling setup 87 * 2.37.0 - allow GS ring setup on r6xx/r7xx 88 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 89 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 90 * 2.39.0 - Add INFO query for number of active CUs 91 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 92 * CS to GPU on >= r600 93 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 94 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 95 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 96 * 2.44.0 - SET_APPEND_CNT packet3 support 97 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 98 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 99 * 2.47.0 - Add UVD_NO_OP register support 100 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 101 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 102 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 103 */ 104 #define KMS_DRIVER_MAJOR 2 105 #define KMS_DRIVER_MINOR 50 106 #define KMS_DRIVER_PATCHLEVEL 0 107 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 108 void radeon_driver_unload_kms(struct drm_device *dev); 109 void radeon_driver_lastclose_kms(struct drm_device *dev); 110 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 111 void radeon_driver_postclose_kms(struct drm_device *dev, 112 struct drm_file *file_priv); 113 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 114 bool fbcon, bool freeze); 115 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 116 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 117 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 118 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 119 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 120 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 121 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 122 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 123 void radeon_gem_object_free(struct drm_gem_object *obj); 124 int radeon_gem_object_open(struct drm_gem_object *obj, 125 struct drm_file *file_priv); 126 void radeon_gem_object_close(struct drm_gem_object *obj, 127 struct drm_file *file_priv); 128 struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, 129 struct drm_gem_object *gobj, 130 int flags); 131 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 132 unsigned int flags, int *vpos, int *hpos, 133 ktime_t *stime, ktime_t *etime, 134 const struct drm_display_mode *mode); 135 extern bool radeon_is_px(struct drm_device *dev); 136 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 137 extern int radeon_max_kms_ioctl; 138 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 139 int radeon_mode_dumb_mmap(struct drm_file *filp, 140 struct drm_device *dev, 141 uint32_t handle, uint64_t *offset_p); 142 int radeon_mode_dumb_create(struct drm_file *file_priv, 143 struct drm_device *dev, 144 struct drm_mode_create_dumb *args); 145 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 146 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 147 struct dma_buf_attachment *, 148 struct sg_table *sg); 149 int radeon_gem_prime_pin(struct drm_gem_object *obj); 150 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 151 struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *); 152 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 153 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 154 155 /* atpx handler */ 156 #if defined(CONFIG_VGA_SWITCHEROO) 157 void radeon_register_atpx_handler(void); 158 void radeon_unregister_atpx_handler(void); 159 bool radeon_has_atpx_dgpu_power_cntl(void); 160 bool radeon_is_atpx_hybrid(void); 161 #else 162 static inline void radeon_register_atpx_handler(void) {} 163 static inline void radeon_unregister_atpx_handler(void) {} 164 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 165 static inline bool radeon_is_atpx_hybrid(void) { return false; } 166 #endif 167 168 int radeon_no_wb; 169 int radeon_modeset = -1; 170 int radeon_dynclks = -1; 171 int radeon_r4xx_atom = 0; 172 int radeon_agpmode = 0; 173 int radeon_vram_limit = 0; 174 int radeon_gart_size = -1; /* auto */ 175 int radeon_benchmarking = 0; 176 int radeon_testing = 0; 177 int radeon_connector_table = 0; 178 int radeon_tv = 1; 179 int radeon_audio = -1; 180 int radeon_disp_priority = 0; 181 int radeon_hw_i2c = 0; 182 int radeon_pcie_gen2 = -1; 183 int radeon_msi = -1; 184 int radeon_lockup_timeout = 10000; 185 int radeon_fastfb = 0; 186 int radeon_dpm = -1; 187 int radeon_aspm = -1; 188 int radeon_runtime_pm = -1; 189 int radeon_hard_reset = 0; 190 int radeon_vm_size = 8; 191 int radeon_vm_block_size = -1; 192 int radeon_deep_color = 0; 193 int radeon_use_pflipirq = 2; 194 int radeon_bapm = -1; 195 int radeon_backlight = -1; 196 int radeon_auxch = -1; 197 int radeon_mst = 0; 198 int radeon_uvd = 1; 199 int radeon_vce = 1; 200 201 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 202 module_param_named(no_wb, radeon_no_wb, int, 0444); 203 204 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 205 module_param_named(modeset, radeon_modeset, int, 0400); 206 207 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 208 module_param_named(dynclks, radeon_dynclks, int, 0444); 209 210 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 211 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 212 213 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 214 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 215 216 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 217 module_param_named(agpmode, radeon_agpmode, int, 0444); 218 219 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 220 module_param_named(gartsize, radeon_gart_size, int, 0600); 221 222 MODULE_PARM_DESC(benchmark, "Run benchmark"); 223 module_param_named(benchmark, radeon_benchmarking, int, 0444); 224 225 MODULE_PARM_DESC(test, "Run tests"); 226 module_param_named(test, radeon_testing, int, 0444); 227 228 MODULE_PARM_DESC(connector_table, "Force connector table"); 229 module_param_named(connector_table, radeon_connector_table, int, 0444); 230 231 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 232 module_param_named(tv, radeon_tv, int, 0444); 233 234 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 235 module_param_named(audio, radeon_audio, int, 0444); 236 237 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 238 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 239 240 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 241 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 242 243 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 244 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 245 246 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 247 module_param_named(msi, radeon_msi, int, 0444); 248 249 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 250 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 251 252 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 253 module_param_named(fastfb, radeon_fastfb, int, 0444); 254 255 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 256 module_param_named(dpm, radeon_dpm, int, 0444); 257 258 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 259 module_param_named(aspm, radeon_aspm, int, 0444); 260 261 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 262 module_param_named(runpm, radeon_runtime_pm, int, 0444); 263 264 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 265 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 266 267 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 268 module_param_named(vm_size, radeon_vm_size, int, 0444); 269 270 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 271 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 272 273 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 274 module_param_named(deep_color, radeon_deep_color, int, 0444); 275 276 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 277 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 278 279 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 280 module_param_named(bapm, radeon_bapm, int, 0444); 281 282 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 283 module_param_named(backlight, radeon_backlight, int, 0444); 284 285 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 286 module_param_named(auxch, radeon_auxch, int, 0444); 287 288 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 289 module_param_named(mst, radeon_mst, int, 0444); 290 291 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 292 module_param_named(uvd, radeon_uvd, int, 0444); 293 294 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 295 module_param_named(vce, radeon_vce, int, 0444); 296 297 int radeon_si_support = 1; 298 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 299 module_param_named(si_support, radeon_si_support, int, 0444); 300 301 int radeon_cik_support = 1; 302 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 303 module_param_named(cik_support, radeon_cik_support, int, 0444); 304 305 static struct pci_device_id pciidlist[] = { 306 radeon_PCI_IDS 307 }; 308 309 MODULE_DEVICE_TABLE(pci, pciidlist); 310 311 static struct drm_driver kms_driver; 312 313 bool radeon_device_is_virtual(void); 314 315 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 316 { 317 struct apertures_struct *ap; 318 bool primary = false; 319 320 ap = alloc_apertures(1); 321 if (!ap) 322 return -ENOMEM; 323 324 ap->ranges[0].base = pci_resource_start(pdev, 0); 325 ap->ranges[0].size = pci_resource_len(pdev, 0); 326 327 #ifdef CONFIG_X86 328 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 329 #endif 330 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 331 kfree(ap); 332 333 return 0; 334 } 335 336 static int radeon_pci_probe(struct pci_dev *pdev, 337 const struct pci_device_id *ent) 338 { 339 int ret; 340 341 /* 342 * Initialize amdkfd before starting radeon. If it was not loaded yet, 343 * defer radeon probing 344 */ 345 ret = radeon_kfd_init(); 346 if (ret == -EPROBE_DEFER) 347 return ret; 348 349 if (vga_switcheroo_client_probe_defer(pdev)) 350 return -EPROBE_DEFER; 351 352 /* Get rid of things like offb */ 353 ret = radeon_kick_out_firmware_fb(pdev); 354 if (ret) 355 return ret; 356 357 return drm_get_pci_dev(pdev, ent, &kms_driver); 358 } 359 360 static void 361 radeon_pci_remove(struct pci_dev *pdev) 362 { 363 struct drm_device *dev = pci_get_drvdata(pdev); 364 365 drm_put_dev(dev); 366 } 367 368 static void 369 radeon_pci_shutdown(struct pci_dev *pdev) 370 { 371 /* if we are running in a VM, make sure the device 372 * torn down properly on reboot/shutdown 373 */ 374 if (radeon_device_is_virtual()) 375 radeon_pci_remove(pdev); 376 } 377 378 static int radeon_pmops_suspend(struct device *dev) 379 { 380 struct pci_dev *pdev = to_pci_dev(dev); 381 struct drm_device *drm_dev = pci_get_drvdata(pdev); 382 return radeon_suspend_kms(drm_dev, true, true, false); 383 } 384 385 static int radeon_pmops_resume(struct device *dev) 386 { 387 struct pci_dev *pdev = to_pci_dev(dev); 388 struct drm_device *drm_dev = pci_get_drvdata(pdev); 389 390 /* GPU comes up enabled by the bios on resume */ 391 if (radeon_is_px(drm_dev)) { 392 pm_runtime_disable(dev); 393 pm_runtime_set_active(dev); 394 pm_runtime_enable(dev); 395 } 396 397 return radeon_resume_kms(drm_dev, true, true); 398 } 399 400 static int radeon_pmops_freeze(struct device *dev) 401 { 402 struct pci_dev *pdev = to_pci_dev(dev); 403 struct drm_device *drm_dev = pci_get_drvdata(pdev); 404 return radeon_suspend_kms(drm_dev, false, true, true); 405 } 406 407 static int radeon_pmops_thaw(struct device *dev) 408 { 409 struct pci_dev *pdev = to_pci_dev(dev); 410 struct drm_device *drm_dev = pci_get_drvdata(pdev); 411 return radeon_resume_kms(drm_dev, false, true); 412 } 413 414 static int radeon_pmops_runtime_suspend(struct device *dev) 415 { 416 struct pci_dev *pdev = to_pci_dev(dev); 417 struct drm_device *drm_dev = pci_get_drvdata(pdev); 418 int ret; 419 420 if (!radeon_is_px(drm_dev)) { 421 pm_runtime_forbid(dev); 422 return -EBUSY; 423 } 424 425 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 426 drm_kms_helper_poll_disable(drm_dev); 427 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 428 429 ret = radeon_suspend_kms(drm_dev, false, false, false); 430 pci_save_state(pdev); 431 pci_disable_device(pdev); 432 pci_ignore_hotplug(pdev); 433 if (radeon_is_atpx_hybrid()) 434 pci_set_power_state(pdev, PCI_D3cold); 435 else if (!radeon_has_atpx_dgpu_power_cntl()) 436 pci_set_power_state(pdev, PCI_D3hot); 437 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 438 439 return 0; 440 } 441 442 static int radeon_pmops_runtime_resume(struct device *dev) 443 { 444 struct pci_dev *pdev = to_pci_dev(dev); 445 struct drm_device *drm_dev = pci_get_drvdata(pdev); 446 int ret; 447 448 if (!radeon_is_px(drm_dev)) 449 return -EINVAL; 450 451 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 452 453 if (radeon_is_atpx_hybrid() || 454 !radeon_has_atpx_dgpu_power_cntl()) 455 pci_set_power_state(pdev, PCI_D0); 456 pci_restore_state(pdev); 457 ret = pci_enable_device(pdev); 458 if (ret) 459 return ret; 460 pci_set_master(pdev); 461 462 ret = radeon_resume_kms(drm_dev, false, false); 463 drm_kms_helper_poll_enable(drm_dev); 464 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 465 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 466 return 0; 467 } 468 469 static int radeon_pmops_runtime_idle(struct device *dev) 470 { 471 struct pci_dev *pdev = to_pci_dev(dev); 472 struct drm_device *drm_dev = pci_get_drvdata(pdev); 473 struct drm_crtc *crtc; 474 475 if (!radeon_is_px(drm_dev)) { 476 pm_runtime_forbid(dev); 477 return -EBUSY; 478 } 479 480 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 481 if (crtc->enabled) { 482 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 483 return -EBUSY; 484 } 485 } 486 487 pm_runtime_mark_last_busy(dev); 488 pm_runtime_autosuspend(dev); 489 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 490 return 1; 491 } 492 493 long radeon_drm_ioctl(struct file *filp, 494 unsigned int cmd, unsigned long arg) 495 { 496 struct drm_file *file_priv = filp->private_data; 497 struct drm_device *dev; 498 long ret; 499 dev = file_priv->minor->dev; 500 ret = pm_runtime_get_sync(dev->dev); 501 if (ret < 0) 502 return ret; 503 504 ret = drm_ioctl(filp, cmd, arg); 505 506 pm_runtime_mark_last_busy(dev->dev); 507 pm_runtime_put_autosuspend(dev->dev); 508 return ret; 509 } 510 511 #ifdef CONFIG_COMPAT 512 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 513 { 514 unsigned int nr = DRM_IOCTL_NR(cmd); 515 int ret; 516 517 if (nr < DRM_COMMAND_BASE) 518 return drm_compat_ioctl(filp, cmd, arg); 519 520 ret = radeon_drm_ioctl(filp, cmd, arg); 521 522 return ret; 523 } 524 #endif 525 526 static const struct dev_pm_ops radeon_pm_ops = { 527 .suspend = radeon_pmops_suspend, 528 .resume = radeon_pmops_resume, 529 .freeze = radeon_pmops_freeze, 530 .thaw = radeon_pmops_thaw, 531 .poweroff = radeon_pmops_freeze, 532 .restore = radeon_pmops_resume, 533 .runtime_suspend = radeon_pmops_runtime_suspend, 534 .runtime_resume = radeon_pmops_runtime_resume, 535 .runtime_idle = radeon_pmops_runtime_idle, 536 }; 537 538 static const struct file_operations radeon_driver_kms_fops = { 539 .owner = THIS_MODULE, 540 .open = drm_open, 541 .release = drm_release, 542 .unlocked_ioctl = radeon_drm_ioctl, 543 .mmap = radeon_mmap, 544 .poll = drm_poll, 545 .read = drm_read, 546 #ifdef CONFIG_COMPAT 547 .compat_ioctl = radeon_kms_compat_ioctl, 548 #endif 549 }; 550 551 static bool 552 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 553 bool in_vblank_irq, int *vpos, int *hpos, 554 ktime_t *stime, ktime_t *etime, 555 const struct drm_display_mode *mode) 556 { 557 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 558 stime, etime, mode); 559 } 560 561 static struct drm_driver kms_driver = { 562 .driver_features = 563 DRIVER_USE_AGP | 564 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 565 DRIVER_PRIME | DRIVER_RENDER, 566 .load = radeon_driver_load_kms, 567 .open = radeon_driver_open_kms, 568 .postclose = radeon_driver_postclose_kms, 569 .lastclose = radeon_driver_lastclose_kms, 570 .set_busid = drm_pci_set_busid, 571 .unload = radeon_driver_unload_kms, 572 .get_vblank_counter = radeon_get_vblank_counter_kms, 573 .enable_vblank = radeon_enable_vblank_kms, 574 .disable_vblank = radeon_disable_vblank_kms, 575 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 576 .get_scanout_position = radeon_get_crtc_scanout_position, 577 .irq_preinstall = radeon_driver_irq_preinstall_kms, 578 .irq_postinstall = radeon_driver_irq_postinstall_kms, 579 .irq_uninstall = radeon_driver_irq_uninstall_kms, 580 .irq_handler = radeon_driver_irq_handler_kms, 581 .ioctls = radeon_ioctls_kms, 582 .gem_free_object_unlocked = radeon_gem_object_free, 583 .gem_open_object = radeon_gem_object_open, 584 .gem_close_object = radeon_gem_object_close, 585 .dumb_create = radeon_mode_dumb_create, 586 .dumb_map_offset = radeon_mode_dumb_mmap, 587 .dumb_destroy = drm_gem_dumb_destroy, 588 .fops = &radeon_driver_kms_fops, 589 590 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 591 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 592 .gem_prime_export = radeon_gem_prime_export, 593 .gem_prime_import = drm_gem_prime_import, 594 .gem_prime_pin = radeon_gem_prime_pin, 595 .gem_prime_unpin = radeon_gem_prime_unpin, 596 .gem_prime_res_obj = radeon_gem_prime_res_obj, 597 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 598 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 599 .gem_prime_vmap = radeon_gem_prime_vmap, 600 .gem_prime_vunmap = radeon_gem_prime_vunmap, 601 602 .name = DRIVER_NAME, 603 .desc = DRIVER_DESC, 604 .date = DRIVER_DATE, 605 .major = KMS_DRIVER_MAJOR, 606 .minor = KMS_DRIVER_MINOR, 607 .patchlevel = KMS_DRIVER_PATCHLEVEL, 608 }; 609 610 static struct drm_driver *driver; 611 static struct pci_driver *pdriver; 612 613 static struct pci_driver radeon_kms_pci_driver = { 614 .name = DRIVER_NAME, 615 .id_table = pciidlist, 616 .probe = radeon_pci_probe, 617 .remove = radeon_pci_remove, 618 .shutdown = radeon_pci_shutdown, 619 .driver.pm = &radeon_pm_ops, 620 }; 621 622 static int __init radeon_init(void) 623 { 624 if (vgacon_text_force() && radeon_modeset == -1) { 625 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 626 radeon_modeset = 0; 627 } 628 /* set to modesetting by default if not nomodeset */ 629 if (radeon_modeset == -1) 630 radeon_modeset = 1; 631 632 if (radeon_modeset == 1) { 633 DRM_INFO("radeon kernel modesetting enabled.\n"); 634 driver = &kms_driver; 635 pdriver = &radeon_kms_pci_driver; 636 driver->driver_features |= DRIVER_MODESET; 637 driver->num_ioctls = radeon_max_kms_ioctl; 638 radeon_register_atpx_handler(); 639 640 } else { 641 DRM_ERROR("No UMS support in radeon module!\n"); 642 return -EINVAL; 643 } 644 645 /* let modprobe override vga console setting */ 646 return drm_pci_init(driver, pdriver); 647 } 648 649 static void __exit radeon_exit(void) 650 { 651 radeon_kfd_fini(); 652 drm_pci_exit(driver, pdriver); 653 radeon_unregister_atpx_handler(); 654 } 655 656 module_init(radeon_init); 657 module_exit(radeon_exit); 658 659 MODULE_AUTHOR(DRIVER_AUTHOR); 660 MODULE_DESCRIPTION(DRIVER_DESC); 661 MODULE_LICENSE("GPL and additional rights"); 662