1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <drm/drmP.h> 33 #include <drm/radeon_drm.h> 34 #include "radeon_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/vga_switcheroo.h> 41 #include "drm_crtc_helper.h" 42 /* 43 * KMS wrapper. 44 * - 2.0.0 - initial interface 45 * - 2.1.0 - add square tiling interface 46 * - 2.2.0 - add r6xx/r7xx const buffer support 47 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 48 * - 2.4.0 - add crtc id query 49 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 50 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 51 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 52 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 53 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 54 * 2.10.0 - fusion 2D tiling 55 * 2.11.0 - backend map, initial compute support for the CS checker 56 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 57 * 2.13.0 - virtual memory support, streamout 58 * 2.14.0 - add evergreen tiling informations 59 * 2.15.0 - add max_pipes query 60 * 2.16.0 - fix evergreen 2D tiled surface calculation 61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 62 * 2.18.0 - r600-eg: allow "invalid" DB formats 63 * 2.19.0 - r600-eg: MSAA textures 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 65 * 2.21.0 - r600-r700: FMASK and CMASK 66 * 2.22.0 - r600 only: RESOLVE_BOX allowed 67 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 68 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 69 * 2.25.0 - eg+: new info request for num SE and num SH 70 * 2.26.0 - r600-eg: fix htile size computation 71 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 72 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 73 * 2.29.0 - R500 FP16 color clear registers 74 * 2.30.0 - fix for FMASK texturing 75 * 2.31.0 - Add fastfb support for rs690 76 * 2.32.0 - new info request for rings working 77 * 2.33.0 - Add SI tiling mode array query 78 * 2.34.0 - Add CIK tiling mode array query 79 * 2.35.0 - Add CIK macrotile mode array query 80 * 2.36.0 - Fix CIK DCE tiling setup 81 * 2.37.0 - allow GS ring setup on r6xx/r7xx 82 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 83 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 84 * 2.39.0 - Add INFO query for number of active CUs 85 */ 86 #define KMS_DRIVER_MAJOR 2 87 #define KMS_DRIVER_MINOR 39 88 #define KMS_DRIVER_PATCHLEVEL 0 89 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 90 int radeon_driver_unload_kms(struct drm_device *dev); 91 void radeon_driver_lastclose_kms(struct drm_device *dev); 92 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 93 void radeon_driver_postclose_kms(struct drm_device *dev, 94 struct drm_file *file_priv); 95 void radeon_driver_preclose_kms(struct drm_device *dev, 96 struct drm_file *file_priv); 97 int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 98 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 99 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); 100 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); 101 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); 102 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 103 int *max_error, 104 struct timeval *vblank_time, 105 unsigned flags); 106 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 107 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 108 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 109 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 110 void radeon_gem_object_free(struct drm_gem_object *obj); 111 int radeon_gem_object_open(struct drm_gem_object *obj, 112 struct drm_file *file_priv); 113 void radeon_gem_object_close(struct drm_gem_object *obj, 114 struct drm_file *file_priv); 115 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 116 unsigned int flags, 117 int *vpos, int *hpos, ktime_t *stime, 118 ktime_t *etime); 119 extern bool radeon_is_px(struct drm_device *dev); 120 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 121 extern int radeon_max_kms_ioctl; 122 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 123 int radeon_mode_dumb_mmap(struct drm_file *filp, 124 struct drm_device *dev, 125 uint32_t handle, uint64_t *offset_p); 126 int radeon_mode_dumb_create(struct drm_file *file_priv, 127 struct drm_device *dev, 128 struct drm_mode_create_dumb *args); 129 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 130 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 131 size_t size, 132 struct sg_table *sg); 133 int radeon_gem_prime_pin(struct drm_gem_object *obj); 134 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 135 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 136 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 137 extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, 138 unsigned long arg); 139 140 #if defined(CONFIG_DEBUG_FS) 141 int radeon_debugfs_init(struct drm_minor *minor); 142 void radeon_debugfs_cleanup(struct drm_minor *minor); 143 #endif 144 145 /* atpx handler */ 146 #if defined(CONFIG_VGA_SWITCHEROO) 147 void radeon_register_atpx_handler(void); 148 void radeon_unregister_atpx_handler(void); 149 #else 150 static inline void radeon_register_atpx_handler(void) {} 151 static inline void radeon_unregister_atpx_handler(void) {} 152 #endif 153 154 int radeon_no_wb; 155 int radeon_modeset = -1; 156 int radeon_dynclks = -1; 157 int radeon_r4xx_atom = 0; 158 int radeon_agpmode = 0; 159 int radeon_vram_limit = 0; 160 int radeon_gart_size = -1; /* auto */ 161 int radeon_benchmarking = 0; 162 int radeon_testing = 0; 163 int radeon_connector_table = 0; 164 int radeon_tv = 1; 165 int radeon_audio = -1; 166 int radeon_disp_priority = 0; 167 int radeon_hw_i2c = 0; 168 int radeon_pcie_gen2 = -1; 169 int radeon_msi = -1; 170 int radeon_lockup_timeout = 10000; 171 int radeon_fastfb = 0; 172 int radeon_dpm = -1; 173 int radeon_aspm = -1; 174 int radeon_runtime_pm = -1; 175 int radeon_hard_reset = 0; 176 int radeon_vm_size = 4096; 177 int radeon_vm_block_size = 9; 178 int radeon_deep_color = 0; 179 180 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 181 module_param_named(no_wb, radeon_no_wb, int, 0444); 182 183 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 184 module_param_named(modeset, radeon_modeset, int, 0400); 185 186 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 187 module_param_named(dynclks, radeon_dynclks, int, 0444); 188 189 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 190 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 191 192 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 193 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 194 195 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 196 module_param_named(agpmode, radeon_agpmode, int, 0444); 197 198 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 199 module_param_named(gartsize, radeon_gart_size, int, 0600); 200 201 MODULE_PARM_DESC(benchmark, "Run benchmark"); 202 module_param_named(benchmark, radeon_benchmarking, int, 0444); 203 204 MODULE_PARM_DESC(test, "Run tests"); 205 module_param_named(test, radeon_testing, int, 0444); 206 207 MODULE_PARM_DESC(connector_table, "Force connector table"); 208 module_param_named(connector_table, radeon_connector_table, int, 0444); 209 210 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 211 module_param_named(tv, radeon_tv, int, 0444); 212 213 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 214 module_param_named(audio, radeon_audio, int, 0444); 215 216 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 217 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 218 219 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 220 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 221 222 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 223 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 224 225 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 226 module_param_named(msi, radeon_msi, int, 0444); 227 228 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 229 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 230 231 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 232 module_param_named(fastfb, radeon_fastfb, int, 0444); 233 234 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 235 module_param_named(dpm, radeon_dpm, int, 0444); 236 237 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 238 module_param_named(aspm, radeon_aspm, int, 0444); 239 240 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 241 module_param_named(runpm, radeon_runtime_pm, int, 0444); 242 243 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 244 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 245 246 MODULE_PARM_DESC(vm_size, "VM address space size in megabytes (default 4GB)"); 247 module_param_named(vm_size, radeon_vm_size, int, 0444); 248 249 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)"); 250 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 251 252 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 253 module_param_named(deep_color, radeon_deep_color, int, 0444); 254 255 static struct pci_device_id pciidlist[] = { 256 radeon_PCI_IDS 257 }; 258 259 MODULE_DEVICE_TABLE(pci, pciidlist); 260 261 #ifdef CONFIG_DRM_RADEON_UMS 262 263 static int radeon_suspend(struct drm_device *dev, pm_message_t state) 264 { 265 drm_radeon_private_t *dev_priv = dev->dev_private; 266 267 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 268 return 0; 269 270 /* Disable *all* interrupts */ 271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 272 RADEON_WRITE(R500_DxMODE_INT_MASK, 0); 273 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 274 return 0; 275 } 276 277 static int radeon_resume(struct drm_device *dev) 278 { 279 drm_radeon_private_t *dev_priv = dev->dev_private; 280 281 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 282 return 0; 283 284 /* Restore interrupt registers */ 285 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) 286 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); 287 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); 288 return 0; 289 } 290 291 292 static const struct file_operations radeon_driver_old_fops = { 293 .owner = THIS_MODULE, 294 .open = drm_open, 295 .release = drm_release, 296 .unlocked_ioctl = drm_ioctl, 297 .mmap = drm_mmap, 298 .poll = drm_poll, 299 .read = drm_read, 300 #ifdef CONFIG_COMPAT 301 .compat_ioctl = radeon_compat_ioctl, 302 #endif 303 .llseek = noop_llseek, 304 }; 305 306 static struct drm_driver driver_old = { 307 .driver_features = 308 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | 309 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED, 310 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 311 .load = radeon_driver_load, 312 .firstopen = radeon_driver_firstopen, 313 .open = radeon_driver_open, 314 .preclose = radeon_driver_preclose, 315 .postclose = radeon_driver_postclose, 316 .lastclose = radeon_driver_lastclose, 317 .unload = radeon_driver_unload, 318 .suspend = radeon_suspend, 319 .resume = radeon_resume, 320 .get_vblank_counter = radeon_get_vblank_counter, 321 .enable_vblank = radeon_enable_vblank, 322 .disable_vblank = radeon_disable_vblank, 323 .master_create = radeon_master_create, 324 .master_destroy = radeon_master_destroy, 325 .irq_preinstall = radeon_driver_irq_preinstall, 326 .irq_postinstall = radeon_driver_irq_postinstall, 327 .irq_uninstall = radeon_driver_irq_uninstall, 328 .irq_handler = radeon_driver_irq_handler, 329 .ioctls = radeon_ioctls, 330 .dma_ioctl = radeon_cp_buffers, 331 .fops = &radeon_driver_old_fops, 332 .name = DRIVER_NAME, 333 .desc = DRIVER_DESC, 334 .date = DRIVER_DATE, 335 .major = DRIVER_MAJOR, 336 .minor = DRIVER_MINOR, 337 .patchlevel = DRIVER_PATCHLEVEL, 338 }; 339 340 #endif 341 342 static struct drm_driver kms_driver; 343 344 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 345 { 346 struct apertures_struct *ap; 347 bool primary = false; 348 349 ap = alloc_apertures(1); 350 if (!ap) 351 return -ENOMEM; 352 353 ap->ranges[0].base = pci_resource_start(pdev, 0); 354 ap->ranges[0].size = pci_resource_len(pdev, 0); 355 356 #ifdef CONFIG_X86 357 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 358 #endif 359 remove_conflicting_framebuffers(ap, "radeondrmfb", primary); 360 kfree(ap); 361 362 return 0; 363 } 364 365 static int radeon_pci_probe(struct pci_dev *pdev, 366 const struct pci_device_id *ent) 367 { 368 int ret; 369 370 /* Get rid of things like offb */ 371 ret = radeon_kick_out_firmware_fb(pdev); 372 if (ret) 373 return ret; 374 375 return drm_get_pci_dev(pdev, ent, &kms_driver); 376 } 377 378 static void 379 radeon_pci_remove(struct pci_dev *pdev) 380 { 381 struct drm_device *dev = pci_get_drvdata(pdev); 382 383 drm_put_dev(dev); 384 } 385 386 static int radeon_pmops_suspend(struct device *dev) 387 { 388 struct pci_dev *pdev = to_pci_dev(dev); 389 struct drm_device *drm_dev = pci_get_drvdata(pdev); 390 return radeon_suspend_kms(drm_dev, true, true); 391 } 392 393 static int radeon_pmops_resume(struct device *dev) 394 { 395 struct pci_dev *pdev = to_pci_dev(dev); 396 struct drm_device *drm_dev = pci_get_drvdata(pdev); 397 return radeon_resume_kms(drm_dev, true, true); 398 } 399 400 static int radeon_pmops_freeze(struct device *dev) 401 { 402 struct pci_dev *pdev = to_pci_dev(dev); 403 struct drm_device *drm_dev = pci_get_drvdata(pdev); 404 return radeon_suspend_kms(drm_dev, false, true); 405 } 406 407 static int radeon_pmops_thaw(struct device *dev) 408 { 409 struct pci_dev *pdev = to_pci_dev(dev); 410 struct drm_device *drm_dev = pci_get_drvdata(pdev); 411 return radeon_resume_kms(drm_dev, false, true); 412 } 413 414 static int radeon_pmops_runtime_suspend(struct device *dev) 415 { 416 struct pci_dev *pdev = to_pci_dev(dev); 417 struct drm_device *drm_dev = pci_get_drvdata(pdev); 418 int ret; 419 420 if (!radeon_is_px(drm_dev)) { 421 pm_runtime_forbid(dev); 422 return -EBUSY; 423 } 424 425 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 426 drm_kms_helper_poll_disable(drm_dev); 427 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 428 429 ret = radeon_suspend_kms(drm_dev, false, false); 430 pci_save_state(pdev); 431 pci_disable_device(pdev); 432 pci_set_power_state(pdev, PCI_D3cold); 433 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 434 435 return 0; 436 } 437 438 static int radeon_pmops_runtime_resume(struct device *dev) 439 { 440 struct pci_dev *pdev = to_pci_dev(dev); 441 struct drm_device *drm_dev = pci_get_drvdata(pdev); 442 int ret; 443 444 if (!radeon_is_px(drm_dev)) 445 return -EINVAL; 446 447 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 448 449 pci_set_power_state(pdev, PCI_D0); 450 pci_restore_state(pdev); 451 ret = pci_enable_device(pdev); 452 if (ret) 453 return ret; 454 pci_set_master(pdev); 455 456 ret = radeon_resume_kms(drm_dev, false, false); 457 drm_kms_helper_poll_enable(drm_dev); 458 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 459 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 460 return 0; 461 } 462 463 static int radeon_pmops_runtime_idle(struct device *dev) 464 { 465 struct pci_dev *pdev = to_pci_dev(dev); 466 struct drm_device *drm_dev = pci_get_drvdata(pdev); 467 struct drm_crtc *crtc; 468 469 if (!radeon_is_px(drm_dev)) { 470 pm_runtime_forbid(dev); 471 return -EBUSY; 472 } 473 474 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 475 if (crtc->enabled) { 476 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 477 return -EBUSY; 478 } 479 } 480 481 pm_runtime_mark_last_busy(dev); 482 pm_runtime_autosuspend(dev); 483 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 484 return 1; 485 } 486 487 long radeon_drm_ioctl(struct file *filp, 488 unsigned int cmd, unsigned long arg) 489 { 490 struct drm_file *file_priv = filp->private_data; 491 struct drm_device *dev; 492 long ret; 493 dev = file_priv->minor->dev; 494 ret = pm_runtime_get_sync(dev->dev); 495 if (ret < 0) 496 return ret; 497 498 ret = drm_ioctl(filp, cmd, arg); 499 500 pm_runtime_mark_last_busy(dev->dev); 501 pm_runtime_put_autosuspend(dev->dev); 502 return ret; 503 } 504 505 static const struct dev_pm_ops radeon_pm_ops = { 506 .suspend = radeon_pmops_suspend, 507 .resume = radeon_pmops_resume, 508 .freeze = radeon_pmops_freeze, 509 .thaw = radeon_pmops_thaw, 510 .poweroff = radeon_pmops_freeze, 511 .restore = radeon_pmops_resume, 512 .runtime_suspend = radeon_pmops_runtime_suspend, 513 .runtime_resume = radeon_pmops_runtime_resume, 514 .runtime_idle = radeon_pmops_runtime_idle, 515 }; 516 517 static const struct file_operations radeon_driver_kms_fops = { 518 .owner = THIS_MODULE, 519 .open = drm_open, 520 .release = drm_release, 521 .unlocked_ioctl = radeon_drm_ioctl, 522 .mmap = radeon_mmap, 523 .poll = drm_poll, 524 .read = drm_read, 525 #ifdef CONFIG_COMPAT 526 .compat_ioctl = radeon_kms_compat_ioctl, 527 #endif 528 }; 529 530 static struct drm_driver kms_driver = { 531 .driver_features = 532 DRIVER_USE_AGP | 533 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 534 DRIVER_PRIME | DRIVER_RENDER, 535 .load = radeon_driver_load_kms, 536 .open = radeon_driver_open_kms, 537 .preclose = radeon_driver_preclose_kms, 538 .postclose = radeon_driver_postclose_kms, 539 .lastclose = radeon_driver_lastclose_kms, 540 .unload = radeon_driver_unload_kms, 541 .get_vblank_counter = radeon_get_vblank_counter_kms, 542 .enable_vblank = radeon_enable_vblank_kms, 543 .disable_vblank = radeon_disable_vblank_kms, 544 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 545 .get_scanout_position = radeon_get_crtc_scanoutpos, 546 #if defined(CONFIG_DEBUG_FS) 547 .debugfs_init = radeon_debugfs_init, 548 .debugfs_cleanup = radeon_debugfs_cleanup, 549 #endif 550 .irq_preinstall = radeon_driver_irq_preinstall_kms, 551 .irq_postinstall = radeon_driver_irq_postinstall_kms, 552 .irq_uninstall = radeon_driver_irq_uninstall_kms, 553 .irq_handler = radeon_driver_irq_handler_kms, 554 .ioctls = radeon_ioctls_kms, 555 .gem_free_object = radeon_gem_object_free, 556 .gem_open_object = radeon_gem_object_open, 557 .gem_close_object = radeon_gem_object_close, 558 .dumb_create = radeon_mode_dumb_create, 559 .dumb_map_offset = radeon_mode_dumb_mmap, 560 .dumb_destroy = drm_gem_dumb_destroy, 561 .fops = &radeon_driver_kms_fops, 562 563 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 564 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 565 .gem_prime_export = drm_gem_prime_export, 566 .gem_prime_import = drm_gem_prime_import, 567 .gem_prime_pin = radeon_gem_prime_pin, 568 .gem_prime_unpin = radeon_gem_prime_unpin, 569 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 570 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 571 .gem_prime_vmap = radeon_gem_prime_vmap, 572 .gem_prime_vunmap = radeon_gem_prime_vunmap, 573 574 .name = DRIVER_NAME, 575 .desc = DRIVER_DESC, 576 .date = DRIVER_DATE, 577 .major = KMS_DRIVER_MAJOR, 578 .minor = KMS_DRIVER_MINOR, 579 .patchlevel = KMS_DRIVER_PATCHLEVEL, 580 }; 581 582 static struct drm_driver *driver; 583 static struct pci_driver *pdriver; 584 585 #ifdef CONFIG_DRM_RADEON_UMS 586 static struct pci_driver radeon_pci_driver = { 587 .name = DRIVER_NAME, 588 .id_table = pciidlist, 589 }; 590 #endif 591 592 static struct pci_driver radeon_kms_pci_driver = { 593 .name = DRIVER_NAME, 594 .id_table = pciidlist, 595 .probe = radeon_pci_probe, 596 .remove = radeon_pci_remove, 597 .driver.pm = &radeon_pm_ops, 598 }; 599 600 static int __init radeon_init(void) 601 { 602 #ifdef CONFIG_VGA_CONSOLE 603 if (vgacon_text_force() && radeon_modeset == -1) { 604 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 605 radeon_modeset = 0; 606 } 607 #endif 608 /* set to modesetting by default if not nomodeset */ 609 if (radeon_modeset == -1) 610 radeon_modeset = 1; 611 612 if (radeon_modeset == 1) { 613 DRM_INFO("radeon kernel modesetting enabled.\n"); 614 driver = &kms_driver; 615 pdriver = &radeon_kms_pci_driver; 616 driver->driver_features |= DRIVER_MODESET; 617 driver->num_ioctls = radeon_max_kms_ioctl; 618 radeon_register_atpx_handler(); 619 620 } else { 621 #ifdef CONFIG_DRM_RADEON_UMS 622 DRM_INFO("radeon userspace modesetting enabled.\n"); 623 driver = &driver_old; 624 pdriver = &radeon_pci_driver; 625 driver->driver_features &= ~DRIVER_MODESET; 626 driver->num_ioctls = radeon_max_ioctl; 627 #else 628 DRM_ERROR("No UMS support in radeon module!\n"); 629 return -EINVAL; 630 #endif 631 } 632 633 /* let modprobe override vga console setting */ 634 return drm_pci_init(driver, pdriver); 635 } 636 637 static void __exit radeon_exit(void) 638 { 639 drm_pci_exit(driver, pdriver); 640 radeon_unregister_atpx_handler(); 641 } 642 643 module_init(radeon_init); 644 module_exit(radeon_exit); 645 646 MODULE_AUTHOR(DRIVER_AUTHOR); 647 MODULE_DESCRIPTION(DRIVER_DESC); 648 MODULE_LICENSE("GPL and additional rights"); 649