1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 40 #include <drm/drm_agpsupport.h> 41 #include <drm/drm_crtc_helper.h> 42 #include <drm/drm_drv.h> 43 #include <drm/drm_fb_helper.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_gem.h> 46 #include <drm/drm_ioctl.h> 47 #include <drm/drm_pci.h> 48 #include <drm/drm_pciids.h> 49 #include <drm/drm_probe_helper.h> 50 #include <drm/drm_vblank.h> 51 #include <drm/radeon_drm.h> 52 53 #include "radeon_drv.h" 54 55 /* 56 * KMS wrapper. 57 * - 2.0.0 - initial interface 58 * - 2.1.0 - add square tiling interface 59 * - 2.2.0 - add r6xx/r7xx const buffer support 60 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 61 * - 2.4.0 - add crtc id query 62 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 63 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 64 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 65 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 66 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 67 * 2.10.0 - fusion 2D tiling 68 * 2.11.0 - backend map, initial compute support for the CS checker 69 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 70 * 2.13.0 - virtual memory support, streamout 71 * 2.14.0 - add evergreen tiling informations 72 * 2.15.0 - add max_pipes query 73 * 2.16.0 - fix evergreen 2D tiled surface calculation 74 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 75 * 2.18.0 - r600-eg: allow "invalid" DB formats 76 * 2.19.0 - r600-eg: MSAA textures 77 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 78 * 2.21.0 - r600-r700: FMASK and CMASK 79 * 2.22.0 - r600 only: RESOLVE_BOX allowed 80 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 81 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 82 * 2.25.0 - eg+: new info request for num SE and num SH 83 * 2.26.0 - r600-eg: fix htile size computation 84 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 85 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 86 * 2.29.0 - R500 FP16 color clear registers 87 * 2.30.0 - fix for FMASK texturing 88 * 2.31.0 - Add fastfb support for rs690 89 * 2.32.0 - new info request for rings working 90 * 2.33.0 - Add SI tiling mode array query 91 * 2.34.0 - Add CIK tiling mode array query 92 * 2.35.0 - Add CIK macrotile mode array query 93 * 2.36.0 - Fix CIK DCE tiling setup 94 * 2.37.0 - allow GS ring setup on r6xx/r7xx 95 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 96 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 97 * 2.39.0 - Add INFO query for number of active CUs 98 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 99 * CS to GPU on >= r600 100 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 101 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 102 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 103 * 2.44.0 - SET_APPEND_CNT packet3 support 104 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 105 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 106 * 2.47.0 - Add UVD_NO_OP register support 107 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 108 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 109 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 110 */ 111 #define KMS_DRIVER_MAJOR 2 112 #define KMS_DRIVER_MINOR 50 113 #define KMS_DRIVER_PATCHLEVEL 0 114 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 115 void radeon_driver_unload_kms(struct drm_device *dev); 116 void radeon_driver_lastclose_kms(struct drm_device *dev); 117 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 118 void radeon_driver_postclose_kms(struct drm_device *dev, 119 struct drm_file *file_priv); 120 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 121 bool fbcon, bool freeze); 122 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 123 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 124 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 125 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 126 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 127 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 128 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 129 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 130 void radeon_gem_object_free(struct drm_gem_object *obj); 131 int radeon_gem_object_open(struct drm_gem_object *obj, 132 struct drm_file *file_priv); 133 void radeon_gem_object_close(struct drm_gem_object *obj, 134 struct drm_file *file_priv); 135 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 136 int flags); 137 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 138 unsigned int flags, int *vpos, int *hpos, 139 ktime_t *stime, ktime_t *etime, 140 const struct drm_display_mode *mode); 141 extern bool radeon_is_px(struct drm_device *dev); 142 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 143 extern int radeon_max_kms_ioctl; 144 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 145 int radeon_mode_dumb_mmap(struct drm_file *filp, 146 struct drm_device *dev, 147 uint32_t handle, uint64_t *offset_p); 148 int radeon_mode_dumb_create(struct drm_file *file_priv, 149 struct drm_device *dev, 150 struct drm_mode_create_dumb *args); 151 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 152 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 153 struct dma_buf_attachment *, 154 struct sg_table *sg); 155 int radeon_gem_prime_pin(struct drm_gem_object *obj); 156 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 157 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 158 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 159 160 /* atpx handler */ 161 #if defined(CONFIG_VGA_SWITCHEROO) 162 void radeon_register_atpx_handler(void); 163 void radeon_unregister_atpx_handler(void); 164 bool radeon_has_atpx_dgpu_power_cntl(void); 165 bool radeon_is_atpx_hybrid(void); 166 #else 167 static inline void radeon_register_atpx_handler(void) {} 168 static inline void radeon_unregister_atpx_handler(void) {} 169 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 170 static inline bool radeon_is_atpx_hybrid(void) { return false; } 171 #endif 172 173 int radeon_no_wb; 174 int radeon_modeset = -1; 175 int radeon_dynclks = -1; 176 int radeon_r4xx_atom = 0; 177 #ifdef __powerpc__ 178 /* Default to PCI on PowerPC (fdo #95017) */ 179 int radeon_agpmode = -1; 180 #else 181 int radeon_agpmode = 0; 182 #endif 183 int radeon_vram_limit = 0; 184 int radeon_gart_size = -1; /* auto */ 185 int radeon_benchmarking = 0; 186 int radeon_testing = 0; 187 int radeon_connector_table = 0; 188 int radeon_tv = 1; 189 int radeon_audio = -1; 190 int radeon_disp_priority = 0; 191 int radeon_hw_i2c = 0; 192 int radeon_pcie_gen2 = -1; 193 int radeon_msi = -1; 194 int radeon_lockup_timeout = 10000; 195 int radeon_fastfb = 0; 196 int radeon_dpm = -1; 197 int radeon_aspm = -1; 198 int radeon_runtime_pm = -1; 199 int radeon_hard_reset = 0; 200 int radeon_vm_size = 8; 201 int radeon_vm_block_size = -1; 202 int radeon_deep_color = 0; 203 int radeon_use_pflipirq = 2; 204 int radeon_bapm = -1; 205 int radeon_backlight = -1; 206 int radeon_auxch = -1; 207 int radeon_mst = 0; 208 int radeon_uvd = 1; 209 int radeon_vce = 1; 210 211 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 212 module_param_named(no_wb, radeon_no_wb, int, 0444); 213 214 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 215 module_param_named(modeset, radeon_modeset, int, 0400); 216 217 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 218 module_param_named(dynclks, radeon_dynclks, int, 0444); 219 220 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 221 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 222 223 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 224 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 225 226 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 227 module_param_named(agpmode, radeon_agpmode, int, 0444); 228 229 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 230 module_param_named(gartsize, radeon_gart_size, int, 0600); 231 232 MODULE_PARM_DESC(benchmark, "Run benchmark"); 233 module_param_named(benchmark, radeon_benchmarking, int, 0444); 234 235 MODULE_PARM_DESC(test, "Run tests"); 236 module_param_named(test, radeon_testing, int, 0444); 237 238 MODULE_PARM_DESC(connector_table, "Force connector table"); 239 module_param_named(connector_table, radeon_connector_table, int, 0444); 240 241 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 242 module_param_named(tv, radeon_tv, int, 0444); 243 244 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 245 module_param_named(audio, radeon_audio, int, 0444); 246 247 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 248 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 249 250 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 251 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 252 253 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 254 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 255 256 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 257 module_param_named(msi, radeon_msi, int, 0444); 258 259 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 260 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 261 262 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 263 module_param_named(fastfb, radeon_fastfb, int, 0444); 264 265 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 266 module_param_named(dpm, radeon_dpm, int, 0444); 267 268 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 269 module_param_named(aspm, radeon_aspm, int, 0444); 270 271 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 272 module_param_named(runpm, radeon_runtime_pm, int, 0444); 273 274 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 275 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 276 277 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 278 module_param_named(vm_size, radeon_vm_size, int, 0444); 279 280 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 281 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 282 283 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 284 module_param_named(deep_color, radeon_deep_color, int, 0444); 285 286 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 287 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 288 289 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 290 module_param_named(bapm, radeon_bapm, int, 0444); 291 292 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 293 module_param_named(backlight, radeon_backlight, int, 0444); 294 295 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 296 module_param_named(auxch, radeon_auxch, int, 0444); 297 298 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 299 module_param_named(mst, radeon_mst, int, 0444); 300 301 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 302 module_param_named(uvd, radeon_uvd, int, 0444); 303 304 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 305 module_param_named(vce, radeon_vce, int, 0444); 306 307 int radeon_si_support = 1; 308 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 309 module_param_named(si_support, radeon_si_support, int, 0444); 310 311 int radeon_cik_support = 1; 312 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 313 module_param_named(cik_support, radeon_cik_support, int, 0444); 314 315 static struct pci_device_id pciidlist[] = { 316 radeon_PCI_IDS 317 }; 318 319 MODULE_DEVICE_TABLE(pci, pciidlist); 320 321 static struct drm_driver kms_driver; 322 323 bool radeon_device_is_virtual(void); 324 325 static int radeon_pci_probe(struct pci_dev *pdev, 326 const struct pci_device_id *ent) 327 { 328 unsigned long flags = 0; 329 struct drm_device *dev; 330 int ret; 331 332 if (!ent) 333 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 334 335 flags = ent->driver_data; 336 337 if (!radeon_si_support) { 338 switch (flags & RADEON_FAMILY_MASK) { 339 case CHIP_TAHITI: 340 case CHIP_PITCAIRN: 341 case CHIP_VERDE: 342 case CHIP_OLAND: 343 case CHIP_HAINAN: 344 dev_info(&pdev->dev, 345 "SI support disabled by module param\n"); 346 return -ENODEV; 347 } 348 } 349 if (!radeon_cik_support) { 350 switch (flags & RADEON_FAMILY_MASK) { 351 case CHIP_KAVERI: 352 case CHIP_BONAIRE: 353 case CHIP_HAWAII: 354 case CHIP_KABINI: 355 case CHIP_MULLINS: 356 dev_info(&pdev->dev, 357 "CIK support disabled by module param\n"); 358 return -ENODEV; 359 } 360 } 361 362 if (vga_switcheroo_client_probe_defer(pdev)) 363 return -EPROBE_DEFER; 364 365 /* Get rid of things like offb */ 366 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 367 if (ret) 368 return ret; 369 370 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 371 if (IS_ERR(dev)) 372 return PTR_ERR(dev); 373 374 ret = pci_enable_device(pdev); 375 if (ret) 376 goto err_free; 377 378 dev->pdev = pdev; 379 #ifdef __alpha__ 380 dev->hose = pdev->sysdata; 381 #endif 382 383 pci_set_drvdata(pdev, dev); 384 385 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) 386 dev->agp = drm_agp_init(dev); 387 if (dev->agp) { 388 dev->agp->agp_mtrr = arch_phys_wc_add( 389 dev->agp->agp_info.aper_base, 390 dev->agp->agp_info.aper_size * 391 1024 * 1024); 392 } 393 394 ret = drm_dev_register(dev, ent->driver_data); 395 if (ret) 396 goto err_agp; 397 398 return 0; 399 400 err_agp: 401 if (dev->agp) 402 arch_phys_wc_del(dev->agp->agp_mtrr); 403 kfree(dev->agp); 404 pci_disable_device(pdev); 405 err_free: 406 drm_dev_put(dev); 407 return ret; 408 } 409 410 static void 411 radeon_pci_remove(struct pci_dev *pdev) 412 { 413 struct drm_device *dev = pci_get_drvdata(pdev); 414 415 drm_put_dev(dev); 416 } 417 418 static void 419 radeon_pci_shutdown(struct pci_dev *pdev) 420 { 421 /* if we are running in a VM, make sure the device 422 * torn down properly on reboot/shutdown 423 */ 424 if (radeon_device_is_virtual()) 425 radeon_pci_remove(pdev); 426 427 #ifdef CONFIG_PPC64 428 /* 429 * Some adapters need to be suspended before a 430 * shutdown occurs in order to prevent an error 431 * during kexec. 432 * Make this power specific becauase it breaks 433 * some non-power boards. 434 */ 435 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 436 #endif 437 } 438 439 static int radeon_pmops_suspend(struct device *dev) 440 { 441 struct drm_device *drm_dev = dev_get_drvdata(dev); 442 return radeon_suspend_kms(drm_dev, true, true, false); 443 } 444 445 static int radeon_pmops_resume(struct device *dev) 446 { 447 struct drm_device *drm_dev = dev_get_drvdata(dev); 448 449 /* GPU comes up enabled by the bios on resume */ 450 if (radeon_is_px(drm_dev)) { 451 pm_runtime_disable(dev); 452 pm_runtime_set_active(dev); 453 pm_runtime_enable(dev); 454 } 455 456 return radeon_resume_kms(drm_dev, true, true); 457 } 458 459 static int radeon_pmops_freeze(struct device *dev) 460 { 461 struct drm_device *drm_dev = dev_get_drvdata(dev); 462 return radeon_suspend_kms(drm_dev, false, true, true); 463 } 464 465 static int radeon_pmops_thaw(struct device *dev) 466 { 467 struct drm_device *drm_dev = dev_get_drvdata(dev); 468 return radeon_resume_kms(drm_dev, false, true); 469 } 470 471 static int radeon_pmops_runtime_suspend(struct device *dev) 472 { 473 struct pci_dev *pdev = to_pci_dev(dev); 474 struct drm_device *drm_dev = pci_get_drvdata(pdev); 475 int ret; 476 477 if (!radeon_is_px(drm_dev)) { 478 pm_runtime_forbid(dev); 479 return -EBUSY; 480 } 481 482 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 483 drm_kms_helper_poll_disable(drm_dev); 484 485 ret = radeon_suspend_kms(drm_dev, false, false, false); 486 pci_save_state(pdev); 487 pci_disable_device(pdev); 488 pci_ignore_hotplug(pdev); 489 if (radeon_is_atpx_hybrid()) 490 pci_set_power_state(pdev, PCI_D3cold); 491 else if (!radeon_has_atpx_dgpu_power_cntl()) 492 pci_set_power_state(pdev, PCI_D3hot); 493 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 494 495 return 0; 496 } 497 498 static int radeon_pmops_runtime_resume(struct device *dev) 499 { 500 struct pci_dev *pdev = to_pci_dev(dev); 501 struct drm_device *drm_dev = pci_get_drvdata(pdev); 502 int ret; 503 504 if (!radeon_is_px(drm_dev)) 505 return -EINVAL; 506 507 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 508 509 if (radeon_is_atpx_hybrid() || 510 !radeon_has_atpx_dgpu_power_cntl()) 511 pci_set_power_state(pdev, PCI_D0); 512 pci_restore_state(pdev); 513 ret = pci_enable_device(pdev); 514 if (ret) 515 return ret; 516 pci_set_master(pdev); 517 518 ret = radeon_resume_kms(drm_dev, false, false); 519 drm_kms_helper_poll_enable(drm_dev); 520 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 521 return 0; 522 } 523 524 static int radeon_pmops_runtime_idle(struct device *dev) 525 { 526 struct drm_device *drm_dev = dev_get_drvdata(dev); 527 struct drm_crtc *crtc; 528 529 if (!radeon_is_px(drm_dev)) { 530 pm_runtime_forbid(dev); 531 return -EBUSY; 532 } 533 534 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 535 if (crtc->enabled) { 536 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 537 return -EBUSY; 538 } 539 } 540 541 pm_runtime_mark_last_busy(dev); 542 pm_runtime_autosuspend(dev); 543 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 544 return 1; 545 } 546 547 long radeon_drm_ioctl(struct file *filp, 548 unsigned int cmd, unsigned long arg) 549 { 550 struct drm_file *file_priv = filp->private_data; 551 struct drm_device *dev; 552 long ret; 553 dev = file_priv->minor->dev; 554 ret = pm_runtime_get_sync(dev->dev); 555 if (ret < 0) 556 return ret; 557 558 ret = drm_ioctl(filp, cmd, arg); 559 560 pm_runtime_mark_last_busy(dev->dev); 561 pm_runtime_put_autosuspend(dev->dev); 562 return ret; 563 } 564 565 #ifdef CONFIG_COMPAT 566 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 567 { 568 unsigned int nr = DRM_IOCTL_NR(cmd); 569 int ret; 570 571 if (nr < DRM_COMMAND_BASE) 572 return drm_compat_ioctl(filp, cmd, arg); 573 574 ret = radeon_drm_ioctl(filp, cmd, arg); 575 576 return ret; 577 } 578 #endif 579 580 static const struct dev_pm_ops radeon_pm_ops = { 581 .suspend = radeon_pmops_suspend, 582 .resume = radeon_pmops_resume, 583 .freeze = radeon_pmops_freeze, 584 .thaw = radeon_pmops_thaw, 585 .poweroff = radeon_pmops_freeze, 586 .restore = radeon_pmops_resume, 587 .runtime_suspend = radeon_pmops_runtime_suspend, 588 .runtime_resume = radeon_pmops_runtime_resume, 589 .runtime_idle = radeon_pmops_runtime_idle, 590 }; 591 592 static const struct file_operations radeon_driver_kms_fops = { 593 .owner = THIS_MODULE, 594 .open = drm_open, 595 .release = drm_release, 596 .unlocked_ioctl = radeon_drm_ioctl, 597 .mmap = radeon_mmap, 598 .poll = drm_poll, 599 .read = drm_read, 600 #ifdef CONFIG_COMPAT 601 .compat_ioctl = radeon_kms_compat_ioctl, 602 #endif 603 }; 604 605 static bool 606 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 607 bool in_vblank_irq, int *vpos, int *hpos, 608 ktime_t *stime, ktime_t *etime, 609 const struct drm_display_mode *mode) 610 { 611 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 612 stime, etime, mode); 613 } 614 615 static struct drm_driver kms_driver = { 616 .driver_features = 617 DRIVER_GEM | DRIVER_RENDER, 618 .load = radeon_driver_load_kms, 619 .open = radeon_driver_open_kms, 620 .postclose = radeon_driver_postclose_kms, 621 .lastclose = radeon_driver_lastclose_kms, 622 .unload = radeon_driver_unload_kms, 623 .get_vblank_counter = radeon_get_vblank_counter_kms, 624 .enable_vblank = radeon_enable_vblank_kms, 625 .disable_vblank = radeon_disable_vblank_kms, 626 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 627 .get_scanout_position = radeon_get_crtc_scanout_position, 628 .irq_preinstall = radeon_driver_irq_preinstall_kms, 629 .irq_postinstall = radeon_driver_irq_postinstall_kms, 630 .irq_uninstall = radeon_driver_irq_uninstall_kms, 631 .irq_handler = radeon_driver_irq_handler_kms, 632 .ioctls = radeon_ioctls_kms, 633 .gem_free_object_unlocked = radeon_gem_object_free, 634 .gem_open_object = radeon_gem_object_open, 635 .gem_close_object = radeon_gem_object_close, 636 .dumb_create = radeon_mode_dumb_create, 637 .dumb_map_offset = radeon_mode_dumb_mmap, 638 .fops = &radeon_driver_kms_fops, 639 640 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 641 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 642 .gem_prime_export = radeon_gem_prime_export, 643 .gem_prime_pin = radeon_gem_prime_pin, 644 .gem_prime_unpin = radeon_gem_prime_unpin, 645 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 646 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 647 .gem_prime_vmap = radeon_gem_prime_vmap, 648 .gem_prime_vunmap = radeon_gem_prime_vunmap, 649 650 .name = DRIVER_NAME, 651 .desc = DRIVER_DESC, 652 .date = DRIVER_DATE, 653 .major = KMS_DRIVER_MAJOR, 654 .minor = KMS_DRIVER_MINOR, 655 .patchlevel = KMS_DRIVER_PATCHLEVEL, 656 }; 657 658 static struct drm_driver *driver; 659 static struct pci_driver *pdriver; 660 661 static struct pci_driver radeon_kms_pci_driver = { 662 .name = DRIVER_NAME, 663 .id_table = pciidlist, 664 .probe = radeon_pci_probe, 665 .remove = radeon_pci_remove, 666 .shutdown = radeon_pci_shutdown, 667 .driver.pm = &radeon_pm_ops, 668 }; 669 670 static int __init radeon_init(void) 671 { 672 if (vgacon_text_force() && radeon_modeset == -1) { 673 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 674 radeon_modeset = 0; 675 } 676 /* set to modesetting by default if not nomodeset */ 677 if (radeon_modeset == -1) 678 radeon_modeset = 1; 679 680 if (radeon_modeset == 1) { 681 DRM_INFO("radeon kernel modesetting enabled.\n"); 682 driver = &kms_driver; 683 pdriver = &radeon_kms_pci_driver; 684 driver->driver_features |= DRIVER_MODESET; 685 driver->num_ioctls = radeon_max_kms_ioctl; 686 radeon_register_atpx_handler(); 687 688 } else { 689 DRM_ERROR("No UMS support in radeon module!\n"); 690 return -EINVAL; 691 } 692 693 return pci_register_driver(pdriver); 694 } 695 696 static void __exit radeon_exit(void) 697 { 698 pci_unregister_driver(pdriver); 699 radeon_unregister_atpx_handler(); 700 mmu_notifier_synchronize(); 701 } 702 703 module_init(radeon_init); 704 module_exit(radeon_exit); 705 706 MODULE_AUTHOR(DRIVER_AUTHOR); 707 MODULE_DESCRIPTION(DRIVER_DESC); 708 MODULE_LICENSE("GPL and additional rights"); 709