1 /* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <linux/aperture.h> 33 #include <linux/compat.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pci.h> 39 40 #include <drm/drm_client_setup.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_gem.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_pciids.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_vblank.h> 49 #include <drm/radeon_drm.h> 50 51 #include "radeon_drv.h" 52 #include "radeon.h" 53 #include "radeon_kms.h" 54 #include "radeon_ttm.h" 55 #include "radeon_device.h" 56 #include "radeon_prime.h" 57 58 /* 59 * KMS wrapper. 60 * - 2.0.0 - initial interface 61 * - 2.1.0 - add square tiling interface 62 * - 2.2.0 - add r6xx/r7xx const buffer support 63 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 64 * - 2.4.0 - add crtc id query 65 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 66 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 67 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 68 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 69 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 70 * 2.10.0 - fusion 2D tiling 71 * 2.11.0 - backend map, initial compute support for the CS checker 72 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 73 * 2.13.0 - virtual memory support, streamout 74 * 2.14.0 - add evergreen tiling informations 75 * 2.15.0 - add max_pipes query 76 * 2.16.0 - fix evergreen 2D tiled surface calculation 77 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 78 * 2.18.0 - r600-eg: allow "invalid" DB formats 79 * 2.19.0 - r600-eg: MSAA textures 80 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 81 * 2.21.0 - r600-r700: FMASK and CMASK 82 * 2.22.0 - r600 only: RESOLVE_BOX allowed 83 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 84 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 85 * 2.25.0 - eg+: new info request for num SE and num SH 86 * 2.26.0 - r600-eg: fix htile size computation 87 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 88 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 89 * 2.29.0 - R500 FP16 color clear registers 90 * 2.30.0 - fix for FMASK texturing 91 * 2.31.0 - Add fastfb support for rs690 92 * 2.32.0 - new info request for rings working 93 * 2.33.0 - Add SI tiling mode array query 94 * 2.34.0 - Add CIK tiling mode array query 95 * 2.35.0 - Add CIK macrotile mode array query 96 * 2.36.0 - Fix CIK DCE tiling setup 97 * 2.37.0 - allow GS ring setup on r6xx/r7xx 98 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 99 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 100 * 2.39.0 - Add INFO query for number of active CUs 101 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 102 * CS to GPU on >= r600 103 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 104 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 105 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 106 * 2.44.0 - SET_APPEND_CNT packet3 support 107 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 108 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 109 * 2.47.0 - Add UVD_NO_OP register support 110 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 111 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 112 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 113 */ 114 #define KMS_DRIVER_MAJOR 2 115 #define KMS_DRIVER_MINOR 50 116 #define KMS_DRIVER_PATCHLEVEL 0 117 118 int radeon_no_wb; 119 int radeon_modeset = -1; 120 int radeon_dynclks = -1; 121 int radeon_r4xx_atom; 122 int radeon_agpmode = -1; 123 int radeon_vram_limit; 124 int radeon_gart_size = -1; /* auto */ 125 int radeon_benchmarking; 126 int radeon_testing; 127 int radeon_connector_table; 128 int radeon_tv = 1; 129 int radeon_audio = -1; 130 int radeon_disp_priority; 131 int radeon_hw_i2c; 132 int radeon_pcie_gen2 = -1; 133 int radeon_msi = -1; 134 int radeon_lockup_timeout = 10000; 135 int radeon_fastfb; 136 int radeon_dpm = -1; 137 int radeon_aspm = -1; 138 int radeon_runtime_pm = -1; 139 int radeon_hard_reset; 140 int radeon_vm_size = 8; 141 int radeon_vm_block_size = -1; 142 int radeon_deep_color; 143 int radeon_use_pflipirq = 2; 144 int radeon_bapm = -1; 145 int radeon_backlight = -1; 146 int radeon_auxch = -1; 147 int radeon_uvd = 1; 148 int radeon_vce = 1; 149 150 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 151 module_param_named(no_wb, radeon_no_wb, int, 0444); 152 153 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 154 module_param_named(modeset, radeon_modeset, int, 0400); 155 156 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 157 module_param_named(dynclks, radeon_dynclks, int, 0444); 158 159 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 160 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 161 162 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 163 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 164 165 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 166 module_param_named(agpmode, radeon_agpmode, int, 0444); 167 168 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 169 module_param_named(gartsize, radeon_gart_size, int, 0600); 170 171 MODULE_PARM_DESC(benchmark, "Run benchmark"); 172 module_param_named(benchmark, radeon_benchmarking, int, 0444); 173 174 MODULE_PARM_DESC(test, "Run tests"); 175 module_param_named(test, radeon_testing, int, 0444); 176 177 MODULE_PARM_DESC(connector_table, "Force connector table"); 178 module_param_named(connector_table, radeon_connector_table, int, 0444); 179 180 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 181 module_param_named(tv, radeon_tv, int, 0444); 182 183 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 184 module_param_named(audio, radeon_audio, int, 0444); 185 186 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 187 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 188 189 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 190 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 191 192 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 193 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 194 195 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 196 module_param_named(msi, radeon_msi, int, 0444); 197 198 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 199 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 200 201 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 202 module_param_named(fastfb, radeon_fastfb, int, 0444); 203 204 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 205 module_param_named(dpm, radeon_dpm, int, 0444); 206 207 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 208 module_param_named(aspm, radeon_aspm, int, 0444); 209 210 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 211 module_param_named(runpm, radeon_runtime_pm, int, 0444); 212 213 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 214 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 215 216 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 217 module_param_named(vm_size, radeon_vm_size, int, 0444); 218 219 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 220 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 221 222 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 223 module_param_named(deep_color, radeon_deep_color, int, 0444); 224 225 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 226 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 227 228 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 229 module_param_named(bapm, radeon_bapm, int, 0444); 230 231 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 232 module_param_named(backlight, radeon_backlight, int, 0444); 233 234 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 235 module_param_named(auxch, radeon_auxch, int, 0444); 236 237 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 238 module_param_named(uvd, radeon_uvd, int, 0444); 239 240 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 241 module_param_named(vce, radeon_vce, int, 0444); 242 243 int radeon_si_support = 1; 244 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 245 module_param_named(si_support, radeon_si_support, int, 0444); 246 247 int radeon_cik_support = 1; 248 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 249 module_param_named(cik_support, radeon_cik_support, int, 0444); 250 251 static struct pci_device_id pciidlist[] = { 252 radeon_PCI_IDS 253 }; 254 255 MODULE_DEVICE_TABLE(pci, pciidlist); 256 257 static const struct drm_driver kms_driver; 258 259 static int radeon_pci_probe(struct pci_dev *pdev, 260 const struct pci_device_id *ent) 261 { 262 unsigned long flags = 0; 263 struct drm_device *ddev; 264 struct radeon_device *rdev; 265 const struct drm_format_info *format; 266 int ret; 267 268 if (!ent) 269 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 270 271 flags = ent->driver_data; 272 273 if (!radeon_si_support) { 274 switch (flags & RADEON_FAMILY_MASK) { 275 case CHIP_TAHITI: 276 case CHIP_PITCAIRN: 277 case CHIP_VERDE: 278 case CHIP_OLAND: 279 case CHIP_HAINAN: 280 dev_info(&pdev->dev, 281 "SI support disabled by module param\n"); 282 return -ENODEV; 283 } 284 } 285 if (!radeon_cik_support) { 286 switch (flags & RADEON_FAMILY_MASK) { 287 case CHIP_KAVERI: 288 case CHIP_BONAIRE: 289 case CHIP_HAWAII: 290 case CHIP_KABINI: 291 case CHIP_MULLINS: 292 dev_info(&pdev->dev, 293 "CIK support disabled by module param\n"); 294 return -ENODEV; 295 } 296 } 297 298 if (vga_switcheroo_client_probe_defer(pdev)) 299 return -EPROBE_DEFER; 300 301 /* Get rid of things like offb */ 302 ret = aperture_remove_conflicting_pci_devices(pdev, kms_driver.name); 303 if (ret) 304 return ret; 305 306 rdev = devm_drm_dev_alloc(&pdev->dev, &kms_driver, typeof(*rdev), ddev); 307 if (IS_ERR(rdev)) 308 return PTR_ERR(rdev); 309 310 rdev->dev = &pdev->dev; 311 rdev->pdev = pdev; 312 ddev = rdev_to_drm(rdev); 313 ddev->dev_private = rdev; 314 315 ret = pci_enable_device(pdev); 316 if (ret) 317 goto err_free; 318 319 pci_set_drvdata(pdev, ddev); 320 321 ret = radeon_driver_load_kms(ddev, flags); 322 if (ret) 323 goto err_agp; 324 325 ret = drm_dev_register(ddev, flags); 326 if (ret) 327 goto err_agp; 328 329 if (rdev->mc.real_vram_size <= (8 * 1024 * 1024)) 330 format = drm_format_info(DRM_FORMAT_C8); 331 else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024)) 332 format = drm_format_info(DRM_FORMAT_RGB565); 333 else 334 format = NULL; 335 336 drm_client_setup(ddev, format); 337 338 return 0; 339 340 err_agp: 341 pci_disable_device(pdev); 342 err_free: 343 drm_dev_put(ddev); 344 return ret; 345 } 346 347 static void 348 radeon_pci_remove(struct pci_dev *pdev) 349 { 350 struct drm_device *dev = pci_get_drvdata(pdev); 351 352 drm_put_dev(dev); 353 } 354 355 static void 356 radeon_pci_shutdown(struct pci_dev *pdev) 357 { 358 /* if we are running in a VM, make sure the device 359 * torn down properly on reboot/shutdown 360 */ 361 if (radeon_device_is_virtual()) 362 radeon_pci_remove(pdev); 363 364 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 365 /* 366 * Some adapters need to be suspended before a 367 * shutdown occurs in order to prevent an error 368 * during kexec, shutdown or reboot. 369 * Make this power and Loongson specific because 370 * it breaks some other boards. 371 */ 372 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 373 #endif 374 } 375 376 static int radeon_pmops_suspend(struct device *dev) 377 { 378 struct drm_device *drm_dev = dev_get_drvdata(dev); 379 380 return radeon_suspend_kms(drm_dev, true, true, false); 381 } 382 383 static int radeon_pmops_resume(struct device *dev) 384 { 385 struct drm_device *drm_dev = dev_get_drvdata(dev); 386 387 /* GPU comes up enabled by the bios on resume */ 388 if (radeon_is_px(drm_dev)) { 389 pm_runtime_disable(dev); 390 pm_runtime_set_active(dev); 391 pm_runtime_enable(dev); 392 } 393 394 return radeon_resume_kms(drm_dev, true, true); 395 } 396 397 static int radeon_pmops_freeze(struct device *dev) 398 { 399 struct drm_device *drm_dev = dev_get_drvdata(dev); 400 401 return radeon_suspend_kms(drm_dev, false, true, true); 402 } 403 404 static int radeon_pmops_thaw(struct device *dev) 405 { 406 struct drm_device *drm_dev = dev_get_drvdata(dev); 407 408 return radeon_resume_kms(drm_dev, false, true); 409 } 410 411 static int radeon_pmops_runtime_suspend(struct device *dev) 412 { 413 struct pci_dev *pdev = to_pci_dev(dev); 414 struct drm_device *drm_dev = pci_get_drvdata(pdev); 415 416 if (!radeon_is_px(drm_dev)) { 417 pm_runtime_forbid(dev); 418 return -EBUSY; 419 } 420 421 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 422 drm_kms_helper_poll_disable(drm_dev); 423 424 radeon_suspend_kms(drm_dev, false, false, false); 425 pci_save_state(pdev); 426 pci_disable_device(pdev); 427 pci_ignore_hotplug(pdev); 428 if (radeon_is_atpx_hybrid()) 429 pci_set_power_state(pdev, PCI_D3cold); 430 else if (!radeon_has_atpx_dgpu_power_cntl()) 431 pci_set_power_state(pdev, PCI_D3hot); 432 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 433 434 return 0; 435 } 436 437 static int radeon_pmops_runtime_resume(struct device *dev) 438 { 439 struct pci_dev *pdev = to_pci_dev(dev); 440 struct drm_device *drm_dev = pci_get_drvdata(pdev); 441 int ret; 442 443 if (!radeon_is_px(drm_dev)) 444 return -EINVAL; 445 446 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 447 448 if (radeon_is_atpx_hybrid() || 449 !radeon_has_atpx_dgpu_power_cntl()) 450 pci_set_power_state(pdev, PCI_D0); 451 pci_restore_state(pdev); 452 ret = pci_enable_device(pdev); 453 if (ret) 454 return ret; 455 pci_set_master(pdev); 456 457 ret = radeon_resume_kms(drm_dev, false, false); 458 drm_kms_helper_poll_enable(drm_dev); 459 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 460 return 0; 461 } 462 463 static int radeon_pmops_runtime_idle(struct device *dev) 464 { 465 struct drm_device *drm_dev = dev_get_drvdata(dev); 466 struct drm_crtc *crtc; 467 468 if (!radeon_is_px(drm_dev)) { 469 pm_runtime_forbid(dev); 470 return -EBUSY; 471 } 472 473 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 474 if (crtc->enabled) { 475 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 476 return -EBUSY; 477 } 478 } 479 480 pm_runtime_mark_last_busy(dev); 481 pm_runtime_autosuspend(dev); 482 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 483 return 1; 484 } 485 486 long radeon_drm_ioctl(struct file *filp, 487 unsigned int cmd, unsigned long arg) 488 { 489 struct drm_file *file_priv = filp->private_data; 490 struct drm_device *dev; 491 long ret; 492 493 dev = file_priv->minor->dev; 494 ret = pm_runtime_get_sync(dev->dev); 495 if (ret < 0) { 496 pm_runtime_put_autosuspend(dev->dev); 497 return ret; 498 } 499 500 ret = drm_ioctl(filp, cmd, arg); 501 502 pm_runtime_mark_last_busy(dev->dev); 503 pm_runtime_put_autosuspend(dev->dev); 504 return ret; 505 } 506 507 #ifdef CONFIG_COMPAT 508 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 509 { 510 unsigned int nr = DRM_IOCTL_NR(cmd); 511 512 if (nr < DRM_COMMAND_BASE) 513 return drm_compat_ioctl(filp, cmd, arg); 514 515 return radeon_drm_ioctl(filp, cmd, arg); 516 } 517 #endif 518 519 static const struct dev_pm_ops radeon_pm_ops = { 520 .suspend = radeon_pmops_suspend, 521 .resume = radeon_pmops_resume, 522 .freeze = radeon_pmops_freeze, 523 .thaw = radeon_pmops_thaw, 524 .poweroff = radeon_pmops_freeze, 525 .restore = radeon_pmops_resume, 526 .runtime_suspend = radeon_pmops_runtime_suspend, 527 .runtime_resume = radeon_pmops_runtime_resume, 528 .runtime_idle = radeon_pmops_runtime_idle, 529 }; 530 531 static const struct file_operations radeon_driver_kms_fops = { 532 .owner = THIS_MODULE, 533 .open = drm_open, 534 .release = drm_release, 535 .unlocked_ioctl = radeon_drm_ioctl, 536 .mmap = drm_gem_mmap, 537 .poll = drm_poll, 538 .read = drm_read, 539 #ifdef CONFIG_COMPAT 540 .compat_ioctl = radeon_kms_compat_ioctl, 541 #endif 542 .fop_flags = FOP_UNSIGNED_OFFSET, 543 }; 544 545 static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 546 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 547 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 548 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 549 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 550 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 551 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 552 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 553 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 554 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 555 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 556 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 557 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 558 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 559 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 560 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 561 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 562 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 563 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 564 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 565 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 566 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 567 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 568 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 569 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 570 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 571 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 572 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 573 /* KMS */ 574 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 575 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 576 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 577 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 578 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 579 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 580 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 581 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 582 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 583 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 584 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 585 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 586 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 587 }; 588 589 static const struct drm_driver kms_driver = { 590 .driver_features = 591 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 592 .open = radeon_driver_open_kms, 593 .postclose = radeon_driver_postclose_kms, 594 .unload = radeon_driver_unload_kms, 595 .ioctls = radeon_ioctls_kms, 596 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 597 .dumb_create = radeon_mode_dumb_create, 598 .dumb_map_offset = radeon_mode_dumb_mmap, 599 .fops = &radeon_driver_kms_fops, 600 601 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 602 603 RADEON_FBDEV_DRIVER_OPS, 604 605 .name = DRIVER_NAME, 606 .desc = DRIVER_DESC, 607 .date = DRIVER_DATE, 608 .major = KMS_DRIVER_MAJOR, 609 .minor = KMS_DRIVER_MINOR, 610 .patchlevel = KMS_DRIVER_PATCHLEVEL, 611 }; 612 613 static struct pci_driver radeon_kms_pci_driver = { 614 .name = DRIVER_NAME, 615 .id_table = pciidlist, 616 .probe = radeon_pci_probe, 617 .remove = radeon_pci_remove, 618 .shutdown = radeon_pci_shutdown, 619 .driver.pm = &radeon_pm_ops, 620 }; 621 622 static int __init radeon_module_init(void) 623 { 624 if (drm_firmware_drivers_only() && radeon_modeset == -1) 625 radeon_modeset = 0; 626 627 if (radeon_modeset == 0) 628 return -EINVAL; 629 630 DRM_INFO("radeon kernel modesetting enabled.\n"); 631 radeon_register_atpx_handler(); 632 633 return pci_register_driver(&radeon_kms_pci_driver); 634 } 635 636 static void __exit radeon_module_exit(void) 637 { 638 pci_unregister_driver(&radeon_kms_pci_driver); 639 radeon_unregister_atpx_handler(); 640 mmu_notifier_synchronize(); 641 } 642 643 module_init(radeon_module_init); 644 module_exit(radeon_module_exit); 645 646 MODULE_AUTHOR(DRIVER_AUTHOR); 647 MODULE_DESCRIPTION(DRIVER_DESC); 648 MODULE_LICENSE("GPL and additional rights"); 649