1 /* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 #include <linux/aperture.h> 33 #include <linux/compat.h> 34 #include <linux/module.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/vga_switcheroo.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/pci.h> 39 40 #include <drm/clients/drm_client_setup.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_gem.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_pciids.h> 47 #include <drm/drm_probe_helper.h> 48 #include <drm/drm_vblank.h> 49 #include <drm/radeon_drm.h> 50 51 #include "radeon_drv.h" 52 #include "radeon.h" 53 #include "radeon_kms.h" 54 #include "radeon_ttm.h" 55 #include "radeon_device.h" 56 #include "radeon_prime.h" 57 58 /* 59 * KMS wrapper. 60 * - 2.0.0 - initial interface 61 * - 2.1.0 - add square tiling interface 62 * - 2.2.0 - add r6xx/r7xx const buffer support 63 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 64 * - 2.4.0 - add crtc id query 65 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 66 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 67 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 68 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 69 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 70 * 2.10.0 - fusion 2D tiling 71 * 2.11.0 - backend map, initial compute support for the CS checker 72 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 73 * 2.13.0 - virtual memory support, streamout 74 * 2.14.0 - add evergreen tiling informations 75 * 2.15.0 - add max_pipes query 76 * 2.16.0 - fix evergreen 2D tiled surface calculation 77 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 78 * 2.18.0 - r600-eg: allow "invalid" DB formats 79 * 2.19.0 - r600-eg: MSAA textures 80 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 81 * 2.21.0 - r600-r700: FMASK and CMASK 82 * 2.22.0 - r600 only: RESOLVE_BOX allowed 83 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 84 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 85 * 2.25.0 - eg+: new info request for num SE and num SH 86 * 2.26.0 - r600-eg: fix htile size computation 87 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 88 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 89 * 2.29.0 - R500 FP16 color clear registers 90 * 2.30.0 - fix for FMASK texturing 91 * 2.31.0 - Add fastfb support for rs690 92 * 2.32.0 - new info request for rings working 93 * 2.33.0 - Add SI tiling mode array query 94 * 2.34.0 - Add CIK tiling mode array query 95 * 2.35.0 - Add CIK macrotile mode array query 96 * 2.36.0 - Fix CIK DCE tiling setup 97 * 2.37.0 - allow GS ring setup on r6xx/r7xx 98 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 99 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 100 * 2.39.0 - Add INFO query for number of active CUs 101 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 102 * CS to GPU on >= r600 103 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 104 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 105 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 106 * 2.44.0 - SET_APPEND_CNT packet3 support 107 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 108 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 109 * 2.47.0 - Add UVD_NO_OP register support 110 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 111 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 112 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 113 * 2.51.0 - Add evergreen/cayman OpenGL 4.6 compatibility 114 */ 115 #define KMS_DRIVER_MAJOR 2 116 #define KMS_DRIVER_MINOR 51 117 #define KMS_DRIVER_PATCHLEVEL 0 118 119 int radeon_no_wb; 120 int radeon_modeset = -1; 121 int radeon_dynclks = -1; 122 int radeon_r4xx_atom; 123 int radeon_agpmode = -1; 124 int radeon_vram_limit; 125 int radeon_gart_size = -1; /* auto */ 126 int radeon_benchmarking; 127 int radeon_testing; 128 int radeon_connector_table; 129 int radeon_tv = 1; 130 int radeon_audio = -1; 131 int radeon_disp_priority; 132 int radeon_hw_i2c; 133 int radeon_pcie_gen2 = -1; 134 int radeon_msi = -1; 135 int radeon_lockup_timeout = 10000; 136 int radeon_fastfb; 137 int radeon_dpm = -1; 138 int radeon_aspm = -1; 139 int radeon_runtime_pm = -1; 140 int radeon_hard_reset; 141 int radeon_vm_size = 8; 142 int radeon_vm_block_size = -1; 143 int radeon_deep_color; 144 int radeon_use_pflipirq = 2; 145 int radeon_bapm = -1; 146 int radeon_backlight = -1; 147 int radeon_auxch = -1; 148 int radeon_uvd = 1; 149 int radeon_vce = 1; 150 151 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 152 module_param_named(no_wb, radeon_no_wb, int, 0444); 153 154 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 155 module_param_named(modeset, radeon_modeset, int, 0400); 156 157 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 158 module_param_named(dynclks, radeon_dynclks, int, 0444); 159 160 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 161 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 162 163 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 164 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 165 166 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 167 module_param_named(agpmode, radeon_agpmode, int, 0444); 168 169 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 170 module_param_named(gartsize, radeon_gart_size, int, 0600); 171 172 MODULE_PARM_DESC(benchmark, "Run benchmark"); 173 module_param_named(benchmark, radeon_benchmarking, int, 0444); 174 175 MODULE_PARM_DESC(test, "Run tests"); 176 module_param_named(test, radeon_testing, int, 0444); 177 178 MODULE_PARM_DESC(connector_table, "Force connector table"); 179 module_param_named(connector_table, radeon_connector_table, int, 0444); 180 181 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 182 module_param_named(tv, radeon_tv, int, 0444); 183 184 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 185 module_param_named(audio, radeon_audio, int, 0444); 186 187 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 188 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 189 190 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 191 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 192 193 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 194 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 195 196 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 197 module_param_named(msi, radeon_msi, int, 0444); 198 199 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 200 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 201 202 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 203 module_param_named(fastfb, radeon_fastfb, int, 0444); 204 205 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 206 module_param_named(dpm, radeon_dpm, int, 0444); 207 208 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 209 module_param_named(aspm, radeon_aspm, int, 0444); 210 211 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 212 module_param_named(runpm, radeon_runtime_pm, int, 0444); 213 214 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 215 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 216 217 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 218 module_param_named(vm_size, radeon_vm_size, int, 0444); 219 220 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 221 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 222 223 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 224 module_param_named(deep_color, radeon_deep_color, int, 0444); 225 226 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 227 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 228 229 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 230 module_param_named(bapm, radeon_bapm, int, 0444); 231 232 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 233 module_param_named(backlight, radeon_backlight, int, 0444); 234 235 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 236 module_param_named(auxch, radeon_auxch, int, 0444); 237 238 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 239 module_param_named(uvd, radeon_uvd, int, 0444); 240 241 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 242 module_param_named(vce, radeon_vce, int, 0444); 243 244 int radeon_si_support = -1; 245 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); 246 module_param_named(si_support, radeon_si_support, int, 0444); 247 248 int radeon_cik_support = -1; 249 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); 250 module_param_named(cik_support, radeon_cik_support, int, 0444); 251 252 static const struct pci_device_id pciidlist[] = { 253 radeon_PCI_IDS 254 }; 255 MODULE_DEVICE_TABLE(pci, pciidlist); 256 257 static const struct drm_driver kms_driver; 258 259 static bool radeon_support_enabled(struct device *dev, 260 const enum radeon_family family) 261 { 262 const char *gen; 263 int module_param = -1; 264 bool amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU); 265 bool support_by_default = true; 266 267 switch (family) { 268 case CHIP_TAHITI: 269 case CHIP_PITCAIRN: 270 case CHIP_VERDE: 271 case CHIP_OLAND: 272 case CHIP_HAINAN: 273 gen = "SI"; 274 module_param = radeon_si_support; 275 amdgpu_support_built &= IS_ENABLED(CONFIG_DRM_AMDGPU_SI); 276 support_by_default = false; 277 break; 278 279 case CHIP_BONAIRE: 280 case CHIP_HAWAII: 281 case CHIP_KAVERI: 282 case CHIP_KABINI: 283 case CHIP_MULLINS: 284 gen = "CIK"; 285 module_param = radeon_cik_support; 286 amdgpu_support_built &= IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); 287 support_by_default = false; 288 break; 289 290 default: 291 /* All other chips are supported by radeon only */ 292 return true; 293 } 294 295 if ((module_param == -1 && (support_by_default || !amdgpu_support_built)) || 296 module_param == 1) 297 return true; 298 299 if (!module_param) 300 dev_info(dev, "%s support disabled by module param\n", gen); 301 302 return false; 303 } 304 305 static int radeon_pci_probe(struct pci_dev *pdev, 306 const struct pci_device_id *ent) 307 { 308 unsigned long flags = 0; 309 struct drm_device *ddev; 310 struct radeon_device *rdev; 311 struct device *dev = &pdev->dev; 312 const struct drm_format_info *format; 313 int ret; 314 315 if (!ent) 316 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 317 318 flags = ent->driver_data; 319 320 if (!radeon_support_enabled(dev, flags & RADEON_FAMILY_MASK)) 321 return -ENODEV; 322 323 if (vga_switcheroo_client_probe_defer(pdev)) 324 return -EPROBE_DEFER; 325 326 /* Get rid of things like offb */ 327 ret = aperture_remove_conflicting_pci_devices(pdev, kms_driver.name); 328 if (ret) 329 return ret; 330 331 rdev = devm_drm_dev_alloc(dev, &kms_driver, typeof(*rdev), ddev); 332 if (IS_ERR(rdev)) 333 return PTR_ERR(rdev); 334 335 rdev->dev = dev; 336 rdev->pdev = pdev; 337 ddev = rdev_to_drm(rdev); 338 ddev->dev_private = rdev; 339 340 ret = pci_enable_device(pdev); 341 if (ret) 342 return ret; 343 344 pci_set_drvdata(pdev, ddev); 345 346 ret = radeon_driver_load_kms(ddev, flags); 347 if (ret) 348 goto err; 349 350 ret = drm_dev_register(ddev, flags); 351 if (ret) 352 goto err; 353 354 if (rdev->mc.real_vram_size <= (8 * 1024 * 1024)) 355 format = drm_format_info(DRM_FORMAT_C8); 356 else if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32 * 1024 * 1024)) 357 format = drm_format_info(DRM_FORMAT_RGB565); 358 else 359 format = NULL; 360 361 drm_client_setup(ddev, format); 362 363 return 0; 364 365 err: 366 pci_disable_device(pdev); 367 return ret; 368 } 369 370 static void 371 radeon_pci_shutdown(struct pci_dev *pdev) 372 { 373 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 374 /* 375 * Some adapters need to be suspended before a 376 * shutdown occurs in order to prevent an error 377 * during kexec, shutdown or reboot. 378 * Make this power and Loongson specific because 379 * it breaks some other boards. 380 */ 381 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 382 #endif 383 } 384 385 static int radeon_pmops_suspend(struct device *dev) 386 { 387 struct drm_device *drm_dev = dev_get_drvdata(dev); 388 389 return radeon_suspend_kms(drm_dev, true, true, false); 390 } 391 392 static int radeon_pmops_resume(struct device *dev) 393 { 394 struct drm_device *drm_dev = dev_get_drvdata(dev); 395 396 /* GPU comes up enabled by the bios on resume */ 397 if (radeon_is_px(drm_dev)) { 398 pm_runtime_disable(dev); 399 pm_runtime_set_active(dev); 400 pm_runtime_enable(dev); 401 } 402 403 return radeon_resume_kms(drm_dev, true, true); 404 } 405 406 static int radeon_pmops_freeze(struct device *dev) 407 { 408 struct drm_device *drm_dev = dev_get_drvdata(dev); 409 410 return radeon_suspend_kms(drm_dev, false, true, true); 411 } 412 413 static int radeon_pmops_thaw(struct device *dev) 414 { 415 struct drm_device *drm_dev = dev_get_drvdata(dev); 416 417 return radeon_resume_kms(drm_dev, false, true); 418 } 419 420 static int radeon_pmops_runtime_suspend(struct device *dev) 421 { 422 struct pci_dev *pdev = to_pci_dev(dev); 423 struct drm_device *drm_dev = pci_get_drvdata(pdev); 424 425 if (!radeon_is_px(drm_dev)) { 426 pm_runtime_forbid(dev); 427 return -EBUSY; 428 } 429 430 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 431 drm_kms_helper_poll_disable(drm_dev); 432 433 radeon_suspend_kms(drm_dev, false, false, false); 434 pci_save_state(pdev); 435 pci_disable_device(pdev); 436 pci_ignore_hotplug(pdev); 437 if (radeon_is_atpx_hybrid()) 438 pci_set_power_state(pdev, PCI_D3cold); 439 else if (!radeon_has_atpx_dgpu_power_cntl()) 440 pci_set_power_state(pdev, PCI_D3hot); 441 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 442 443 return 0; 444 } 445 446 static int radeon_pmops_runtime_resume(struct device *dev) 447 { 448 struct pci_dev *pdev = to_pci_dev(dev); 449 struct drm_device *drm_dev = pci_get_drvdata(pdev); 450 int ret; 451 452 if (!radeon_is_px(drm_dev)) 453 return -EINVAL; 454 455 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 456 457 if (radeon_is_atpx_hybrid() || 458 !radeon_has_atpx_dgpu_power_cntl()) 459 pci_set_power_state(pdev, PCI_D0); 460 pci_restore_state(pdev); 461 ret = pci_enable_device(pdev); 462 if (ret) 463 return ret; 464 pci_set_master(pdev); 465 466 ret = radeon_resume_kms(drm_dev, false, false); 467 drm_kms_helper_poll_enable(drm_dev); 468 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 469 return 0; 470 } 471 472 static int radeon_pmops_runtime_idle(struct device *dev) 473 { 474 struct drm_device *drm_dev = dev_get_drvdata(dev); 475 struct drm_crtc *crtc; 476 477 if (!radeon_is_px(drm_dev)) { 478 pm_runtime_forbid(dev); 479 return -EBUSY; 480 } 481 482 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 483 if (crtc->enabled) { 484 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 485 return -EBUSY; 486 } 487 } 488 489 pm_runtime_autosuspend(dev); 490 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 491 return 1; 492 } 493 494 long radeon_drm_ioctl(struct file *filp, 495 unsigned int cmd, unsigned long arg) 496 { 497 struct drm_file *file_priv = filp->private_data; 498 struct drm_device *dev; 499 long ret; 500 501 dev = file_priv->minor->dev; 502 ret = pm_runtime_get_sync(dev->dev); 503 if (ret < 0) { 504 pm_runtime_put_autosuspend(dev->dev); 505 return ret; 506 } 507 508 ret = drm_ioctl(filp, cmd, arg); 509 510 pm_runtime_put_autosuspend(dev->dev); 511 return ret; 512 } 513 514 #ifdef CONFIG_COMPAT 515 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 516 { 517 unsigned int nr = DRM_IOCTL_NR(cmd); 518 519 if (nr < DRM_COMMAND_BASE) 520 return drm_compat_ioctl(filp, cmd, arg); 521 522 return radeon_drm_ioctl(filp, cmd, arg); 523 } 524 #endif 525 526 static const struct dev_pm_ops radeon_pm_ops = { 527 .suspend = radeon_pmops_suspend, 528 .resume = radeon_pmops_resume, 529 .freeze = radeon_pmops_freeze, 530 .thaw = radeon_pmops_thaw, 531 .poweroff = radeon_pmops_freeze, 532 .restore = radeon_pmops_resume, 533 .runtime_suspend = radeon_pmops_runtime_suspend, 534 .runtime_resume = radeon_pmops_runtime_resume, 535 .runtime_idle = radeon_pmops_runtime_idle, 536 }; 537 538 static const struct file_operations radeon_driver_kms_fops = { 539 .owner = THIS_MODULE, 540 .open = drm_open, 541 .release = drm_release, 542 .unlocked_ioctl = radeon_drm_ioctl, 543 .mmap = drm_gem_mmap, 544 .poll = drm_poll, 545 .read = drm_read, 546 #ifdef CONFIG_COMPAT 547 .compat_ioctl = radeon_kms_compat_ioctl, 548 #endif 549 .fop_flags = FOP_UNSIGNED_OFFSET, 550 }; 551 552 static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 553 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 554 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 555 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 556 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 557 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 558 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 559 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 560 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 561 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 562 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 563 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 564 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 565 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 566 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 567 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 568 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 569 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 570 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 571 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 572 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 573 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 574 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 575 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 576 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 577 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 578 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 579 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 580 /* KMS */ 581 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 582 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 583 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 584 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 585 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 586 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 587 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 588 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 589 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 590 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 591 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 592 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 593 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 594 }; 595 596 static const struct drm_driver kms_driver = { 597 .driver_features = 598 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 599 .open = radeon_driver_open_kms, 600 .postclose = radeon_driver_postclose_kms, 601 .unload = radeon_driver_unload_kms, 602 .ioctls = radeon_ioctls_kms, 603 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 604 .dumb_create = radeon_mode_dumb_create, 605 .dumb_map_offset = radeon_mode_dumb_mmap, 606 .fops = &radeon_driver_kms_fops, 607 608 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 609 610 RADEON_FBDEV_DRIVER_OPS, 611 612 .name = DRIVER_NAME, 613 .desc = DRIVER_DESC, 614 .major = KMS_DRIVER_MAJOR, 615 .minor = KMS_DRIVER_MINOR, 616 .patchlevel = KMS_DRIVER_PATCHLEVEL, 617 }; 618 619 static struct pci_driver radeon_kms_pci_driver = { 620 .name = DRIVER_NAME, 621 .id_table = pciidlist, 622 .probe = radeon_pci_probe, 623 .shutdown = radeon_pci_shutdown, 624 .driver.pm = &radeon_pm_ops, 625 }; 626 627 static int __init radeon_module_init(void) 628 { 629 if (drm_firmware_drivers_only() && radeon_modeset == -1) 630 radeon_modeset = 0; 631 632 if (radeon_modeset == 0) 633 return -EINVAL; 634 635 DRM_INFO("radeon kernel modesetting enabled.\n"); 636 radeon_register_atpx_handler(); 637 638 return pci_register_driver(&radeon_kms_pci_driver); 639 } 640 641 static void __exit radeon_module_exit(void) 642 { 643 pci_unregister_driver(&radeon_kms_pci_driver); 644 radeon_unregister_atpx_handler(); 645 mmu_notifier_synchronize(); 646 } 647 648 module_init(radeon_module_init); 649 module_exit(radeon_module_exit); 650 651 MODULE_AUTHOR(DRIVER_AUTHOR); 652 MODULE_DESCRIPTION(DRIVER_DESC); 653 MODULE_LICENSE("GPL and additional rights"); 654